A composite spacer layer vertical channel thin-film transistor and its fabrication method

Abstract

This invention relates to a composite spacer layer vertical channel thin-film transistor and its fabrication method, comprising: a substrate, a source, a composite spacer layer, a drain, an active layer, a gate insulating layer, and a gate. The substrate, source, composite spacer layer, and drain are arranged sequentially from bottom to top. An active layer is disposed on the drain-composite spacer layer sidewall-source surface. A gate insulating layer and a gate are disposed on the active layer. The composite spacer layer includes an organic layer and several high-k dielectric layers. One side of the organic layer is connected to the source, and the other side is connected to the several sequentially arranged high-k dielectric layers. This invention disrupts the stress-induced leakage current SILC electric field distribution in the spacer layer through the heterogeneous interface formed by different high-k dielectric layers. Each high-k dielectric layer has good dielectric strength, ensuring insulation between the source and drain when the channel length is less than 100 nanometers. Furthermore, the sidewall roughness of the composite spacer layer is significantly better than that of the sidewall formed by etching of traditional oxides, which helps to enhance the electrical performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of display device manufacturing and application technology, specifically relating to a composite spacer layer vertical channel thin film transistor and its preparation method. Background Technology

[0002] With the development of display technology, high-resolution, low-latency display screens provide excellent human-computer interaction experiences in various scenarios. Vertical-channel thin-film transistors (VTFTs), due to their smaller, sub-micron-scale structure, represent a cutting-edge technology for realizing next-generation high-resolution displays. Compared to traditional planar TFTs, the performance of VTFTs is mainly constrained by two key factors: firstly, the interface defects at the spacer / active layer affect the channel interface quality before carrier transport; and secondly, the short-channel effect (SCE), particularly drain-induced barrier reduction (DIBL). The DIBL effect in VTFTs is not solely due to the reduced channel size; in VTFTs, the source and drain may also exhibit a significant DIBL effect through stress-induced leakage current (SILC) in the spacer layer, especially when the spacer layer is less than 100 nanometers thick. In such cases, the silicon oxide spacer layer struggles to maintain a low level of SILC, or under extreme conditions, source-drain breakdown may occur directly. Existing studies have shown that high-quality alumina spacers can be prepared by atomic layer deposition (ALD) to maintain low levels of SILC even at thicknesses below 100 nanometers. However, there is still a minimum thickness limit to maintain SILC at an acceptable level. Furthermore, the roughness of the sidewalls of the etched spacer layer and the carrier transport interface stacked on it is much greater than that of planar TFTs. As a result, the performance of VTFTs is currently far behind that of traditional planar TFTs. Summary of the Invention

[0003] In order to overcome the above-mentioned problems in the prior art, the present invention provides a composite spacer layer vertical channel thin film transistor and its fabrication method, which is used to solve the problem of strong DIBL effect or source-drain breakdown caused by high SILC level when the spacer layer is less than 100 nanometers thick in the prior art.

[0004] A composite spacer layer vertical channel thin-film transistor includes: a substrate, a source, a composite spacer layer, a drain, an active layer, a gate insulating layer, and a gate. The source is disposed on the substrate, the composite spacer layer is disposed on the source, the drain is disposed on the composite spacer layer, the active layer is disposed on the drain-composite spacer layer sidewall-source surface, and the gate insulating layer and gate are disposed on the active layer. The composite spacer layer includes an organic layer and several high-k dielectric layers. One side of the organic layer is connected to the source, and the other side is connected to several sequentially disposed high-k dielectric layers.

[0005] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the substrate is rigid or flexible.

[0006] In addition to the aspects and any possible implementations described above, an implementation is further provided in which the organic layer material includes, but is not limited to, diluted positive photoresist, negative photoresist, polymethyl methacrylate (PMMA), or polyimide (PI).

[0007] In addition to the aspects described above and any possible implementations, an implementation is further provided in which the high-k dielectric layer material includes, but is not limited to, alumina, hafnium oxide, or titanium oxide.

[0008] In addition to the aspects described above and any possible implementations, a further implementation is provided in which the active layer material is a metal oxide semiconductor or a low-dimensional semiconductor material.

[0009] The present invention also provides a method for fabricating a composite spacer layer vertical channel thin film transistor, the method comprising the steps of: S1. forming a patterned source on a substrate;

[0010] S2. Prepare the organic layer in the composite spacer layer on the source electrode and anneal it;

[0011] S3. Prepare several high-k dielectric layers of patterned composite spacers on an organic layer;

[0012] S4. Fabricate a patterned drain on the last high-k dielectric layer of the composite spacer layer;

[0013] S5. The organic layer is ashed using several high-k dielectric layers and drain as ashing masks, the organic layer is patterned and the sidewalls of the organic part are formed;

[0014] S6. A patterned active layer is fabricated on the drain, drain-composite spacer layer sidewall-source surface;

[0015] S7. A patterned gate insulating layer and gate are fabricated on the active layer, and then annealed.

[0016] In addition to the aspects and any possible implementations described above, an implementation is further provided in which the setting of the source or drain is performed by atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, or chemical spin coating.

[0017] In addition to the aspects and any possible implementations described above, an implementation is further provided in which the preparation in S2 is carried out by spin coating or spray coating.

[0018] In addition to the aspects and any possible implementations described above, an implementation is further provided in which the preparation in S6 includes using atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, or chemical spin coating.

[0019] In addition to the aspects and any possible implementations described above, an implementation is further provided in which the preparation in S7 is performed using atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, or chemical spin coating.

[0020] Beneficial effects of the present invention

[0021] The present invention discloses a composite spacer layer vertical channel thin-film transistor (SILC), comprising: a substrate, a source, a composite spacer layer, a drain, an active layer, a gate insulating layer, and a gate. The active and drain electrodes are disposed on the substrate, the composite spacer layer is disposed on the source, the drain electrode is disposed on the composite spacer layer, the active layer is disposed on the drain-composite spacer layer sidewall-source surface, and the gate insulating layer and gate are disposed on the active layer. The composite spacer layer comprises an organic layer and several high-k dielectric layers. One side of the organic layer is connected to the source, and the other side is connected to several sequentially disposed high-k dielectric layers. The present invention disrupts the electric field distribution of SILC in the spacer layer through the heterogeneous interface formed by different high-k dielectric layers, and each high-k dielectric layer possesses good dielectric strength, ensuring insulation between the source and drain when the channel length is less than 100 nanometers, thereby significantly enhancing the device's electrical performance. Regarding sidewall roughness: the portion formed by the organic layer in the spacer layer reduces the overall roughness of the spacer layer sidewalls, reducing the defect density of the carrier transport interface formed by subsequent stacking. Attached Figure Description

[0022] Figure 1 The middle section is a flowchart of the preparation method of the present invention;

[0023] Figure 2 The electrode area is 1 mm. 2 A comparison of the dielectric strength of a metal-insulator-metal structure composite spacer layer and each layer thereof with that of a composite spacer layer of the same thickness prepared by thermal oxidative silicon and atomic deposition of a high-k dielectric layer.

[0024] Figure 3 This is a graph showing the results of the root mean square roughness (RMS) test of the sidewall of the composite spacer layer using atomic force microscopy in height sensor mode.

[0025] Figure 4 This is a structural diagram of the fabricated device. Detailed Implementation

[0026] To better understand the technical solution of this invention, the content of this invention includes, but is not limited to, the specific embodiments described below. Similar technologies and methods should be considered within the scope of protection of this invention. To make the technical problems to be solved, the technical solutions, and advantages of this invention clearer, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0027] It should be understood that the embodiments described in this invention are merely some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0028] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0029] like Figure 1 As shown, this invention provides a specific method for fabricating a composite spacer layer vertical channel thin-film transistor.

[0030] Includes the following steps:

[0031] Step 1. Substrate, wherein the substrate includes, but is not limited to, various organic and inorganic, rigid and flexible substrates;

[0032] Step 2. Deposit a source electrode, wherein the source electrode is disposed on a substrate, and the deposition method used includes, but is not limited to, physical and chemical methods such as atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, and chemical spin coating;

[0033] Step 3: Prepare the organic layer in the composite spacer layer and anneal it. The organic layer is placed on the source electrode and then annealed. The deposition preparation method used includes, but is not limited to, spin coating, spraying, etc. The organic layer includes, but is not limited to, positive adhesive (such as AZ series), negative adhesive (such as SU-8), polymethyl methacrylate (PMMA), polyimide (PI), etc. The purpose is to make the RMS of the sidewalls after the organic layer is ashed better than that of the sidewalls etched by traditional oxide materials, which is beneficial to improving device performance.

[0034] Step 4: Prepare the high-k dielectric layer and drain in the composite spacer layer. Several high-k dielectric layers can be prepared and deposited on the organic layer, ranging from two to five layers. This invention preferably uses three layers, such as high-k dielectric layers one, two, and three, where adjacent layers are heterogeneous (ABA structure) with a thickness of 5-20 nm. Patterning is then performed on these layers, i.e., creating the desired pattern. Preparation methods include, but are not limited to, atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, chemical spin coating, and other physical and chemical methods. Patterning methods include, but are not limited to, photolithography lift-off and mask patterning. The materials used for high-k dielectric layers one, two, and three include, but are not limited to, alumina, hafnium oxide, and titanium oxide.

[0035] Step 5: Plasma ashing of the organic layer: Plasma ashing is an industry-standard process for removing organic residues. It involves non-directional etching using plasma at a power of up to 100W, meaning areas covered by a mask will not be cleaned by plasma contact, and vice versa. This masked cleaning of the organic layer replaces traditional dry etching, resulting in better sidewall roughness.

[0036] The ashing gas includes, but is not limited to, oxygen, argon, nitrogen and their mixtures. In step 4, the high-k dielectric layers one, two, three and the drain electrode serve as the ashing mask for this step, forming the sidewalls of the organic layer.

[0037] Step 6: Prepare the active layer. The materials include, but are not limited to, metal oxide semiconductors, low-dimensional semiconductor materials, etc. The preparation methods include, but are not limited to, atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, chemical spin coating and other physical and chemical methods.

[0038] Step 8: Prepare the gate insulating layer. The deposition methods used include, but are not limited to, atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, chemical spin coating, and other physical and chemical methods. The materials include, but are not limited to, silicon dioxide, aluminum oxide, hafnium oxide, etc.

[0039] The fabrication sequence of the aforementioned composite spacer thin-film transistor includes, but is not limited to, the sequence described in this invention; other sequences are also feasible. Diluted photoresist or PI / PMMA is spin-coated or spray-coated onto the surface of the prepared sample. The organic layer is annealed and cured; curing is performed to prevent further deformation by drying the solvent in the organic solution. Three patterned high-k dielectric layers are fabricated on the entire surface of the organic layer, using an ABA material structure to ensure that adjacent layers are heterogeneous interfaces of different materials. After patterning these high-k layers, the drain electrode is simultaneously patterned on the outermost surface of the high-k layer. Using the stack formed by the three high-k layers and the drain electrode as a mask, the layer is ashed in a plasma cleaner to form the sidewalls of the organic layer in the composite spacer layer. At this point, the fabrication of the composite spacer layer is complete, forming the steps of the VTFT.

[0040] like Figure 1 As shown, the vertical arrows represent the deposition process of the film layer, and the oblique arrows represent the ashing plasma.

[0041] As an embodiment disclosed in this invention, such as Figure 4As shown, this invention also provides a composite spacer layer vertical channel thin-film transistor, obtained using the fabrication method of this invention. It includes a substrate 1, a source 2, a composite spacer layer 3, a drain 4, an active layer 5, a gate insulating layer 6, and a gate 7. The source 2 is disposed on the substrate 1, the composite spacer layer 3 is disposed on the source 2, the drain 4 is disposed on the composite spacer layer 3, the active layer 5 is disposed on the drain-composite spacer layer sidewall-source surface, and the gate insulating layer 6 and gate 7 are disposed on the active layer 5. The composite spacer layer 3 includes an organic layer and several high-k dielectric layers. One side of the organic layer is connected to the source 2, and the other side is connected to several sequentially disposed high-k dielectric layers. In the composite spacer layer 3, the organic layer is first fully covered. The high-k layer and drain are patterned using photolithography or a mask. After the high-k layer and drain are fabricated, they are used as mask patterns, and plasma ashing is used to pattern the organic layer, partially covering it. All film layers in the entire device are patterned, with partial coverage at their designated positions.

[0042] Furthermore, the high-k dielectric layer in the composite spacer layer of this invention can be a multi-layered structure, consisting of alternating layers of two different high-k dielectric materials or periodically stacked layers of multiple high-k dielectric materials. The principle is to form multiple heterojunction interfaces to disrupt the electric field distribution of SILC. The composite spacer layer is sequentially composed of an organic layer, a first high-k dielectric layer, a second high-k dielectric layer, and a third high-k dielectric layer. This composite spacer layer, through multiple heterojunctions and the high dielectric strength of the high-k dielectric material, ensures that the vertical channel thin-film transistor does not experience source-drain breakdown in sub-100 nm channel lengths, maintains a low level of stress-induced leakage current, and suppresses drain-induced barrier reduction. Simultaneously, the annealed photoresist portion provides better sidewall roughness for the composite spacer layer, improving the back channel interface quality of the device and effectively enhancing the electrical performance of the vertical channel thin-film transistor, thus expanding its application prospects in next-generation high-resolution displays. Figure 2As shown, taking a diluted I-line photoresist PR DongjingDSP-i100 45nm (thickness) / sputtered alumina 20nm (thickness) / sputtered hafnium oxide 10nm (thickness) / sputtered alumina 5nm (thickness) composite spacer layer as an example, the dielectric breakdown experiments of each layer structure are compared with its constituent 80nm composite spacer layer SILC and a thermally oxidized silicon spacer layer of the same thickness, or with a high-k dielectric layer structure prepared by a more advanced atomic layer deposition (ALD) process for MIM structures (metal-insulator-metal structures, where the metal area corresponds to the electrode contact area of ​​the VTFT device). The blue curve Spacer indicates that the composite spacer layer of the present invention, prepared by magnetron sputtering technology with a high-k dielectric layer, did not break down within the common VTFT bias range of 0-2.5V and maintained a low leakage current level. The comparison shows that although the existing magnetron sputtering composite spacer is not as good as the same structure prepared by the traditional thermal oxysilicon spacer or ALD process (although ALD is a better embodiment of the present invention), the present invention has better sidewall roughness than the traditional thermal oxysilicon spacer, provides a better quality front channel stack, and the leakage current is within the range that does not affect the normal off-state current of the device. Overall, it has better electrical performance than traditional thermal oxysilicon and silicon oxide VTFTs prepared by PECVD. Figure 2 The black, red, and green curves represent the dielectric properties of some components of the composite spacer layer. They demonstrate that each component alone cannot maintain dielectric insulation; they need to be combined to achieve the result shown by the blue curve, thus meeting the device's requirements. The light blue curve represents the insulation performance of a commonly used spacer layer in the industry, offering better insulation performance, but with significantly higher sidewall roughness, which is detrimental to the device's electrical performance. The purple curve represents the result of further process optimization in this invention, yielding even better results.

[0043] like Figure 3 The image shows the AFM test results for the sidewall of the composite spacer layer consisting of I-line PR 45nm / sputtered alumina 20nm / sputtered hafnium oxide 10nm / sputtered alumina 5nm.

[0044] The preparation process is illustrated below with an example:

[0045] 1. Clean the thermo-oxidized silicon substrate by immersing it in acetone solution and sonicating it at 70W for 5 minutes. Then, clean the substrate in isopropanol solution for 1 minute and finally perform plasma cleaning in an argon atmosphere for 5 minutes (Ar: 5sccm 50W).

[0046] 2. Deposit the patterned source electrode: Spin-coat Dongjin DSP-i100 photoresist at 500 rpm for 20 seconds, pre-bake at 100℃ for 30 seconds, align with the desired area of ​​the source electrode, expose with I-line for 30 seconds, post-bake for 20 seconds, and after development, place the sample in a thermal evaporation coating machine. Evaporate the vacuum to 5e-4 Pa, and heat the aluminum particles in the evaporation boat to deposit a 30 nm thick aluminum film. Remove the sample and ultrasonically peel off the photoresist and the aluminum film adhering to its surface in an acetone solution, leaving the desired patterned aluminum source electrode.

[0047] 3. Prepare the organic layer: Dilute the diluted Dongjin DSP-i100 photoresist with PGMEA solvent at a volume ratio of 4:1 (photoresist), pre-rotate at 500 rpm for 5 seconds, spin at 3000 rpm for 15 seconds to form a photoresist film of about 80 nm. Bake at a gradient temperature of 100-120℃ for 40 minutes, and then anneal the sample in a tube furnace at 300℃ for 2 hours. At this time, the photoresist film is about 45 nm.

[0048] 4. Fabricate patterned high-k dielectric layer and drain. Spin-coat Dongjin DSP-i100 photoresist on the sample surface at 500 rpm for 20 s, pre-bake at 100℃ for 30 s, align the required area of ​​the composite spacer layer, expose on I-line for 30 s, post-bake for 20 s, and develop. Then place the sample in a magnetron sputtering coating machine, evacuate to 3e-3 Pa, introduce argon gas at 35 sccm and oxygen gas at 7 sccm, set the RF power to 200 W, turn on the RF power at 2 Pa, check for ignition, adjust the chamber pressure to the working pressure of 4e-1 Pa, and sputter a 20 nm thick alumina film as a high-k dielectric layer. Switch to hafnium oxide target, introduce argon gas at 35 sccm and oxygen gas at 3 sccm, set the RF power to 200 W, turn on the RF power at 2 Pa, check for ignition, adjust the chamber pressure to the working pressure of 3e-1 Pa, and sputter a 1 nm thick alumina film as a high-k dielectric layer. A 0 nm hafnium oxide film was sputtered as the second high-k dielectric layer. Switching back to the alumina target, argon gas was introduced at 35 sccm and oxygen at 3 sccm. The RF power was 100 W, and the RF power was turned on at 2 Pa. After checking for ignition, the chamber pressure was adjusted to the working pressure of 3e⁻¹ Pa. A 5 nm thick alumina film was sputtered as the third high-k dielectric layer. Switching to a DC aluminum target, argon gas was introduced at 20 sccm. The DC power was turned on at 2 Pa and controlled at 200 W. After checking for ignition, the chamber pressure was adjusted to the working pressure of 4e⁻¹ Pa. A 30 nm thick aluminum film was sputtered as the drain. The sample was then placed in a PGMEA solution and ultrasonically exfoliated to form a patterned high-k dielectric layer / drain stack region.

[0049] 5. Using the patterned high-k dielectric layer / drain stack region from step 4 as a mask, place the sample in a plasma cleaner, introduce argon gas for 5 sccm, aerate at 50 W for 3 min, then introduce oxygen gas for 5 sccm, aerate at 10 W for 1 min to complete the preparation of the organic layer sidewall.

[0050] 6. To prepare the patterned active layer, spin-coat the sample surface with Dongjin DSP-i100 photoresist at 500 rpm for 20 seconds, pre-bake at 100℃ for 30 seconds, align the desired active layer area, expose with I-line for 30 seconds, post-bake for 20 seconds, and develop. Place the sample in the magnetron sputtering chamber, evacuate to 3e-3 Pa, introduce argon gas at 30 sccm and oxygen gas at 10 sccm, set the RF power to 45 W, turn on the RF power at 2 Pa, check for ignition, and adjust the chamber pressure to the working pressure of 4e-1 Pa. Sputter a 15 nm thick ITZO film with an ITZO target, and ultrasonically peel the sample in PGMEA solvent to form the patterned active layer region.

[0051] 7. Fabricate a patterned gate insulating layer. Spin-coat the sample surface with Dongjin DSP-i100 photoresist at 500 rpm for 20 seconds, pre-bake at 100℃ for 30 seconds, align the required area for the gate insulating layer, expose the I-line for 30 seconds, post-bake for 20 seconds, and develop. Place the sample in the magnetron sputtering chamber, evacuate to 3e-3 Pa, introduce argon at 35 sccm and oxygen at 7 sccm, set the RF power to 300 W, turn on the RF power at 2 Pa, check for ignition, and adjust the chamber pressure to the working pressure of 4e-1 Pa. Sputter a 30 nm thick alumina film using an alumina target as the gate insulating layer.

[0052] 8. Fabricate the patterned gate: Spin-coat the sample surface with Dongjin DSP-i100 photoresist at 500 rpm for 20 seconds, pre-bake at 100℃ for 30 seconds, align the required area for the gate by overlay, expose the I-line for 30 seconds, post-bake for 20 seconds, and develop. Place the sample in a thermal evaporation coating machine, evaporate a 30 nm thick layer of aluminum metal to 5e-4 Pa, and then ultrasonically peel it off in PGMEA solvent to form the gate pattern.

[0053] 9. Annealing treatment: Place the sample in a tube furnace and anneal at 300℃ for 2 hours. Remove the sample to complete device fabrication.

[0054] The foregoing description illustrates and describes several preferred embodiments of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A composite spacer layer vertical channel thin-film transistor, characterized in that, include: The device comprises a substrate, a source electrode, a composite spacer layer, a drain electrode, an active layer, a gate insulating layer, and a gate electrode. A source electrode is disposed on the substrate, a composite spacer layer is disposed on the source electrode, a drain electrode is disposed on the composite spacer layer, an active layer is disposed on the drain-composite spacer layer sidewall-source electrode surface, and a gate insulating layer and a gate electrode are disposed on the active layer. The composite spacer layer includes an organic layer and several high-k dielectric layers. One side of the organic layer is connected to the source electrode, and the other side is connected to several sequentially disposed high-k dielectric layers.

2. The transistor according to claim 1, characterized in that, The substrate can be rigid or flexible.

3. The transistor according to claim 1, characterized in that, The organic layer includes positive photoresist, negative photoresist, polymethyl methacrylate (PMMA), or polyimide (PI) with different dilution ratios.

4. The transistor according to claim 1, characterized in that, The high-k dielectric layer material includes aluminum oxide, hafnium oxide, or titanium oxide.

5. The transistor according to claim 1, characterized in that, The active layer material is a metal oxide semiconductor or a low-dimensional semiconductor material.

6. A method for fabricating a composite spacer layer vertical channel thin-film transistor, characterized in that, The method includes the following steps: S1. A source electrode is disposed on the substrate; S2. Prepare the organic layer in the composite spacer layer on the source electrode and perform annealing and curing treatment; S3. Prepare several high-k dielectric layers on the organic layer to form a composite spacer layer; S4. Fabricate the drain electrode on a high-k dielectric layer; S5. Using several high-k dielectric layers and drain as ashing masks, plasma ashing of the organic layer forms the sidewalls of the organic part; S6. An active layer is prepared on the continuous interface between the drain-composite spacer layer sidewall and the source. S7. Prepare a gate insulating layer and a gate on the active layer, and anneal them.

7. The preparation method according to claim 6, characterized in that, The source / drain is configured using atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, or chemical spin coating.

8. The preparation method according to claim 6, characterized in that, In S2, the preparation is carried out by spin coating or spray coating.

9. The preparation method according to claim 6, characterized in that, Preparation in S3 includes methods such as atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, thermal evaporation, electron beam evaporation, or chemical spin coating.

10. The preparation method according to claim 6, characterized in that, The preparation in S6 is carried out by atomic layer deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, or chemical spin coating.

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