A semiconductor device and its manufacturing method

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology. The device reduces the spacing between a first transistor and a second transistor along the thickness direction of the substrate, thereby lowering the parasitic resistance and capacitance of the semiconductor device and improving its performance. The semiconductor device includes a substrate, a first transistor, and a second transistor. The first and second transistors are spaced apart on the substrate along its thickness direction, with the second transistor positioned above the first transistor. The first active structure of the first transistor and the second active structure of the second transistor are offset along a direction parallel to the substrate surface. Both the first and second active structures include a channel region and source / drain regions located on either side of the channel region along its length. The manufacturing method of the semiconductor device is used to manufacture the aforementioned semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Three-dimensional stacked transistors consist of two transistors stacked vertically along the thickness direction of the substrate, eliminating the lateral spacing between the two transistors. This allows for a further increase in the effective channel width, thereby improving the performance and integration of semiconductor devices.

[0003] However, in existing three-dimensional stacked transistors, the spacing between the upper and lower transistors along the substrate thickness direction is relatively large, which leads to an increase in the parasitic resistance and parasitic capacitance of the semiconductor device, which is not conducive to improving the working performance of the semiconductor device. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can reduce the spacing between the first transistor and the second transistor along the substrate thickness, thereby reducing the parasitic resistance and parasitic capacitance of the semiconductor device and improving the working performance of the semiconductor device.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor device comprising: a substrate, a first transistor, and a second transistor. The first transistor and the second transistor are disposed on the substrate at a distance along the thickness direction of the substrate, with the second transistor positioned above the first transistor. The first active structure of the first transistor and the second active structure of the second transistor are offset along a direction parallel to the surface of the substrate. Both the first and second active structures include a channel region and source / drain regions located on both sides of the channel region along its length direction.

[0006] When the above technical solution is adopted, the semiconductor device includes a first transistor and a second transistor that are spaced apart along the thickness direction of the substrate. Clearly, the first transistor and the second transistor can constitute a three-dimensional stacked transistor (CFET device) to improve the integration density of the semiconductor device.

[0007] Furthermore, the first active structure of the first transistor and the second active structure of the second transistor are staggered along a direction parallel to the substrate surface. In this case, the two source-drain regions located on the same side along the length of the gate stack structure in the first and second transistors can be staggered along a direction parallel to the substrate surface. In other words, along the thickness direction of the substrate, the lower source-drain region can be exposed outside the upper source-drain region. This facilitates the subsequent generation of source-drain contact structures to be electrically connected to the corresponding source-drain regions through the staggered spacing between the two. This not only prevents device failure caused by overlapping of different source-drain contact structures, but also eliminates the need to set a conductive structure for lead-out between the two. This reduces the thickness of the isolation material (which may be the first isolation structure mentioned below) used to electrically insulate the source-drain regions of the first and second transistors, thereby reducing the parasitic capacitance of the semiconductor device. At the same time, because the thickness of the isolation material is smaller, the length of the source-drain contact structure used to lead out the lower source-drain region upward (or the length of the source-drain contact structure used to lead out the upper source-drain region downward) is also smaller, reducing the parasitic resistance of the semiconductor device and improving the operating performance of the semiconductor device.

[0008] In one example, the semiconductor device further includes a first isolation structure. Along the thickness direction of the substrate, the first isolation structure is disposed between the source / drain regions included in the first active structure and the source / drain regions included in the second active structure.

[0009] In one example, the thickness of the first isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm along the thickness direction of the substrate.

[0010] In one example, the parts of the first isolation structure are formed as a single unit.

[0011] In one example, the semiconductor device further includes a first semiconductor portion disposed on a substrate, and the first semiconductor portion and the first active structure are laterally distributed along the substrate surface. A second active structure is disposed above the first semiconductor portion. A first isolation structure directly covers both sides of the first semiconductor portion along its length direction and covers the source / drain regions included in the first active structure, and the first isolation structure is located below the source / drain regions included in the second active structure.

[0012] In one example, the channel region of the first active structure is distributed in parallel with the first semiconductor portion.

[0013] In one example, the channel region of the first active structure has the same shape and / or material as the first semiconductor portion.

[0014] In one example, the semiconductor device further includes a second semiconductor portion disposed above the first active structure, the second semiconductor portion and the second active structure being laterally distributed along a surface direction parallel to the substrate.

[0015] In one example, the channel region of the second active structure is distributed in parallel with the second semiconductor portion.

[0016] In one example, the second active structure includes a channel region that has the same shape and / or material as the second semiconductor portion.

[0017] In one example, where the semiconductor device further includes a first semiconductor portion, the channel region of the second active structure is aligned with the first semiconductor portion.

[0018] In one example, the channel region of the first active structure is aligned with the second semiconductor portion.

[0019] In one example, the first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure. The first source-drain contact structure is electrically contacted with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is electrically contacted with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the gate stack structure included in the first transistor and / or the second transistor, and are spaced apart along the surface direction of the substrate. The first source-drain contact structure and the second source-drain contact structure extend along a surface direction perpendicular to the substrate.

[0020] In one example, the first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the upper surface of the source-drain region included in the first active structure and the second active structure, respectively. Alternatively, the first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the lower surface of the source-drain region included in the first active structure and the second active structure, respectively.

[0021] In one example, the first transistor and the second transistor further include a third source-drain contact structure. The third source-drain contact structure includes a vertical extension and a lateral extension electrically contacting the vertical extension. The vertical extension is located above and electrically contacting the other source-drain region included in the first active structure. The lateral extension is located above or below the other source-drain region included in the second active structure and serves to electrically connect the vertical extension to the other source-drain region included in the second active structure.

[0022] In one example, the vertical extension extends along a surface direction perpendicular to the substrate.

[0023] In one example, the first and second transistors have opposite conductivity types.

[0024] In one example, along the width direction of the channel region, the spacing between the channel region included in the first active structure and the channel region included in the second active structure is greater than or equal to 10 nm and less than or equal to 40 nm.

[0025] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: firstly, forming a first fin structure and a second fin structure on a substrate. The first fin structure and the second fin structure are spaced apart along a direction parallel to the surface of the substrate. Along the thickness direction of the substrate, each of the first fin structure and the second fin structure includes a lower fin portion, a semiconductor isolation portion, and an upper fin portion sequentially disposed therefrom. Next, the upper fin portion of the first fin structure and the second fin structure is protected, and source / drain regions are formed epitaxially on both sides of the lower fin portion of the first fin structure and the second fin structure. Next, the source / drain regions on both sides of the lower fin portion of the second fin structure are etched away. Next, the lower fin portion of the first fin structure and the second fin structure are protected, and source / drain regions are formed epitaxially on both sides of the upper fin portion of the first fin structure and the second fin structure. Next, the source / drain regions on both sides of the upper fin portion of the first fin structure are etched away.

[0026] In one example, protecting the upper fin portion of the first and second fin structures includes: forming a first mask structure spanning the first and second fin structures. Next, etching away portions of the first and second fin structures exposed outside the first mask structure. Next, forming a second mask structure on a substrate covering both sides of the lower fin portion of the first and second fin structures along their length. Next, forming a third mask structure covering both sides of the upper fin portion of the first and second fin structures along their length; the material of the third mask structure is different from the material of the second mask structure. Next, selectively removing the second mask structure.

[0027] In one example, protecting the lower fin portion of the first fin structure and the second fin structure includes forming a first isolation structure covering both sides of the lower fin portion of the second fin structure along its length and covering the formed source / drain region.

[0028] In one example, after etching away the source and drain regions on both sides of the upper fin of the first fin structure, the method for manufacturing the semiconductor device further includes: using a semiconductor process to form a first transistor based on the remaining lower fin in the first fin structure and the source and drain regions adjacent to it, and to form a second transistor based on the remaining upper fin in the second fin structure and the source and drain regions adjacent to it.

[0029] In one example, after forming the first transistor and the second transistor, the method of manufacturing the semiconductor device further includes: forming a first source-drain contact structure electrically contacting one of the source-drain regions included in the first transistor; forming a second source-drain contact structure electrically contacting one of the source-drain regions included in the second transistor; the first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the gate stack structure included in the first transistor and / or the second transistor, and are spaced apart; the first source-drain contact structure extends along a surface direction perpendicular to the substrate.

[0030] In one example, after forming the first transistor and the second transistor, the method of manufacturing the semiconductor device further includes: forming a third source-drain contact structure that is electrically connected to both the other source-drain region included in the first transistor and the other source-drain region included in the second transistor; the third source-drain contact structure includes a vertical extension and a lateral extension electrically connected to the vertical extension; the vertical extension is located above and electrically connected to the other source-drain region included in the first transistor; the lateral extension is located above or below the other source-drain region included in the second transistor and is used to electrically connect the vertical extension to the other source-drain region included in the second transistor.

[0031] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0033] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0034] Figure 2 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0035] Figure 3 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 3 ;

[0036] Figure 4 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 4 ;

[0037] Figure 5A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 5 ;

[0038] Figure 6 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 6 ;

[0039] Figure 7 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 7 ;

[0040] Figure 8 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 8 ;

[0041] Figure 9 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 9 ;

[0042] Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 ;

[0043] Figure 11 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 one;

[0044] Figure 12 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 two;

[0045] Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 three;

[0046] Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 Four;

[0047] Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 five;

[0048] Figure 16 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 six;

[0049] Figure 17 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 seven;

[0050] Figure 18 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 10 eight.

[0051] Reference numerals: 11 is the substrate, 12 is the first transistor, 13 is the second transistor, 14 is the first isolation structure, 15 is the channel region, 16 is the source-drain region, 17 is the gate stack structure, 18 is the gate sidewall, 19 is the first well region, 20 is the second well region, 21 is the isolation region, 22 is the source-drain contact structure, 23 is the insulating dielectric layer, 24 is the third source-drain contact structure, 25 is the first source-drain contact structure, 26 is the second source-drain contact structure, 27 is the first fin structure, 28 is the second fin structure, 29 is the sacrificial layer, 30 is the channel layer, 31 is the lower fin, 32 is the upper fin, 33 is the semiconductor isolation portion, 34 is the first mask structure, 35 is the sacrificial gate, 36 is the second isolation structure, and 37 is the shallow trench isolation structure. Detailed Implementation

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0053] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0054] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0057] Three-dimensional stacked transistors consist of two transistors stacked vertically along the thickness direction of the substrate, eliminating the lateral spacing between the two transistors. This allows for a further increase in the effective channel width, thereby improving the performance and integration of semiconductor devices.

[0058] However, in existing three-dimensional stacked transistors, the source and drain regions of the upper and lower transistors are roughly aligned along a direction parallel to the substrate surface. If the transistors are led upwards, the source and drain regions of the lower transistor cannot be exposed outside the source and drain regions of the upper transistor; similarly, if they are led downwards, the source and drain regions of the upper transistor cannot be exposed outside the source and drain regions of the lower transistor. In this situation, a conductive structure is needed between the source and drain regions of the upper and lower transistors to electrically connect the obscured source and drain regions to the source and drain contact structure. This ensures isolation from the source and drain contact structures of the source and drain regions electrically connected to the same side along the length of the gate stack in both transistors, preventing device failure. However, providing a conductive structure between the source and drain regions of the upper and lower transistors results in a larger isolation structure, leading to an increase in the parasitic capacitance of the semiconductor device. Furthermore, the increased thickness of the isolation structure also increases the lead-out length of the source and drain contact structure, resulting in an increase in the parasitic resistance of the semiconductor device, which is detrimental to improving the operating performance of the semiconductor device.

[0059] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, the active structures of the first transistor and the second transistor are staggered along a direction parallel to the substrate surface. This facilitates a reduction in the thickness of the first isolation structure, thereby reducing the parasitic resistance and capacitance of the semiconductor device and improving its performance.

[0060] In a first aspect, embodiments of the present invention provide a semiconductor device. For example... Figure 14 and Figure 15 As shown, the semiconductor device includes a substrate 11, a first transistor 12, and a second transistor 13. The first transistor 12 and the second transistor 13 are disposed on the substrate 11 at a distance from each other along the thickness direction, with the second transistor 13 positioned above the first transistor 12. The first active structure of the first transistor 12 and the second active structure of the second transistor 13 are offset along a direction parallel to the surface of the substrate 11. Both the first and second active structures include a channel region 15 and source / drain regions 16 located on both sides of the channel region 15 along its length direction.

[0061] When the above technical solution is adopted, such as Figures 15 to 18 As shown, the semiconductor device includes a first transistor 12 and a second transistor 13 spaced apart along the thickness direction of the substrate 11. Clearly, the first transistor 12 and the second transistor 13 can form a three-dimensional stacked transistor (CFET device) to improve the integration density of the semiconductor device. Furthermore, the first active structures of the first transistor 12 and the second transistor 13 are staggered along a direction parallel to the surface of the substrate 11. In this case, the two source / drain regions 16 located on the same side along the length direction of the gate stack structure 17 in the first transistor 12 and the second transistor 13 can be staggered along a direction parallel to the surface of the substrate 11. In other words, along the thickness direction of the substrate 11, the lower source / drain region 16 can be exposed outside the upper source / drain region 16. This facilitates the subsequent fabrication of source / drain contact structures 22, which are electrically connected to the corresponding source / drain regions 16 through the staggered spacing, preventing different source / drain contact structures from being electrically connected. The overlap of the drain contact structure 22 causes device failure, and there is no need to set a conductive structure for lead-out between the two. This helps to reduce the thickness of the isolation material (which may be the first isolation structure 14 hereinafter referred to as the first isolation structure) used to electrically insulate the source-drain regions 16 including the first transistor 12 and the second transistor 13, thereby reducing the parasitic capacitance of the semiconductor device. At the same time, because the thickness of the isolation material is smaller, the length of the source-drain contact structure 22 used to lead out the lower source-drain region 16 upward (or the length of the source-drain contact structure 22 used to lead out the upper source-drain region 16 downward) is also smaller, reducing the parasitic resistance of the semiconductor device and improving the operating performance of the semiconductor device.

[0062] In practical applications, the embodiments of the present invention do not specifically limit the structure and material of the substrate, as long as it can be applied to the semiconductor device provided by the embodiments of the present invention.

[0063] For example, the substrate can be any semiconductor material such as silicon, germanium silicon, or germanium.

[0064] For example, the substrate can also be an insulating material such as silicon dioxide or ceramic.

[0065] The substrate material can be determined based on the manufacturing process of the first and second transistors, as well as the lead-out direction of the source and drain contact structures included in the first and second transistors. For example, when the source and drain contact structures of both the first and second transistors are led out in an upward direction (i.e., from the first transistor to the second transistor), the substrate can be a semiconductor substrate. When the source and drain contact structures of both the first and second transistors are led out in a downward direction (i.e., from the second transistor to the first transistor), the substrate can be an insulating substrate.

[0066] In some cases, such as Figures 15 to 18 As shown, the semiconductor device may further include a first isolation structure 14. Along the thickness direction of the substrate 11, the first isolation structure 14 is disposed between the source / drain regions 16 included in the first transistor 12 and the source / drain regions 16 included in the second transistor 13 to prevent leakage current and device failure.

[0067] In some cases, such as Figures 15 to 18 As shown, the surface of the substrate 11 may include a first well region 19 and a second well region 20 spaced apart, and an isolation region 21 located at least between the first well region 19 and the second well region 20. Furthermore, the first transistor 12 is directly disposed on the first well region 19, and the second transistor 13 is disposed above the second well region 20. In the above case, the first isolation structure 14 may directly cover the second well region 20 and the source / drain region 16 included in the first transistor 12, and is located below the source / drain region 16 included in the second transistor 13. Alternatively, the semiconductor device may also include an insulating material directly covering the second well region 20; and the first isolation structure 14 may cover the insulating material and the source / drain region 16 included in the first transistor 12.

[0068] In some cases, such as Figure 15 As shown, the semiconductor device may further include an insulating dielectric layer 23 to reduce the risk of leakage current in the semiconductor device and improve the yield of the source-drain regions 16 included in the second transistor 13, thereby improving the operating performance of the semiconductor device. The insulating dielectric layer 23 covers the second transistor 13 and also covers the portion of the first isolation structure 14 corresponding to the first transistor 12.

[0069] The material of the insulating dielectric layer may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention.

[0070] Regarding the first transistor and the second transistor, in terms of conductivity type, the first transistor and the second transistor can have the same or opposite conductivity types. The specific conductivity types of the first transistor and the second transistor can be set according to actual requirements.

[0071] In terms of device type, the embodiments of the present invention do not specifically limit the device types of the first transistor and the second transistor, as long as they can be applied to the semiconductor device provided in the embodiments of the present invention. The device types of the first transistor and the second transistor can be the same or different.

[0072] For example, the first transistor and / or the second transistor may be a fin field-effect transistor or a gate-around transistor.

[0073] For example, when the first transistor and / or the second transistor is a finned field-effect transistor, the first transistor and / or the second transistor includes a source / drain region, a channel region, and a gate stack structure. The source / drain regions are located on both sides of the channel region along its length, and the gate stack structure covers the top and both sides of the channel region.

[0074] For example, when the first transistor and / or the second transistor is a gate-to-ring transistor, the first transistor and / or the second transistor includes a source-drain region, a channel region, and a gate stack structure. The source-drain region is disposed on both sides of the channel region along its length. The channel region includes at least one layer of nanostructure suspended between the source-drain region. The gate stack structure surrounds the outer periphery of each nanostructure layer. This embodiment of the invention does not specifically limit the number of nanostructure layers included in the channel region.

[0075] It should be noted that the source region of the second transistor may be located on the same side as the source region of the first transistor along the length of the gate stack structure; or the drain region of the second transistor may be located on the same side as the source region of the first transistor along the length of the gate stack structure.

[0076] Secondly, since the active structures of the first transistor and the second transistor are staggered along a surface direction parallel to the substrate, when the first mask structure is selectively removed, the channel regions of the first transistor and the second transistor can be released respectively, forming gate stack structures of the first transistor and the second transistor respectively. This facilitates obtaining first transistors and second transistors with gate stack structures of different materials and / or thicknesses, thereby enabling the regulation of the driving voltage of the first transistor and the second transistor.

[0077] In addition, such as Figures 15 to 18As shown, the first active structure of the first transistor 12 and the second active structure of the second transistor 13 are offset along a direction parallel to the surface of the substrate 11, and the offset distance between them can be set according to actual needs.

[0078] For example, along the width direction of the channel region, the spacing between the channel regions of the first transistor and the second transistor can be greater than or equal to 10 nm and less than or equal to 40 nm. For instance, the spacing between the channel regions of the first transistor and the second transistor can be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, 32 nm, 35 nm, 38 nm, or 40 nm, etc. The spacing between the channel regions of the first transistor and the second transistor within the above range helps prevent a small source / drain region from forming, thus improving the driving performance of the semiconductor device. It also prevents a large spacing from resulting in low lateral integration of the semiconductor device, facilitating the miniaturization of the semiconductor device.

[0079] It should be noted that, as Figure 13 and Figure 14 As shown, the semiconductor device may further include a first semiconductor portion disposed on the substrate 11, and the first semiconductor portion and the first active structure are laterally distributed along the surface of the substrate 11. The second active structure is disposed above the first semiconductor portion. The first isolation structure 14 directly covers both sides of the first semiconductor portion along its length direction and covers the source / drain regions 16 included in the first active structure, and the first isolation structure 14 is located below the source / drain regions 16 included in the second active structure.

[0080] In the actual manufacturing process, such as Figure 13 and Figure 14 As shown, the first semiconductor portion may be at least a portion of the upper fin portion 32 of the remaining first fin structure 27 after the channel region 15 included in the first transistor 12 and the second transistor 13 is formed. The first semiconductor portion is disposed above the first well region 19.

[0081] Specifically, such as Figure 13 and Figure 14 As shown, the channel region 15 included in the first active structure can be distributed parallel to the first semiconductor portion. Alternatively, the extending direction of the channel region 15 included in the first active structure can also intersect with the extending direction of the first semiconductor portion, but the channel region 15 included in the first active structure and the first semiconductor portion are distributed at intervals.

[0082] In addition, such as Figure 13 and Figure 14As shown, the semiconductor device may further include a second semiconductor portion disposed above the first active structure, the second semiconductor portion and the second active structure being laterally distributed along a surface direction parallel to the substrate.

[0083] In the actual manufacturing process, such as Figure 13 and Figure 14 As shown, the second semiconductor portion may be at least a portion of the lower fin 31 of the remaining second fin structure 28 after the channel region 15 included in the first transistor 12 and the second transistor 13 has been formed. The second semiconductor portion is disposed on the second well region 20. Furthermore, the channel region 15 included in the second active structure may be distributed parallel to the second semiconductor portion. Alternatively, the extending direction of the channel region 15 included in the second active structure may intersect with the extending direction of the second semiconductor portion, but the channel region 15 included in the second active structure and the second semiconductor portion are spaced apart.

[0084] The structure and materials of the first and second semiconductor sections can be set according to actual needs.

[0085] For example, such as Figure 13 and Figure 14 As shown, the channel region 15 included in the first active structure may have the same shape and / or material as the first semiconductor portion. In this case, the first semiconductor portion can be formed simultaneously with the fabrication of the channel region 15 included in the first active structure, which can improve the manufacturing efficiency of the semiconductor device. Secondly, the channel region 15 included in the first active structure in the first transistor can be self-aligned with the first semiconductor portion (at this time, the sidewalls of the channel region 15 included in the first active structure are substantially aligned with the sidewalls of the first semiconductor portion).

[0086] For example, such as Figure 13 and Figure 14 As shown, the channel region 15 included in the second active structure has the same shape and / or material as the second semiconductor portion. In this case, the second semiconductor portion can be formed simultaneously with the fabrication of the channel region 15 included in the second active structure, which can improve the manufacturing efficiency of the semiconductor device. Furthermore, the channel region 15 included in the second active structure can be self-aligned with the second semiconductor portion (in this case, the sidewalls of the channel region 15 included in the second active structure are substantially aligned with the sidewalls of the second semiconductor portion).

[0087] It is worth noting that, such as Figures 6 to 18As shown, when the channel region 15 of the first active structure in the first transistor 12 is self-aligned with the first semiconductor portion, and the channel region 15 of the second active structure is self-aligned with the second semiconductor portion, in the actual manufacturing process, a first fin structure 27 and a second fin structure 28 spaced apart can be formed on the substrate 11. The source / drain regions 16 on both sides of the lower fin portion 31 of the second fin structure 28 are selectively etched away, and the source / drain regions 16 on both sides of the upper fin portion 32 of the first fin structure 27 are selectively removed, thus achieving a staggered arrangement of the source / drain regions 16 of the first transistor 12 and the second transistor 13. By controlling the staggered spacing of the first fin structure 27 and the second fin structure 28, the staggered arrangement spacing of the active structures of the first transistor 12 and the second transistor 13 can be precisely controlled, improving the yield of semiconductor devices while reducing the manufacturing difficulty.

[0088] The specific structure of the first semiconductor section can be determined based on the device type of the first transistor. For example, when the first transistor is a fin field-effect transistor, the structure and material of the first semiconductor section are the same as those of the channel region included in the first transistor. When the first transistor is a gate-to-ring transistor, the structure and material of the first semiconductor section and the channel region included in the first transistor can be the same; or the first semiconductor section may include not only nanostructures made of the same material as those included in the channel region of the first transistor, but may also include sacrificial layers located between the nanostructures (the sacrificial layers were not removed during the formation of the channel region included in the second transistor).

[0089] As for the second semiconductor section, its specific structure can be determined based on the device type of the second transistor. For example, when the second transistor is a fin field-effect transistor, the structure and material of the second semiconductor section are the same as those of the channel region included in the second transistor. When the second transistor is a gate-to-ring transistor, the structure and material of the second semiconductor section can be the same as those of the channel region included in the second transistor; or the second semiconductor section may include not only nanostructures made of the same material as those included in the channel region of the second transistor, but also sacrificial layers located between the nanostructures (the sacrificial layers were not removed during the formation of the channel region included in the first transistor).

[0090] In practical applications, such as Figures 16 to 18As shown, the first transistor 12 and the second transistor 13 also include a first source-drain contact structure 25 and a second source-drain contact structure 26. The first source-drain contact structure 25 is electrically contacted with one of the source-drain regions 16 included in the first active structure, and the second source-drain contact structure 26 is electrically contacted with one of the source-drain regions 16 included in the second active structure. The first source-drain contact structure 25 and the second source-drain contact structure 26 are located on the same side of the gate stack structure 17 along the length direction and are spaced apart along the surface direction of the substrate 11. The first source-drain contact structure 25 and the second source-drain contact structure 26 extend in a direction perpendicular to the surface of the substrate 11. In this case, since the first active structure and the second active structure are staggered in a direction parallel to the surface of the substrate 11, there is no need to provide a lead structure between them, which helps to reduce the thickness of the first isolation structure 14 and reduce the parasitic capacitance and parasitic resistance of the semiconductor device. At the same time, it also helps to reduce the space occupied by the first source-drain contact structure 25 and the second source-drain contact structure 26, which is beneficial for the miniaturization of the semiconductor device.

[0091] Specifically, such as Figure 16 As shown, the first source-drain contact structure 25 and the second source-drain contact structure 26 can extend from the substrate 11 along the same side of the thickness direction to the upper surface of the source-drain region 16 included in the first active structure and the second active structure, respectively. Alternatively, as... Figure 17 As shown, the first source-drain contact structure 25 and the second source-drain contact structure 26 can also extend from the same side of the substrate 11 along the thickness direction to the lower surface of the source-drain region 16 included in the first active structure and the second active structure, respectively. In this case, the wiring difficulty on the front side of the semiconductor device can be reduced, electrical interference can be avoided, and the electrical performance of the device can be improved.

[0092] For example, such as Figure 18 As shown, the first transistor 12 and the second transistor 13 may further include a third source-drain contact structure 24. The third source-drain contact structure 24 includes a vertical extension and a lateral extension electrically contacting the vertical extension. The vertical extension is located above and electrically contacting the other of the source-drain regions 16 included in the first active structure. The lateral extension is located above or below the other of the source-drain regions 16 included in the second active structure and serves to electrically connect the vertical extension to the other of the source-drain regions 16 included in the second active structure.

[0093] The vertical extension can extend along a direction perpendicular to the substrate surface to reduce the space occupied by the third source-drain contact structure, which is beneficial for the miniaturization of semiconductor devices. The lateral extension can extend parallel to the substrate surface.

[0094] In addition, if the distance between the source and drain regions of the first transistor and the second transistor along the substrate surface is small, the electrical connection between them can be achieved through only a vertical extension, which can simplify the structure of the semiconductor device and reduce the manufacturing difficulty of the semiconductor device.

[0095] For the first isolation structure, along the thickness direction of the substrate, the first isolation structure is disposed between the source / drain regions of the first transistor and the source / drain regions of the second transistor. The material of the first isolation structure may include any insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The first isolation structure may be a single-layer structure in which all parts are made of the same material, or it may be a multilayer structure including multiple materials (the distribution between different materials can be set according to actual needs, and is not specifically limited here).

[0096] As for the thickness of the first isolation structure, it can be determined based on the electrical insulation requirements of the first isolation structure in the actual application scenario, as well as the requirements for the parasitic capacitance and parasitic resistance of the semiconductor device. No specific limitation is made here.

[0097] For example, along the thickness direction of the substrate, the thickness of the first isolation structure can be greater than or equal to 5 nm and less than or equal to 30 nm. For instance, the thickness of the first isolation structure can be 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 28 nm, or 30 nm, etc.

[0098] In some cases, such as Figure 15 As shown, the various parts of the first isolation structure 14 can be integrally formed (i.e., formed simultaneously in the same step) to simplify the manufacturing process of semiconductor devices and improve the manufacturing efficiency of semiconductor devices.

[0099] In one example, such as Figure 13 and Figure 14 As shown, the semiconductor device may further include a second isolation structure 36. The second isolation structure 36 is disposed between the gate stack structure 17 included in the first transistor 12 and the gate stack structure 17 included in the second transistor 13 to reduce electrical interference between the first transistor 12 and the second transistor 13, thereby improving the electrical performance of the semiconductor device. The material of the second isolation structure 36 may include any insulating material such as silicon oxide or silicon nitride.

[0100] In some cases, such as Figure 15As shown, the semiconductor device provided in this embodiment of the invention may further include a gate sidewall 18. The gate sidewall 18 is disposed on both sides along the length of the gate stack structure 17 included in the first transistor 12 and the second transistor 13, serving to separate the gate stack structure 17 from other adjacent conductive structures and reduce the risk of leakage. The material of the gate sidewall 18 may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0101] In some cases, such as Figure 15 As shown, the semiconductor device provided in this embodiment of the invention may further include a shallow trench isolation structure 37. The shallow trench isolation structure 37 is formed on the substrate 11 to define the active region of the substrate 11, reduce leakage risk, and further improve the yield and performance of the semiconductor device.

[0102] As for the material of the shallow trench isolation structure, it can include any insulating material such as silicon oxide, silicon oxynitride, or silicon oxynitride, without specific limitations here.

[0103] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as that of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the second aspect and its various implementations in the present invention can be analyzed with reference to the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0104] The following will be based on Figures 1 to 18 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0105] First, such as Figures 1 to 3 As shown, a first fin structure 27 and a second fin structure 28 are formed on a substrate 11. The first fin structure 27 and the second fin structure 28 are spaced apart along a direction parallel to the surface of the substrate 11. Along the thickness direction of the substrate 11, both the first fin structure 27 and the second fin structure 28 include a lower fin portion 31, a semiconductor isolation portion 33, and an upper fin portion 32 arranged sequentially.

[0106] In the actual manufacturing process, the lower fin of the first fin structure is used to manufacture the first transistor. Therefore, the specific structure of the lower fin of the first fin structure and the second fin structure can be determined according to the device type and structure of the first transistor.

[0107] For example, when the first transistor is a fin field-effect transistor, the lower fin portion of the first fin structure and the second fin structure can be a single-layer elongated semiconductor structure; or, it can be an elongated semiconductor structure including multiple semiconductor layers. Furthermore, the material and width of the lower fin portion of the first fin structure and the second fin structure are the same as the material and width of the channel region included in the first transistor.

[0108] For example, when the first transistor is a gate-to-ring transistor, the lower fins of the first and second fin structures may include alternately stacked sacrificial layers and channel layers. In the alternately stacked sacrificial layers and channel layers, both the bottom and top layers are sacrificial layers. The channel layer included in the lower fins of the first and second fin structures is used to fabricate the nanostructures in the channel region of the first transistor; therefore, the width of the lower fin and the material of the channel layer included in the lower fin can be determined based on the material and width of the channel region of the first transistor. Regarding the sacrificial layer included in the lower fin, the channel region of the first transistor needs to be released by subsequently removing the sacrificial layer of the lower fin covered by the first mask structure. Furthermore, when selectively removing the sacrificial layer included in the lower fin, the upper fin (or the channel layer included in the upper fin) is retained; therefore, the material of the sacrificial layer included in the lower fin can be any semiconductor material different from the channel layer included in the lower fin and the upper fin (or the channel layer included in the upper fin). For example, if the material of the channel layer in both the lower and upper fins is silicon, the material of the sacrificial layer in the lower fin can be germanium-silicon or germanium.

[0109] Similarly, the upper fin portion of the second fin structure is used to manufacture the second transistor, so the specific structure of the upper fin portion of the first and second fin structures can be determined according to the device type and structure of the second transistor.

[0110] For example, when the second transistor is a fin field-effect transistor, the upper fin portion of the first fin structure and the second fin structure can be a single-layer elongated semiconductor structure; or, it can be an elongated semiconductor structure including multiple semiconductor layers. Furthermore, the material and width of the upper fin portion are the same as the material and width of the channel region included in the second transistor.

[0111] For example, when the second transistor is a gate-around transistor, the upper fin in the first and second fin structures may include at least one semiconductor stack. Each semiconductor stack includes a sacrificial layer and a channel layer located on the sacrificial layer. The channel layer included in the upper fin is used to fabricate the nanostructure in the channel region of the second transistor; therefore, the material of the channel layer included in the upper fin in the first and second fin structures can be determined based on the material of the channel region of the second transistor. Regarding the sacrificial layer included in the upper fin, the channel region of the second transistor needs to be released by subsequently removing the sacrificial layer of the upper fin covered by the first mask structure. Furthermore, when the sacrificial layer included in the upper fin is selectively removed, the lower fin (or the channel layer included in the lower fin) is retained; therefore, the material of the sacrificial layer included in the upper fin can be any semiconductor material different from that of the channel layer included in the upper fin and the lower fin (or the channel layer included in the lower fin). In addition, when both the first transistor and the second transistor are gate-around transistors, the sacrificial layers included in the lower fin and the upper fin can be made of the same material to reduce the limitation of the epitaxial critical thickness and improve the formation quality of the semiconductor device; of course, the two materials can also be different.

[0112] Regarding the semiconductor isolation portions included in the first and second fin structures, these semiconductor isolation portions serve a pre-positioning function. Subsequently, by removing the semiconductor isolation portions not covered by the first mask structure, and after forming the source / drain regions included in the first transistor, a first isolation structure is formed on the source / drain regions included in the first transistor and the substrate. Therefore, the thickness of the semiconductor isolation portion can be determined according to the thickness requirements of the first isolation structure. As for the material of the semiconductor isolation portion, it can be any semiconductor material different from that of the lower and upper fins; no specific limitation is made here.

[0113] For example, such as Figure 1 As shown, epitaxial growth and other processes can be used to form a sacrificial layer 29 and a channel layer 30 for manufacturing the lower fin 31 and the upper fin 32 along the thickness direction of the substrate 11, and to form a semiconductor isolation layer for manufacturing the semiconductor isolation portion 33. Then, as... Figure 2 As shown, the sacrificial layer 29, channel layer 30, semiconductor isolation layer, and part of the substrate 11 are patterned using photolithography and etching processes to form at least two spaced Fin structures. Next, as... Figure 3 As shown, shallow trench isolation structures 37 for defining active regions can be formed between adjacent fin structures using processes such as deposition and etching. The top height of the shallow trench isolation structure 37 is less than or equal to the bottom height of the underlying sacrificial layer 29. The portions of at least two fin structures exposed outside the shallow trench isolation structure 37 include a first fin structure 27 and a second fin structure 28.

[0114] It should be noted that when the manufactured semiconductor device does not include the shallow trench isolation structure mentioned above, only the sacrificial layer, the channel layer and the semiconductor isolation layer can be patterned; and after the patterning process, the first fin structure and the second fin structure can be directly obtained.

[0115] Next, the upper fin portion included in the first and second fin structures is protected.

[0116] For example, such as Figure 4 As shown, a first mask structure 34 can be formed across the first fin structure 27 and the second fin structure 28 using processes such as deposition and etching. The specific structure and material of the first mask structure 34 can be set according to actual needs, as long as it can provide mask protection in the future.

[0117] For example, such as Figure 4 As shown, the first mask structure 34 may include a sacrificial gate 35. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon.

[0118] For example, such as Figure 4 As shown, the first mask structure 34 may include a sacrificial gate 35 and gate sidewalls 18 located at least on both sides of the sacrificial gate 35 along its length. The material of the sacrificial gate 35 may include an easily removable material such as polysilicon. The material of the gate sidewalls 18 can be referred to above.

[0119] For example, the first mask structure described above may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include silicon oxide or the like.

[0120] In one example, after forming the first mask structure, the semiconductor device manufacturing method further includes: removing the remaining semiconductor isolation portion using processes such as dry etching or wet etching. Next, as... Figure 4 As shown, a second isolation structure 36 is formed between the remaining lower fin 31 and the remaining upper fin 32 using processes such as deposition and etching.

[0121] It should be noted that the gate sidewalls on both sides of the first mask structure along its length can be formed simultaneously with the fabrication of the second isolation structure to improve the manufacturing efficiency of the semiconductor device. Alternatively, the second isolation structure can be fabricated using processes such as deposition and etching after the gate sidewalls have been formed.

[0122] Next, as Figure 5 As shown, dry etching or wet etching processes can be used to remove the portions of the first fin structure 27 and the second fin structure 28 that are exposed outside the first mask structure 34 (if the second isolation structure 36 is formed at this time, the second isolation structure 36 also needs to be selectively etched).

[0123] Next, deposition and etching processes can be used to form a second mask structure on the substrate, covering both sides of the lower fin portion included in the first and second fin structures along the length direction. This embodiment of the invention does not specifically limit the material of the second mask structure. The top of the second mask structure needs to be greater than the top height of the lower fin portion and less than the bottom height of the upper fin portion.

[0124] Next, deposition and etching processes can be used to form a third mask structure covering both sides of the upper fin portion along its length, including the first and second fin portions. The material of the third mask structure is different from the material of the second mask structure. This invention does not specifically limit the material of the third mask structure; it can be any material that is different from the material of the second mask structure and is easy to remove.

[0125] For example, the material of the second mask structure may include silicon oxide, and the material of the third mask structure may include silicon nitride.

[0126] Next, wet etching or dry etching processes can be used to selectively remove the second mask structure to expose the lower fin.

[0127] Next, as Figure 6 As shown, under the protection of the third mask structure, source / drain regions 16 can be formed on both sides of the remaining lower fin portion 31 in the first fin structure 27 and the second fin structure 28.

[0128] Alternatively, in practical applications, epitaxial growth or other processes can be used to form source / drain regions on both sides of the remaining lower fin portion in the first and second fin structures. Then, an etching process is used to remove the source / drain regions located on the outer periphery of the remaining upper fin portion (if a semiconductor isolation portion is formed, the source / drain regions on both sides of the semiconductor isolation portion also need to be removed).

[0129] Next, as Figure 7 As shown, the source / drain regions 16 on both sides of the lower fin portion 31 of the second fin structure 28 are etched away.

[0130] In the actual manufacturing process, deposition and etching processes can be used to form a mask material covering the source / drain regions on both sides of the lower fin of the first fin structure. The source / drain regions on both sides of the lower fin of the second fin structure are exposed. Then, dry or wet etching processes are used to selectively remove the source / drain regions on both sides of the lower fin of the second fin structure. Next, the mask material covering the source / drain regions on both sides of the lower fin of the first fin structure is removed.

[0131] Next, as Figure 8 As shown, the lower fin portion of the first fin structure and the second fin structure is protected.

[0132] For example, such as Figure 8 As shown, a first isolation structure 14 can be formed by using processes such as deposition and etching, covering the substrate 11 and the source / drain regions 16 located on both sides of the lower fin portion 31 of the first fin structure.

[0133] Next, as Figure 9 As shown, source / drain regions 16 are formed on both sides of the remaining upper fin portion 32 in the first and second fin structures. It should be noted that... Figure 9 This is just an illustration. In the actual manufacturing process, the source and drain regions 16 located on both sides of the two upper fins 32 can be distributed at intervals along the surface direction parallel to the substrate 11. With this arrangement, when one set of source and drain regions 16 is etched, the other set of source and drain regions 16 will not be affected.

[0134] Next, as Figure 10 As shown, the source / drain regions 16 on both sides of the upper fin portion of the first fin structure are etched away. The operation process for this step can refer to the operation process for etching away the source / drain regions 16 on both sides of the lower fin portion 31 of the second fin structure described above, and will not be repeated here.

[0135] Next, as Figure 11 As shown, an insulating dielectric layer 23 covering the substrate 11 can be formed using processes such as deposition and planarization. The top of this insulating dielectric layer 23 is flush with the top of the first mask structure 34. The material of the insulating dielectric layer 23 can be referred to the previous text and will not be repeated here.

[0136] Next, as Figure 12 As shown, dry etching or wet etching processes can be used to remove at least part of the first mask structure.

[0137] It should be noted that the decision to remove the entire first mask structure or only a portion thereof can be determined based on the specific structure of the first mask structure. For example, if the first mask structure includes only a sacrificial gate or only a sacrificial gate and a gate oxide layer, the entire first mask structure needs to be removed. If the first mask structure includes both a sacrificial gate and a gate sidewall, the gate sidewall needs to be retained, meaning only a portion of the first mask structure needs to be removed.

[0138] Next, as Figures 13 to 15 As shown, a first transistor 12 is formed based on the remaining lower fin portion in the first fin structure and the source / drain region 16 adjacent to itself, and a second transistor 13 is formed based on the remaining upper fin portion in the second fin structure and the source / drain region 16 adjacent to itself.

[0139] The specific execution method of this operation can be set according to the device types of the first and second transistors and actual needs. For example, when the first and second transistors are finned field-effect transistors, after removing the first mask structure, the remaining lower fin portion in the first fin structure forms the channel region included in the first transistor. The remaining upper fin portion in the second fin structure forms the channel region included in the second transistor.

[0140] For example, in the case where the first transistor and / or the second transistor is a gate-around transistor, after removing the first mask structure, it is also necessary to remove the remaining sacrificial layer to release the channel region.

[0141] Next, as Figure 15 As shown, a gate stack structure 17 can be formed on the outer periphery of the channel region 15 using processes such as atomic layer deposition.

[0142] Next, as Figures 16 to 18 As shown, a source-drain contact structure is formed that makes electrical contact with the source-drain regions 16 included in the first transistor 12 and the second transistor 13. The specific formation process of the source-drain contact structure can be determined according to its specific structure and lead-out direction, and is not specifically limited here.

[0143] For example, such as Figure 16 As shown, etching and deposition processes can be used to form a first source-drain contact structure 25 that penetrates the first isolation structure 14 along a direction perpendicular to the surface of the substrate 11, covering one of the source-drain regions 16 included in the first transistor 12, and penetrating the portion of the insulating dielectric layer 23 at the same height as the second transistor 13. The first source-drain contact structure 25 is electrically connected to one of the source-drain regions 16 included in the first transistor 12. Next, as... Figure 16 As shown, a second source-drain contact structure 26 can be formed by etching and deposition processes, penetrating the insulating dielectric layer 23 and covering the portion above one of the source-drain regions 16 included in the second transistor 13, along a direction perpendicular to the surface of the substrate 11. The second source-drain contact structure 26 is electrically connected to the other of the source-drain regions 16 included in the second transistor 13. The first source-drain contact structure 25 and the second source-drain contact structure 26 are disposed on the same side of the first transistor 12 and the second transistor 13 along the length direction of the gate stack structure 17, and the first source-drain contact structure 25 and the second source-drain contact structure 26 are spaced apart.

[0144] In this case, the embodiments of the present invention do not specifically limit the formation order of the first source-drain contact structure and the second source-drain contact structure. The first source-drain contact structure can be formed first, followed by the second source-drain contact structure. Alternatively, the second source-drain contact structure can be formed first, followed by the first source-drain contact structure.

[0145] For example, when the source-drain contact structure includes a first source-drain contact structure and a second source-drain contact structure, and the first source-drain contact structure and the second source-drain contact structure extend downwards, such as... Figure 17 As shown, a first source-drain contact structure 25 can be formed penetrating the substrate 11 along a direction perpendicular to the surface of the substrate 11. The first source-drain contact structure 25 is electrically connected to one of the source-drain regions 16 included in the first transistor 12. Next, as... Figure 17 As shown, a second source-drain contact structure 26 is formed that penetrates the substrate 11 along a direction perpendicular to the surface of the substrate 11 and penetrates the portion of the first isolation structure 14 and the first transistor 12 at the same height. The second source-drain contact structure 26 is electrically connected to one of the source-drain regions 16 included in the second transistor 13.

[0146] In actual manufacturing, when the first and second source / drain contact structures extend downwards, processes such as chemical mechanical polishing, dry etching, and wet etching can be used to thin the substrate. Etching processes are then used to selectively etch the substrate to form contact holes, and physical vapor deposition processes are employed to form the first and second source / drain contact structures filling the contact holes. In other embodiments of the invention, during the etching of the actual contact holes, the top or bottom of the source / drain region 16 may also be etched into a plane, so that the contact surfaces of the first and second source / drain contact structures 25 and 26 with the top or bottom of the source / drain region 16 become planar. In other embodiments, the cross-section of the contact hole may also be larger than the surface area of ​​the source / drain region.

[0147] For example, such as Figure 18 As shown, a third source-drain contact structure 24 is formed that is electrically connected to both the other source-drain region 16 included in the first transistor 12 and the other source-drain region 16 included in the second transistor 13. The third source-drain contact structure 24 includes a vertical extension and a lateral extension electrically connected to the vertical extension. The vertical extension is located above and electrically connected to the other source-drain region 16 included in the first transistor 12. The lateral extension is located above or below the other source-drain region 16 included in the second transistor 13 and is used to electrically connect the vertical extension to the other source-drain region 16 included in the second transistor 13. In this way, a common-drain connection can be achieved in the SRAM cell and the inverter without wasting the overall transistor area, while also reducing the capacitance caused by device contacts.

[0148] Specifically, a mask material can be first formed on a portion of the insulating dielectric layer 23 using processes such as photolithography and etching. Then, under the protection of the mask material, contact holes are formed. Next, a third source-drain contact structure filling the contact holes is formed using processes such as physical vapor deposition.

[0149] It should be noted that the above is only a brief description of the manufacturing process of the source-drain contact structure, so that those skilled in the art can easily implement the embodiments provided by the present invention. Those skilled in the art can certainly imagine other ways to manufacture the source-drain contact structure.

[0150] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0151] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a first transistor, and a second transistor; the first transistor and the second transistor are disposed on the substrate at a distance from each other along the thickness direction of the substrate, and the second transistor is located above the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are offset along a direction parallel to the surface of the substrate; both the first active structure and the second active structure include a channel region and source / drain regions located on both sides of the channel region along the length direction. The semiconductor device further includes a first isolation structure; along the thickness direction of the substrate, the first isolation structure is disposed between the source / drain regions included in the first active structure and the source / drain regions included in the second active structure; The semiconductor device further includes a first semiconductor portion disposed on the substrate, and the first semiconductor portion and the first active structure are laterally distributed along the surface of the substrate; the second active structure is disposed above the first semiconductor portion; the first isolation structure directly covers both sides of the first semiconductor portion along the length direction and covers the source and drain regions included in the first transistor, and the first isolation structure is located below the source and drain regions included in the second transistor; The semiconductor device further includes a second semiconductor portion disposed above the first active structure, the second semiconductor portion and the second active structure being laterally distributed along a surface direction parallel to the substrate.

2. The semiconductor device according to claim 1, characterized in that, Along the thickness direction of the substrate, the thickness of the first isolation structure is greater than or equal to 5 nm and less than or equal to 30 nm; And / or, the various parts of the first isolation structure are integrally formed.

3. The semiconductor device according to claim 1, characterized in that, The channel region included in the first active structure is distributed parallel to the first semiconductor portion; And / or, the channel region included in the first active structure has the same shape and / or material as the first semiconductor portion.

4. The semiconductor device according to claim 1, characterized in that, The channel region included in the second active structure is distributed in parallel with the second semiconductor portion; And / or, the channel region included in the second active structure has the same shape and / or material as the second semiconductor portion.

5. The semiconductor device according to claim 1, characterized in that, In the case where the semiconductor device further includes a first semiconductor portion, the channel region included in the second active structure is aligned with the first semiconductor portion; And / or, the channel region included in the first active structure is aligned with the second semiconductor portion.

6. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor further include a first source-drain contact structure and a second source-drain contact structure; the first source-drain contact structure is electrically contacted with one of the source-drain regions included in the first active structure, and the second source-drain contact structure is electrically contacted with one of the source-drain regions included in the second active structure. The first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the gate stack structure included in the first transistor and / or the second transistor, and are spaced apart along the surface direction of the substrate; the first source-drain contact structure and the second source-drain contact structure extend along the surface direction perpendicular to the substrate.

7. The semiconductor device according to claim 6, characterized in that, The first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the upper surface of the source-drain region included in the first active structure and the second active structure, respectively; Alternatively, the first source-drain contact structure and the second source-drain contact structure extend from the same side of the substrate along the thickness direction to the lower surface of the source-drain region included in the first active structure and the second active structure, respectively.

8. The semiconductor device according to claim 6, characterized in that, The first transistor and the second transistor further include a third source-drain contact structure; the third source-drain contact structure includes a vertical extension and a lateral extension electrically in contact with the vertical extension; the vertical extension is located above the other of the source-drain regions included in the first active structure and is electrically in contact with the other of the source-drain regions included in the first active structure. The lateral extension is located above or below the other of the source / drain regions included in the second active structure, and is used to electrically connect the vertical extension to the other of the source / drain regions included in the second active structure.

9. The semiconductor device according to claim 8, characterized in that, The vertical extension extends along a surface direction perpendicular to the substrate.

10. The semiconductor device according to claim 1, characterized in that, The first transistor and the second transistor have opposite conduction types; And / or, along the width direction of the channel region, the distance between the channel region included in the first active structure and the channel region included in the second active structure is greater than or equal to 10 nm and less than or equal to 40 nm.

11. A method for manufacturing a semiconductor device, characterized in that, include: A first fin-like structure and a second fin-like structure are formed on the substrate; The first fin structure and the second fin structure are distributed at intervals along a direction parallel to the surface of the substrate; along the thickness direction of the substrate, both the first fin structure and the second fin structure include a lower fin, a semiconductor isolation portion and an upper fin, which are arranged sequentially. The upper fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the lower fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the lower fin portion included in the second fin structure are etched away; The lower fin portion included in the first fin structure and the second fin structure is protected, and source / drain regions are formed on both sides of the upper fin portion included in the first fin structure and the second fin structure. The source and drain regions on both sides of the upper fin portion included in the first fin structure are etched away; The protection of the lower fin portion included in the first fin structure and the second fin structure includes: forming a first isolation structure covering both sides of the lower fin portion included in the second fin structure along the length direction and covering the already formed source / drain region.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The protection of the upper fin portion included in the first fin structure and the second fin structure includes: A first mask structure is formed that spans the first fin structure and the second fin structure; Etching removes the portions of the first fin structure and the second fin structure that are exposed outside the first mask structure; A second mask structure is formed on the substrate, covering both sides of the lower fin along the length direction, including the lower fin and the upper fin. A third mask structure is formed covering both sides of the upper fin along the length direction, including the lower fin and the upper fin; the material of the third mask structure is different from the material of the second mask structure; The second mask structure is selectively removed.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The method for manufacturing the semiconductor device after etching away the source / drain regions on both sides of the upper fin portion of the first fin structure further includes: Using semiconductor technology, a first transistor is formed based on the remaining lower fin portion of the first fin structure and the source / drain region adjacent to it, and a second transistor is formed based on the remaining upper fin portion of the second fin structure and the source / drain region adjacent to it.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A first source-drain contact structure is formed that is electrically connected to one of the source-drain regions included in the first transistor; A second source-drain contact structure is formed to electrically contact one of the source-drain regions included in the second transistor; the first source-drain contact structure and the second source-drain contact structure are located on the same side along the length direction of the first transistor and / or the gate stack structure included in the second transistor, and are spaced apart; the first source-drain contact structure extends along a surface direction perpendicular to the substrate.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, After forming the first transistor and the second transistor, the method for manufacturing the semiconductor device further includes: A third source-drain contact structure is formed that is electrically connected to both the other source-drain region included in the first transistor and the other source-drain region included in the second transistor. The third source-drain contact structure includes a vertical extension and a lateral extension electrically contacting the vertical extension. The vertical extension is located above and electrically contacting the other source-drain region included in the first transistor. The lateral extension is located above or below the other source-drain region included in the second transistor and is used to electrically connect the vertical extension to the other source-drain region included in the second transistor.

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