Solar cells and photovoltaic modules

Abstract

This application provides a solar cell and a photovoltaic module, belonging to the field of solar cell technology. The solar cell includes: a semiconductor substrate having opposing first and second surfaces, and a plurality of first side surfaces adjacent to the first and second surfaces; a passivation contact structure located at least on a portion of the first surface of the semiconductor substrate, the passivation contact structure including sequentially stacked interface passivation layers and a first doped semiconductor layer; wherein, in the direction from the first surface to the second surface, the first side surface includes sequentially adjacent first and second regions, the first region protruding in a direction away from the second region compared to the first side surface; the first doped semiconductor layer is also located on a portion of the surface of the first region, wherein the first doped semiconductor layer on the first region is integrally continuous with the first doped semiconductor layer on the first surface; the surface of the portion of the first region adjacent to the second region is not covered by the first doped semiconductor layer.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on September 12, 2024, with application number 202411280473.1 and invention title "Solar Cells and Photovoltaic Modules". Technical Field

[0002] At least one embodiment of this application relates to a solar cell, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0003] In related technologies, solar cells include N-type and P-type regions. A certain degree of electrical isolation is required between the N-type and P-type regions. Generally, the N-type and P-type regions can be isolated by processes such as wet etching. However, the existing methods are not perfect, and there is still a risk of leakage between the front and back of the solar cell.

[0004] Meanwhile, during production and handling, the battery edges are prone to mutual friction, causing the passivation film layer to peel off or be scratched, resulting in the substrate being exposed on the outside. In this case, the surface passivation layer is damaged, which weakens the battery's passivation performance and thus affects battery performance. Summary of the Invention

[0005] In view of this, it is necessary to provide a solar cell and a photovoltaic module formed from a solar cell, addressing the shortcomings of solar cells in related technologies.

[0006] According to one embodiment of this application, a solar cell is provided, comprising:

[0007] A semiconductor substrate having opposing first and second surfaces, and a plurality of first side surfaces adjacent to the first and second surfaces;

[0008] A passivation contact structure is located at least on a portion of the first surface of a semiconductor substrate, and the passivation contact structure includes an interface passivation layer and a first doped semiconductor layer stacked sequentially.

[0009] In the direction from the first surface to the second surface, the first side surface includes a first region and a second region that are sequentially adjacent to each other. The first region protrudes in a direction away from the first side surface compared to the second region. A first doped semiconductor layer is also located on a portion of the surface of the first region, wherein the first doped semiconductor layer located on the first region is integrally continuous with the first doped semiconductor layer located on the first surface. The portion of the surface of the first region adjacent to the second region is not covered by the first doped semiconductor layer.

[0010] According to another embodiment of this application, a photovoltaic module is provided, including the solar cell described above.

[0011] According to the solar cell provided in the above embodiments of this application, in a direction parallel to the first surface, at least one first region on the first side protrudes in a direction away from the first side compared to the second region. This is beneficial to increase the effective area of ​​the passivation contact structure on the first surface, improve the passivation contact performance of the first surface, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.

[0012] According to the solar cell provided in the above embodiments of this application, in a direction parallel to the first surface, at least one first region on the first side protrudes in a direction away from the first side compared to the second region. Since the surface of the protruding portion of the first region is a certain distance from the surface of the first side, it can enhance the electrical isolation between the front and back of the cell (the spatial electrical isolation distance between the first and second surfaces), reducing the risk of leakage between the front and back sides. Simultaneously, during the electrode fabrication process, it can effectively prevent the slurry used for electrode fabrication from leaking and distributing over a larger area on the side of the cell, thus preventing serious damage to the cell's electrical performance. Furthermore, due to the protrusion of the first region, it can reduce the damage to the solar cell performance caused by scratches.

[0013] In the solar cell provided by the above embodiments of this application, the first doped semiconductor layer is also located on a portion of the surface of the first region, which can increase the effective area of ​​the passivated contact structure and improve the carrier collection efficiency while reducing the risk of leakage. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this application, and are not intended to limit this application.

[0015] Figure 1 This is a cross-sectional schematic diagram of a solar cell in related technologies;

[0016] Figure 2 This is a partial cross-sectional schematic diagram of a solar cell in related technologies;

[0017] Figure 3 A top view of a semiconductor substrate provided in an embodiment of this application;

[0018] Figure 4 A cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0019] Figure 5 A partial cross-sectional schematic diagram of a solar cell provided in an embodiment of this application;

[0020] Figure 6 A cross-sectional schematic diagram of a solar cell provided in another embodiment of this application;

[0021] Figure 7 A cross-sectional schematic diagram of a solar cell provided in yet another embodiment of this application;

[0022] Figure 8 A scanning electron microscope image of the first side of a solar cell provided in yet another embodiment of this application;

[0023] Figure 9 A partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application;

[0024] Figure 10 A scanning electron microscope image of a first side of a solar cell provided in another embodiment of this application;

[0025] Figure 11 A partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of this application;

[0026] Figure 12 A cross-sectional schematic diagram of a solar cell provided in another embodiment of this application;

[0027] Figure 13 A cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this application; and

[0028] Figure 14 This is a top view of the first surface of a back-contact solar cell provided in an embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1- Semiconductor substrate;

[0031] A - First surface;

[0032] B - Second surface;

[0033] C - First side view;

[0034] C1 - First Region;

[0035] C2 - Second Region;

[0036] C3 - Third Region;

[0037] 11 - First semiconductor substrate;

[0038] 12 - Second semiconductor substrate;

[0039] 13 - Third semiconductor substrate;

[0040] d1 - Height of the protrusion in the first region;

[0041] d2 - Height of the protrusion in the third region;

[0042] 2-Interface passivation layer;

[0043] 3-First doped semiconductor layer;

[0044] 31 - Third doped semiconductor layer;

[0045] 32 - Fourth doped semiconductor layer;

[0046] 4-First passivation anti-reflection layer;

[0047] 5-Second doped semiconductor layer;

[0048] 6-Second passivation anti-reflection layer;

[0049] 10 - First electrode;

[0050] 20 - Second electrode;

[0051] 111-Heavily doped semiconductor substrate;

[0052] 100 - Low birth rate area;

[0053] 200-Multiple Sub-regions;

[0054] 300 - Isolation Zone. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. However, this application can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the application thorough and complete, and to fully convey the scope of this application to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0057] In related technologies, for example, patent CN202410605390.9 provides a TOPCon battery that improves the leakage risk of bifacial batteries. It has a doped silicon layer retained around the side of the battery substrate. An etching solution is used to etch the surface of the area on the side of the silicon substrate exposed outside the doped silicon layer, preventing the doped silicon layer from remaining on the surface of the area close to the doped silicon layer and thus preventing short circuits. In the side of the silicon substrate, the surface of the area without the corresponding doped silicon layer can be lower than the surface of the area with the corresponding doped silicon layer, further reducing the leakage risk of different doping types of doped silicon layers.

[0058] Similar to patent CN202410605390.9, such as Figures 1-2 The solar cell includes: a semiconductor substrate 1 having a first surface A and a second surface B opposite to each other, and a first side surface C; an interface passivation layer 2 and a first doped semiconductor layer 3 located on the first surface A of the semiconductor substrate 1; and a first passivation antireflection layer 4; wherein, in the direction from the first surface A to the second surface B, the first side surface C of the semiconductor substrate includes an adjacent first region C1 and a second region C2, and the first region C1 protrudes in a direction away from the first side surface C compared to the second region C2.

[0059] refer to Figure 2 As shown, the first doped semiconductor layer 3 extends from the first surface A of the semiconductor substrate 1 and completely covers the first region C1. Although the above method suppresses leakage to some extent, the height of the protrusion of the first region C1 relative to the second region C2 is limited, and if the doped silicon layer formed on the second surface B of the solar cell also has a plating retention area on the first side C, the risk of leakage is still very high.

[0060] In view of this, it is necessary to provide a solar cell and photovoltaic module to address the technical problems in related technologies, such as the risk of leakage between the front and back of solar cells, the susceptibility of the sides to contamination by metal paste, or the reduction in battery performance due to scratches during handling.

[0061] Figure 3 This is a top view of a semiconductor substrate provided in an embodiment of this application.

[0062] Figure 4 This is a cross-sectional schematic diagram of a solar cell provided in an embodiment of this application.

[0063] According to an exemplary embodiment of this application, this application provides a solar cell, with reference to... Figure 3 , Figure 4 As shown, it includes:

[0064] Semiconductor substrate 1 has a first surface A and a second surface B opposite to each other, and a plurality of first side surfaces C adjacent to the first surface A and the second surface B;

[0065] A passivation contact structure is located at least on a portion of the first surface A of the semiconductor substrate 1. The passivation contact structure includes an interface passivation layer 2 and a first doped semiconductor layer 3 stacked sequentially.

[0066] In the direction from the first surface A to the second surface B, the first side surface C includes a first region C1 and a second region C2 that are sequentially adjacent to each other. The first region C1 protrudes in a direction away from the first side surface C compared to the second region C2. The first doped semiconductor layer 3 is also located on a portion of the surface of the first region C1, wherein the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A. The portion of the surface of the first region C1 adjacent to the second region C2 is not covered by the first doped semiconductor layer 3.

[0067] That is, in the direction from the first surface A to the second surface B, the semiconductor substrate 1 includes a first semiconductor base 11 and a second semiconductor base 12 integrally formed with the first semiconductor base 11; the first side surface C includes a first region C1 located on the side of the first semiconductor base 11 and a second region C2 located on the side of the second semiconductor base 12, and at least the first region C1 of the first side surface C protrudes in a direction away from the first side surface C compared to the second region C2.

[0068] According to an embodiment of this application, in a cross section parallel to the first surface A, the area of ​​the first semiconductor substrate 11 is larger than the area of ​​the second semiconductor substrate 12.

[0069] According to an embodiment of this application, the protrusion height d1 of the first region C1 compared to the second region C2 is 0.5μm to 5μm, for example, it can be 0.5μm, 1μm, 2μm, or 5μm, but is not limited to the values ​​mentioned.

[0070] According to embodiments of this application, the semiconductor substrate 1 can be a silicon substrate. Alternatively, the semiconductor substrate 1 can also be a substrate made of any semiconductor material, such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. Furthermore, the semiconductor substrate 1 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The semiconductor substrate 1 can be single-crystal or polycrystalline.

[0071] According to an embodiment of this application, the semiconductor substrate 1 is rectangular in shape, and the adjacent sides of the rectangle have chamfers. (See reference...) Figure 3 As shown, the semiconductor substrate 1 includes, for example, eight first sides C.

[0072] According to embodiments of this application, a passivation contact structure extends from a first surface A of the semiconductor substrate 1 to a portion of the surface of a first region C1 on at least one first side surface C. The passivation contact structure does not completely cover the first region C1, thus reducing the short-circuit risk associated with the passivation contact structure. Furthermore, a stepped structure exists between the first region C1 and the second region C2. Doped regions of the substrate may exist on the sidewalls of this stepped structure, i.e., on the connecting sidewalls between the first region C1 and the second region C2. The first doped semiconductor layer 3 can easily come into contact with these doped regions on the stepped sidewalls, leading to direct contact between the first doped semiconductor layer 3 and the semiconductor substrate 1, potentially causing battery defects. Therefore, positioning the first doped semiconductor layer 3 away from this sidewall can prevent the aforementioned situation from occurring.

[0073] According to an embodiment of this application, in the direction from the first surface A to the second surface B, the distance between the first doped semiconductor layer 3 on the surface of the first region C1 and the second region C2 is greater than or equal to 1 μm.

[0074] According to an embodiment of this application, in a direction perpendicular to the first surface A, the distribution width of the first doped semiconductor layer 3 in the first region A is less than 80% of the width of the first region A.

[0075] According to embodiments of this application, the ratio of the width of the first region C1 in the direction perpendicular to the first surface A to the thickness of the semiconductor substrate 1 ranges from 1% to 20%, for example, it can be 1%, 5%, 10%, 15%, or 20%, but is not limited to the values ​​listed. If the ratio range is too small, it is difficult to achieve the technical effect of increasing the passivation contact structure area and improving the carrier collection efficiency; if the ratio range is too large, leakage current is likely to occur between the first surface A and the second surface B.

[0076] According to an embodiment of this application, the thickness of the first semiconductor substrate 11 in the direction perpendicular to the first surface A ranges from 0.5 μm to 20 μm, for example, it can be 0.5 μm, 1 μm, 5 μm, 10 μm, or 20 μm, but is not limited to the values ​​mentioned above; the thickness of the first semiconductor substrate 11 in the direction perpendicular to the first surface A is the width of the first region C1 in the direction from the first surface A to the second surface B.

[0077] According to an embodiment of this application, in a direction parallel to the first surface A, at least one first side surface C has a first region C1 that protrudes from the second region C2 in a direction away from the first side surface C. This is beneficial to increase the effective area of ​​the passivation contact structure of the first surface A, improve the passivation contact performance of the first surface A, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.

[0078] According to an embodiment of this application, in a direction parallel to the first surface A, at least one first region C1 of the first side surface C protrudes from the second region C2 in a direction away from the first side surface C. Since the surface of the protruding portion of the first region is a certain distance from the surface of the second region C2, it can enhance the electrical isolation between the front and back sides of the battery, reducing the risk of leakage between the front and back sides. Simultaneously, during the electrode fabrication process, it can effectively prevent the slurry used for electrode fabrication from leaking and distributing over a larger area on the side of the battery, thus preventing serious damage to the battery's electrical performance. Furthermore, the protrusion of the first region C1 can reduce damage to the solar cell performance caused by scratches.

[0079] Because the doping concentration of the semiconductor layers is usually high, leakage current in solar cells typically occurs between semiconductor layers with different doping types. When the first region C1 has a large width in the direction perpendicular to the first surface A, the first doped semiconductor layer 3 covering the first region C1 is prone to leakage current with the second doped semiconductor layer 5 located on the second surface B.

[0080] By setting the width of the first region C1 to 1% to 20% of the thickness of the semiconductor substrate, and by placing the first doped semiconductor layer 3 on a portion of the surface of the first region C1, the risk of leakage between the first doped semiconductor layer 3 and the second surface B is reduced.

[0081] According to the solar cell provided in the above embodiments of this application, the first doped semiconductor layer is located on a portion of the surface of the first region, which can reduce the risk of leakage current while increasing the effective area of ​​the passivation contact structure and improving the carrier collection efficiency.

[0082] According to embodiments of this application, the solar cell can be a bifacial solar cell, such as a thin oxide passivated contact (TOPCon) solar cell or a heterojunction with intrinsic thin-layer (HJT) solar cell.

[0083] According to embodiments of this application, the interface passivation layer 2 includes one of an intrinsic amorphous silicon layer, a lightly doped intrinsic amorphous silicon layer (doping concentration lower than that of the first doped semiconductor layer), and a dielectric layer. The dielectric layer includes, but is not limited to, silicon oxide, aluminum oxide, doped aluminum oxide, silicon nitride, and silicon carbonitride. The first doped semiconductor layer 3 is at least one of a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped amorphous silicon layer.

[0084] According to embodiments of this application, the interface passivation layer 2 is, for example, tunneling silicon oxide, and the first doped semiconductor layer 3 is, for example, doped polysilicon.

[0085] According to embodiments of this application, the interface passivation layer 2 is, for example, intrinsic amorphous silicon, and the first doped semiconductor layer 3 is, for example, doped amorphous silicon.

[0086] According to an embodiment of this application, the TOPCon solar cell further includes: a second doped semiconductor layer 5, located at least within the second surface B of the semiconductor substrate 1, serving as the emitter region of the TOPCon solar cell; one of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is N-type, and the other of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is P-type.

[0087] According to embodiments of this application, the TOPCon solar cell further includes a second passivation and antireflection layer 6, located at least on the surface of the second doped semiconductor layer 5 away from the semiconductor substrate 1. The second passivation and antireflection layer 6 is used to achieve passivation and antireflection functions on the second surface B of the semiconductor substrate 1.

[0088] Figure 5 This is a partial cross-sectional schematic diagram of a solar cell provided in an embodiment of this application.

[0089] According to the embodiments of this application, refer to Figure 5 As shown, a heavily doped semiconductor substrate layer 111 is formed on the first surface A and the surface of the first region C1 of the semiconductor substrate 1. Here, the heavily doped semiconductor substrate layer 111 can be understood as having a doping concentration greater than that of the semiconductor substrate 1 itself. Specifically, since doping elements are added during the formation of the first doped semiconductor layer 3, some of these doping elements diffuse into the semiconductor substrate 1, resulting in a doping element concentration in a portion of the semiconductor substrate 1 near the first surface A and the first region C1 that is greater than the overall doping concentration of the semiconductor substrate 1. Optionally, the heavily doped semiconductor substrate layer 111 can be located on a portion of the surface of the first region C1 or on the entire surface of the first region C1.

[0090] Figure 6 This is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.

[0091] According to the embodiments of this application, refer to Figure 6 As shown, at least one first side surface C has a first region C1 that is an inclined plane extending from the side away from the first surface A toward the side closer to the first surface A in a direction away from the semiconductor substrate 1. This increases the surface area of ​​the first surface A and the area of ​​the passivation contact structure located on the first surface A, which is beneficial to improving carrier collection efficiency. Furthermore, it increases the surface distance of the entire first side surface in the direction perpendicular to the first surface A, which is more conducive to the isolation between the first surface A and the second surface B.

[0092] According to an embodiment of this application, a passivated contact structure extends from a first surface A of a semiconductor substrate 1 to a portion of a first region C1 on at least one first side surface C.

[0093] According to an embodiment of this application, the interface passivation layer 2 and the first doped semiconductor layer 3 are also located on a portion of the surface of the first region C1, which can increase the surface area of ​​the passivation contact structure composed of the interface passivation layer 2 and the first doped semiconductor layer 3, thereby improving the carrier collection efficiency and thus improving the efficiency of the solar cell.

[0094] According to an embodiment of this application, the first region C1 is a sloped surface, which is relatively flat and facilitates the deposition of a first passivation and antireflection layer 4 with better film quality on the first side surface C, thereby improving the passivation and antireflection effect of the first passivation and antireflection layer 4.

[0095] According to an embodiment of this application, a passivated contact structure extends from a first surface A of a semiconductor substrate 1 to a portion of the surface of a first region C1 on at least one first side surface C. The passivated contact structure does not completely cover the first region C1, thereby reducing the short-circuit risk associated with the passivated contact structure.

[0096] Figure 7 This is a cross-sectional schematic diagram of a solar cell provided in yet another embodiment of this application.

[0097] According to the embodiments of this application, since at least one first side surface C's first region C1 is an inclined surface extending from the side away from the first surface A to the side close to the first surface A in a direction away from the semiconductor substrate 1, there is no large step between the first region C1 and the second region C2. Therefore, it is beneficial to improve the passivation effect of the first passivation antireflection layer. When considering a better passivation effect, the first doped semiconductor layer 3 can also cover most of the surface of the first region C1, or even cover the entire first region C1.

[0098] Figure 8 A scanning electron microscope image of the first side of a solar cell provided in yet another embodiment of this application.

[0099] refer to Figure 8 As shown, the first region C1 has multiple holes, which are recessed into the semiconductor substrate 1 in a direction parallel to the first surface A.

[0100] According to embodiments of this application, a passivation contact structure extends from a first surface A of a semiconductor substrate 1 to a portion of a first region C1 on at least one first side surface C. A hole is recessed into the semiconductor substrate 1 through the passivation contact structure in a direction parallel to the first surface A. A first passivation antireflection layer 4 is located on the sidewalls and bottom surface of the first region C1 and the hole, allowing hydrogen from the first passivation antireflection layer 4 within the hole to enter the semiconductor substrate 1, improving the hydrogen passivation effect of the semiconductor substrate 1 and thereby increasing the efficiency of the solar cell. Generally, the first passivation antireflection layer 4 may include one or more layers of aluminum oxide, silicon nitride, and silicon oxynitride, such as a stack of aluminum oxide and silicon nitride. A large amount of hydrogen is introduced during aluminum oxide deposition, and due to the porous structure, a large amount of hydrogen can enter the semiconductor substrate 1.

[0101] According to an embodiment of this application, the distribution density of holes in the region near the first surface A is less than the distribution density in the region near the second region C2.

[0102] According to an embodiment of this application, the distribution density of pores in the region near the first surface A is low, which can reduce the recombination centers of charge carriers in the region near the first surface A, reduce charge carrier recombination, and thus improve the collection efficiency of charge carriers.

[0103] According to an embodiment of this application, the radial dimension of the hole gradually decreases in a direction parallel to the first surface A from the surface of the first region C1 to the semiconductor substrate 1. That is, the hole is an inverted pyramid structure extending in a direction parallel to the first surface A from the surface of the first region C1 to the semiconductor substrate 1.

[0104] According to embodiments of this application, the radial dimension of the hole is less than 5 μm, preferably less than 2 μm, and more preferably less than 1 μm; the radial dimension of the hole can be, for example, 4 μm, 3 μm, 2 μm, or 1 μm, but is not limited to the values ​​mentioned above.

[0105] According to embodiments of this application, the ratio of the projected area of ​​the hole in the first region A to the surface area of ​​the first region ranges from 1% to 30%, for example, it can be 1%, 5%, 10%, 20%, or 30%, but is not limited to the values ​​mentioned. If the ratio range is too small, it is difficult to achieve the technical effects of improving the passivation effect of the semiconductor substrate and increasing the passivation contact structure area, or the effect is not obvious; if the ratio range is too large, it will result in too many defects in the semiconductor substrate 1, which is not conducive to the effective collection of charge carriers.

[0106] According to embodiments of this application, the distribution density and radial dimension of the hole structure in the region C1 covered by the first doped semiconductor layer 3 or the passivation contact structure are both smaller than those in the region C1 not covered by the first doped semiconductor layer 3. This reduces damage to the passivation contact structure.

[0107] Figure 9 This is a partial cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.

[0108] Figure 10 A scanning electron microscope image of a first side of a solar cell provided in another embodiment of this application.

[0109] According to the embodiments of this application, refer to Figure 9 , Figure 10 As shown, the first region C1 has a raised ridge that extends in a direction generally parallel to the first surface A.

[0110] According to the embodiments of this application, refer to Figure 9 As shown, the first doped semiconductor layer 3 is also located on a portion of the surface of the first region C1; the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; the portion of the surface of the first region C1 adjacent to the second region C2 is not covered by the first doped semiconductor layer 3.

[0111] According to an embodiment of this application, the first region C1 has raised ridges, and the first doped semiconductor layer 3 is located on a portion of the surface of the first region C1, which can enhance the electrical isolation between the front and back of the battery, and increase the surface area of ​​the first doped semiconductor layer 3 under the condition that leakage is controllable, which is beneficial to improving the carrier collection efficiency.

[0112] Figure 11 This is a partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of this application.

[0113] According to the embodiments of this application, refer to Figure 11 As shown, the first region C1 has raised ridges that extend in a direction approximately parallel to the first surface A, which can increase the surface area of ​​the first region C1. With controllable leakage current, the first doped semiconductor layer 3 completely covers the first region C1, which can increase the surface area of ​​the first doped semiconductor layer 3, thereby improving carrier collection efficiency.

[0114] According to an embodiment of this application, since at least one first side surface C has a raised ridge on a first region C1, the ridge extends in a direction generally parallel to the first surface A; that is, a portion of the first region C1 near the second region C2 is an inclined surface extending from one side of the second region C2 toward the side of the ridge in a direction away from the semiconductor substrate 1.

[0115] There may be no significant step, or even no step, between the first region C1 and the second region C2. This is beneficial for improving the passivation effect of the passivation and antireflection layer. When considering the passivation effect, the first doped semiconductor layer can cover most or even all of the surface of the first region C1. According to an embodiment of this application, the second region C2 has a tower base structure. The width of the first region C1 in the direction perpendicular to the first surface A is smaller than the size of the tower base structure of the second region C2, wherein the size of the tower base structure is defined as the side length or diagonal length of the tower base structure.

[0116] According to an embodiment of this application, the TOPcon solar cell further includes a first electrode 10, which passes through a first passivation antireflection layer 4 and is in electrical contact with a first doped semiconductor layer 3; and a second electrode 20, which passes through a second passivation antireflection layer 6 and is in electrical contact with a second doped semiconductor layer 5.

[0117] According to an embodiment of this application, the distance between the first electrode 10 and the first region C1 in the direction perpendicular to the thickness of the semiconductor substrate 1 (parallel to the first surface A) is greater than or equal to 300 μm. Therefore, during the electrode fabrication process, leakage of the slurry used to fabricate the electrode can be effectively prevented from spreading over a larger area on the side of the battery, thus preventing serious damage to the battery's electrical performance.

[0118] According to embodiments of this application, the first doped semiconductor layer 3 is one or more of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. For example, the first doped semiconductor layer 3 is doped polycrystalline silicon, the thickness of which is typically between 80 nm and 500 nm, and the doping concentration is typically 1*10⁻⁶. 17 ~1*10 21 atoms / cm 3 ...

[0119] Figure 12 This is a cross-sectional schematic diagram of a solar cell provided in another embodiment of this application.

[0120] According to the embodiments of this application, refer to Figure 12 As shown, the first side surface C also includes a third region C3 adjacent to the second region C2, and the third region C3 is closer to the second surface B than the second region C2. That is to say, the solar cell also includes a third semiconductor substrate 13, which is integrally formed with the second semiconductor substrate 12, and the third semiconductor substrate 13 is closer to the second surface B than the second semiconductor substrate 12.

[0121] According to an embodiment of this application, the third region C3 protrudes in a direction away from the first side C compared to the second region C2, and the protrusion height d2 of the third region C3 is greater than the protrusion height d1 of the first region C1.

[0122] According to an embodiment of this application, the protrusion height d2 of the third region C3 is 3μm to 10μm, for example, it can be 3μm, 5μm, 6μm, 8μm, or 10μm, but is not limited to the values ​​mentioned.

[0123] According to an embodiment of this application, when a second doped semiconductor layer 5 is formed on the second surface B, the second doped semiconductor layer 5 is deposited around the first side surface C. When the second doped semiconductor layer 5 deposited around the first side surface C is removed using an alkaline solution, a third region C3 is formed in the area of ​​the first side surface C near the second surface B. The third region C3 protrudes in a direction away from the first side surface C compared to the second region C2. This increases the spatial electrical isolation distance between the first surface A and the second surface B, effectively preventing leakage on the first side of the solar cell. Furthermore, it effectively prevents the paste used to prepare the electrode on the second surface B from leaking to the first side, thereby avoiding damage to the cell's performance.

[0124] In addition, the third region C3 protrudes in a direction away from the first side C compared to the second region C2, which can increase the junction area of ​​the PN junction formed by the semiconductor substrate 1 and the second doped semiconductor layer 5, which is beneficial to improving the photocurrent of the solar cell.

[0125] According to embodiments of this application, the solar cell is a solar cell with a single-sided electrode, such as an interdigitated back contact (IBC) cell.

[0126] Figure 13 This is a cross-sectional schematic diagram of a back-contact solar cell provided in an embodiment of this application.

[0127] Figure 14 This is a top view of the first surface of a back-contact solar cell provided in an embodiment of this application.

[0128] According to an exemplary embodiment of this application, reference is made to Figure 13 , Figure 14 As shown, this application provides a back-contact solar cell.

[0129] According to an embodiment of this application, a first surface A of a semiconductor substrate 1 has an electrode collection region, which includes a plurality of minority carrier regions 100 and a plurality of majority carrier regions 200 alternately distributed along a second direction, and an isolation region 300 is provided between adjacent minority carrier regions 100 and majority carrier regions 200.

[0130] According to an embodiment of this application, the first doped semiconductor layer 3 includes a third doped semiconductor layer 31 and a fourth doped semiconductor layer 32; wherein, the third doped semiconductor layer 31 for collecting and venting minority carriers is disposed in the minority carrier region 100; and the fourth doped semiconductor layer 32 for collecting and venting majority carriers is disposed in the majority carrier region 200. The third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 have opposite conductivity types; one of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 is N-type, and the other is P-type. For example, the conductivity type of the third doped semiconductor layer 31 can be N-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is P-type; or, the conductivity type of the third doped semiconductor layer 31 can be P-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is N-type.

[0131] According to the embodiments of this application, refer to Figure 13 , Figure 14 As shown, a plurality of third doped semiconductor layers 31 extend in a first direction within a first plane parallel to the first surface A.

[0132] According to an embodiment of this application, a plurality of fourth doped semiconductor layers 32 extend in a first direction, and a plurality of third doped semiconductor layers 31 and a plurality of fourth doped semiconductor layers 32 are alternately distributed on a first surface A in a second direction perpendicular to the first direction within a first plane.

[0133] According to an embodiment of this application, the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 are also located on a portion of the surface of the first region C1.

[0134] According to an embodiment of this application, a first doped semiconductor layer 3 located on the minority carrier region 100 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a portion of the surface of the first region C1 on the first side surface C; and / or, a second doped semiconductor layer 5 located on the majority carrier region 200 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a portion of the surface of the first region C1 on the first side surface C.

[0135] According to an embodiment of this application, a first interface passivation layer is further formed between the semiconductor substrate 1 and the third doped semiconductor layer 31. A second interface passivation layer is further formed between the semiconductor substrate 1 and the fourth doped semiconductor layer 32.

[0136] According to embodiments of this application, the first interface passivation layer and / or the second interface passivation layer include one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.

[0137] According to an embodiment of this application, the first passivation antireflection layer 4 of the aforementioned back-contact solar cell is located on the surfaces of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 away from the semiconductor substrate 1, and on the semiconductor substrate 1 of the isolation region 300. The material of the first passivation antireflection layer 4 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon. The first passivation antireflection layer 4 is used to achieve surface passivation and antireflection functions of the back-contact solar cell.

[0138] According to an embodiment of this application, the aforementioned back-contact solar cell further includes: a first electrode 10, which penetrates the first passivation and antireflection layer 4 and is in electrical contact with the third doped semiconductor layer 31; and a second electrode 20, which penetrates the first passivation and antireflection layer 4 and is in electrical contact with the fourth doped semiconductor layer 32.

[0139] According to the embodiments of this application, the width of the first electrode 10 is 5μm to 600μm, for example, it can be 5μm, 10μm, 100μm, 500μm, or 600μm, but is not limited to the values ​​mentioned.

[0140] According to embodiments of this application, the width of the second electrode 20 is 5μm to 600μm, for example, it can be 5μm, 10μm, 100μm, 500μm, or 600μm, but is not limited to the values ​​mentioned.

[0141] According to embodiments of this application, the materials of the first electrode 10 and / or the second electrode 20 include, but are not limited to, one or more of metals, metal oxides, metal nitrides, metal carbides, and metal sulfides. The first electrode 10 and / or the second electrode 20 may also be other conductive connecting materials such as graphene.

[0142] According to an embodiment of this application, during the electrode preparation process, an electrode paste is coated onto the first passivation and antireflection layer 4 on the first surface A, and then sintered so that the electrode paste passes through the first passivation and antireflection layer 4 and forms contact with the doped semiconductor film layer.

[0143] According to an exemplary embodiment of this application, this application provides a photovoltaic module including the solar cell described above.

[0144] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0145] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate (1) having opposing first surfaces (A) and second surfaces (B), and a plurality of first side surfaces (C) adjacent to the first surface (A) and the second surface (B); A passivation contact structure is located at least on a portion of the first surface (A) of the semiconductor substrate (1), the passivation contact structure comprising an interface passivation layer (2) and a first doped semiconductor layer (3) stacked sequentially. Wherein, in the direction from the first surface (A) to the second surface (B), the first side surface (C) includes a first region (C1) and a second region (C2) that are sequentially adjacent to each other, and the first region (C1) protrudes in a direction away from the first side surface (C) compared to the second region (C2); The first doped semiconductor layer (3) is also located on a portion of the surface of the first region (C1), wherein the first doped semiconductor layer (3) located on the first region (C1) is integrally continuous with the first doped semiconductor layer (3) located on the first surface (A); the portion of the surface of the first region (C1) adjacent to the second region (C2) is not covered by the first doped semiconductor layer (3). The protrusion height of the first region (C1) is 0.5μm~5μm compared to the second region (C2).

2. The solar cell according to claim 1, characterized in that, The ratio of the width of the first region (C1) in the direction perpendicular to the first surface (A) to the thickness of the semiconductor substrate (1) ranges from 1% to 20%.

3. The solar cell according to claim 1, characterized in that, The width of the first region (C1) in the direction perpendicular to the first surface (A) is 0.5 μm to 20 μm.

4. The solar cell according to claim 1, characterized in that, In the direction perpendicular to the first surface (A), the distribution width of the first doped semiconductor layer (3) in the first region (C1) is less than 80% of the width of the first region (C1).

5. The solar cell according to any one of claims 1-4, characterized in that, At least one of the first regions (C1) of the first side surface (C) is an inclined surface extending from the side away from the first surface (A) toward the side closer to the first surface (A) in a direction away from the semiconductor substrate (1).

6. The solar cell according to any one of claims 1-4, characterized in that, The first region (C1) includes an edge extending parallel to the first surface (A).

7. The solar cell according to claim 6, characterized in that, The portion of the first region (C1) near the second region (C2) is an inclined surface extending from one side of the second region (C2) toward the edge side in a direction away from the semiconductor substrate (1).

8. The solar cell according to any one of claims 1-4, characterized in that, The first region (C1) has a plurality of holes recessed into the semiconductor substrate (1) in a direction parallel to the first surface (A).

9. The solar cell according to claim 8, characterized in that, The distribution density of the holes in the region near the first surface (A) is less than that in the region near the second region (C2).

10. The solar cell according to claim 9, characterized in that, The radial dimension of the hole gradually decreases in the direction from the surface of the first region (C1) to the semiconductor substrate (1); And / or, the radial dimension of the hole is less than 5 μm.

11. The solar cell according to any one of claims 1-4, characterized in that, Also includes: The second doped semiconductor layer (5) is located at least within the second surface (B) of the semiconductor substrate (1); as well as The second passivation antireflection layer (6) is located at least on the surface of the second doped semiconductor layer (5) away from the semiconductor substrate (1).

12. The solar cell according to any one of claims 1-4, characterized in that, The solar cell is a back-contact solar cell. The first doped semiconductor layer (3) includes a plurality of third doped semiconductor layers (31) and a plurality of fourth doped semiconductor layers (32), wherein the plurality of third doped semiconductor layers (31) and the plurality of fourth doped semiconductor layers (32) are alternately distributed on the first surface (A). Among them, one of the third doped semiconductor layer (31) and the fourth doped semiconductor layer (32) is N-type, and the other of the third doped semiconductor layer and the fourth doped semiconductor layer is P-type.

13. The solar cell according to any one of claims 1-4, characterized in that, Also includes: The first passivation antireflection layer (4) is located at least on the surface of the passivation contact structure away from the semiconductor substrate (1); The first electrode (10) penetrates the first passivation antireflection layer (4) and contacts the first doped semiconductor layer (3); Wherein, the distance between the first electrode (10) and the first region (C1) in the direction parallel to the first surface (A) is greater than or equal to 300 μm.

14. The solar cell according to any one of claims 1-4, characterized in that, The first side surface (C) also includes a third region (C3) adjacent to the second region (C2), the third region (C3) being closer to the second surface (B) than the second region (C2); The third region (C3) protrudes in a direction away from the first side (C) compared to the second region (C2), and the protrusion height of the third region (C3) is greater than the protrusion height of the first region (C1).

15. The solar cell according to claim 1, characterized in that, A heavily doped semiconductor substrate layer (111) is formed on the surface of the first surface (A) and the first region (C1) of the semiconductor substrate (1), and the heavily doped semiconductor substrate layer (111) is located on at least a portion of the surface of the first region (C1).

16. A photovoltaic module, characterized in that, Includes the solar cell as described in any one of claims 1 to 15.

Images