Non-cascaded MIMO channel expander for radar chips

Abstract

A receive spreader in an integrated circuit can include N phase adjustment circuits that adjust phases of N receive signals from N receive antennas, and an N:1 multiplexer that coherently combines the N receive signals into an output signal that is provided to a transceiver chip. Further, a transmit spreader in the integrated circuit can include a 1:M demultiplexer that coherently separates a transmit signal from the transceiver chip into M transmit signals, where N and M are non-zero integers that can be different, and M phase adjustment circuits that adjust phases of the M transmit signals provided to M transmit antennas. Note that the integrated circuit can be coupled to a second integrated circuit that phase shifts the output signal and the transmit signal based at least in part on an oscillator signal. Further, control signals between the integrated circuit and the second integrated circuit can be synchronized.

Description

Technical Field

[0001] This disclosure relates to techniques for using extender chips to increase the number of transmitters and receivers in a multiple-input multiple-output (MIMO) radar system. Background Technology

[0002] To provide improved safety and more convenient transportation options, many automakers are including additional sensors and / or features in their vehicles. For example, autonomous vehicles typically include a wide variety of sensors, such as acoustic and / or electromagnetic sensors that monitor the surrounding environment to detect other vehicles, people, animals, or obstacles. However, many sensors that can include a large number of transmitters and receivers, such as MIMO radar systems, remain prohibitively expensive. Summary of the Invention

[0003] The aforementioned drawbacks can be addressed, at least in part, by MIMO radar systems with channel extenders to further increase the number of receive and / or transmit antennas that a given radar transceiver can support. An exemplary radar system includes: a radar transceiver for generating a transmit signal and down-converting at least one receive signal; and a receive-side extender coupled to a plurality of receive antennas to obtain a plurality of input signals, adjustablely phase-shifting each of the plurality of input signals to generate a set of phase-shifted signals, and coupled to the radar transceiver to provide at least one receive signal, which is the sum of the phase-shifted signals.

[0004] An exemplary receiver-side extender includes: a plurality of phase shifters, each providing an adjustable phase shift to a corresponding input signal; a power combiner that combines the outputs of the plurality of phase shifters to form a received signal; and an internal memory that stores different sequences of phase shift adjustments for each of the plurality of phase shifters. The receiver-side extender may further include an external interface for controlling the timing of supplying the different sequences from the memory to the plurality of phase shifters.

[0005] An exemplary transmitter-side extender includes: a power divider that divides a corresponding transmitted signal into multiple signal copies; a set of multiple phase shifters, each providing an adjustable phase shift for one of the multiple signal copies; a set of power amplifiers, each deriving one of the multiple output signals from the output of a corresponding phase shifter among the multiple phase shifters; and an internal memory that stores different sequences of phase shift adjustments for each of the multiple phase shifters. The transmitter-side extender may further include an external interface for controlling the timing of supplying the different sequences from the memory to the multiple phase shifters.

[0006] An exemplary radar detection method includes: generating a chirped waveform; deriving a transmitted signal from the chirped waveform; obtaining a plurality of input signals from a plurality of receiving antennas; applying an adjustable phase shift to each of the plurality of input signals to provide a plurality of phase-shifted input signals; summing the plurality of phase-shifted input signals to form a received signal; combining the received signal with the chirped waveform to obtain a down-converted received signal; deriving a set of digital input signals from the down-converted received signal; and processing the set of digital input signals to determine the reflected energy as a function of distance or travel time.

[0007] Exemplary systems, extenders, and methods can be used individually or in any suitable combination with one or more of the following optional features: 1. The transmitted signal includes a chirped sequence. 2. A receiver-side extender adjusts the phase shift of multiple input signals once for each chirp. 3. The adjusted phase shift provides progressive phase shifts to the multiple input signals for beam steering. 4. The adjusted phase shift provides code division multiplexing of the multiple input signals. 5. A radar transceiver processes at least one down-converted received signal to obtain a demultiplexed set of digital input signals. 6. The receiver-side extender adjusts the phase shift of the multiple input signals multiple times during each chirp. 7. The adjusted phase shift provides different frequency shifts, different sweep rates, or different code modulations to the multiple input signals. 8. One or more transmitter-side extenders, each coupled to a radar transceiver to obtain a corresponding transmitted signal, and each coupled to a corresponding set of multiple transmit antennas to provide a set of multiple output signals, each of which has an adjustable phase shift. 9. The receiver-side extender adjusts the phase shift of the plurality of output signals once for each chirp. 10. The adjusted phase shift provides progressive phase shifts to the plurality of output signals for beam steering. 11. The adjusted phase shift provides orthogonal code modulation to the plurality of output signals. 12. The radar transceiver processes at least one down-converted received signal to obtain a demultiplexed digital input signal for each transmit antenna. 13. The receiver-side extender adjusts the phase shift of the plurality of output signals multiple times during each chirp. 14. The adjusted phase shift provides different frequency shifts, different sweep rates, or different code modulations to the plurality of output signals. 15. Each transmit-side extender includes: a power divider that divides a corresponding transmit signal into multiple signal copies; a set of multiple phase shifters, each providing an adjustable phase shift to one of the plurality of signal copies; and a set of power amplifiers, each power amplifier deriving one of the plurality of output signals from the output of a corresponding phase shifter among the multiple phase shifters. 16. Each receiver-side extender includes: a set of multiple phase shifters, each providing an adjustable phase shift for one of the multiple input signals; and a power combiner that combines the outputs of the multiple phase shifters to form a corresponding received signal. 17. Each extender includes internal memory to store different sequences of phase shift adjustment for each of the multiple input signals. 18. Each extender includes an external interface that controls the timing for supplying the different sequences from the memory to the multiple phase shifters. 19. The radar transceiver supplies a clock signal to each of the extenders to control the timing for supplying the phase shift adjustment sequences from the internal memory to the multiple phase shifters. 20. Acquisition, application, and summation are performed by a receiver-side extender coupled to the radar transceiver, which performs the combination, derivation, and processing.

[0008] An embodiment of an integrated circuit including a receiver extender is described. The integrated circuit includes: N receive (or input) contacts coupled to N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receive contacts, wherein a given phase adjustment circuit among the N phase adjustment circuits is coupled to a given receive contact among the N receive contacts; an N:1 multiplexer coupled to the N phase adjustment circuits; an amplifier coupled to the N:1 multiplexer; an output contact coupled to the amplifier; and control circuitry controlling the N phase adjustment circuits. Furthermore, the integrated circuit is coupled to a second integrated circuit, wherein the second integrated circuit performs phase shifting and / or frequency shifting of the output signal at least partially based on an oscillator signal. During operation, the integrated circuit receives N receive signals at the N receive contacts. After phase adjustment of the N receive signals using the N phase adjustment circuits, the integrated circuit combines the N receive signals using the N:1 multiplexer. The integrated circuit then amplifies the combined receive signals using the amplifier, and the output signal is provided by the amplifier to the second integrated circuit at the output contact. Furthermore, the control signals are synchronized between the control circuit and the second control circuit on the second integrated circuit, while the oscillator signals are asynchronous between the integrated circuit and the second integrated circuit.

[0009] Note that N received signals can be coherently combined (e.g., by maintaining the relative phase of the N received signals during the combination).

[0010] Furthermore, N phase adjustment circuits can apply different phase adjustments to N received signals.

[0011] Furthermore, the configuration of the integrated circuit and the second integrated circuit can differ from the cascaded configuration.

[0012] Furthermore, this integrated circuit can be different from the second integrated circuit.

[0013] In some embodiments, the N phase adjustment circuits are implemented in the analog domain.

[0014] Note that the second integrated circuit can perform: analog-to-digital conversion (ADC); and signal processing.

[0015] Furthermore, this integrated circuit can increase the number of receiving antennas coupled to the second integrated circuit.

[0016] Furthermore, the frequency shift can be from a frequency band in the RF band to a second frequency band smaller than that band. For example, the second frequency band can be: an intermediate frequency band greater than DC; or the baseband.

[0017] In addition, the second integrated circuit may include a transceiver chip.

[0018] Another embodiment provides a third integrated circuit including a transmit extender. The third integrated circuit includes: an input contact; a 1:M demultiplexer coupled to the input contact, where M is a non-zero integer; M phase adjustment circuits coupled to the 1:M demultiplexer; M power amplifiers coupled to the M phase adjustment circuits, wherein a given power amplifier among the M power amplifiers is coupled to a given phase adjustment circuit among the M phase adjustment circuits; M output (or transmit) contacts coupled to the M power amplifiers and M transmit antennas, wherein a given output contact among the M output contacts is coupled to a given power amplifier; and a third control circuit for controlling the M phase adjustment circuits. Furthermore, the integrated circuit is coupled to a second integrated circuit, wherein the second integrated circuit performs phase shifting and / or frequency shifting of the transmit signal at least partially based on an oscillator signal. During operation, the third integrated circuit receives the transmit signal from the second integrated circuit at the input contact. The third integrated circuit then uses the 1:M demultiplexer to separate the transmit signal into M transmit signals. Furthermore, the third integrated circuit uses the M phase adjustment circuits to phase adjust the M transmit signals. Next, the third integrated circuit uses M power amplifiers to amplify the M transmit signals and outputs the M transmit signals at M output contacts. Furthermore, the control signals are synchronized between the third control circuit and the second control circuit on the second integrated circuit, but the oscillator signals are asynchronous between the second and third integrated circuits.

[0019] Note that the M transmitted signals can be coherently separated (e.g., by maintaining the phase of the transmitted signals among the M transmitted signals during separation).

[0020] Furthermore, the M phase adjustment circuits can apply different phase adjustments to the M transmitted signals.

[0021] Furthermore, the configurations of the second and third integrated circuits can differ from the cascaded configurations.

[0022] In addition, the third integrated circuit may be different from the second integrated circuit.

[0023] In some embodiments, the M phase shift adjustment circuits are implemented in the analog domain.

[0024] Note that the second integrated circuit can perform: ADC; and signal processing.

[0025] Furthermore, N can be different from M.

[0026] Furthermore, the third integrated circuit can increase the number of transmission channels output by the second integrated circuit.

[0027] Additionally, the frequency shift can be from a frequency band in the RF circuit to a second frequency band smaller than that band. For example, the second frequency band could be: an intermediate frequency band greater than DC; or the baseband.

[0028] In some embodiments, the second integrated circuit may include a transceiver chip.

[0029] Another embodiment provides a fourth integrated circuit, which includes a receive extender and a transmit extender.

[0030] Another embodiment provides a system comprising a second integrated circuit and one or more of the following: the integrated circuit, a third integrated circuit, and / or a fourth integrated circuit.

[0031] Another embodiment provides a method for expanding an integrated circuit. The method includes at least some of the operations performed by the said integrated circuit, a second integrated circuit, a third integrated circuit, and / or a fourth integrated circuit.

[0032] This invention is provided for the purpose of illustrating some exemplary embodiments to provide a basic understanding of some aspects of the subject matter described herein. Therefore, it will be understood that the above features are illustrative and should not be construed as narrowing the scope or spirit of the subject matter described herein in any way. Other features, aspects, and advantages of the subject matter described herein will become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0033] Figure 1 This is a diagram illustrating an example of a vehicle equipped with radar sensors according to some embodiments of the present disclosure.

[0034] Figure 2 This is a block diagram illustrating an example of a driver assistance system according to some embodiments of the present disclosure.

[0035] Figure 3 This is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure.

[0036] Figure 4 This is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure.

[0037] Figure 5 This is a block diagram illustrating an example of a radar transceiver chip according to some embodiments of the present disclosure.

[0038] Figure 6 This is a block diagram illustrating an example of a radar system with an extender chip according to some embodiments of the present disclosure.

[0039] Figure 7 This is a block diagram illustrating an example of an input expander chip according to some embodiments of the present disclosure.

[0040] Figure 8This is a block diagram illustrating an example of an output expander chip according to some embodiments of the present disclosure.

[0041] Figure 9A and Figure 9B This is a block diagram illustrating examples of data cubes representing the acquired set of radar measurements and the transformed set of radar measurements, respectively, according to some embodiments of the present disclosure.

[0042] Figure 10 This is a flowchart illustrating an example data stream in a radar system according to some embodiments of the present disclosure.

[0043] Figure 11 This is a flowchart illustrating an example of a method for radar detection according to some embodiments of the present disclosure.

[0044] Figure 12 This is a block diagram illustrating an example of a cascaded chip according to some embodiments of the present disclosure.

[0045] Figure 13 This is a block diagram illustrating examples of radar chips and extender chips according to some embodiments of the present disclosure.

[0046] Figure 14 This is a block diagram illustrating examples of radar chips and transmit channel extender chips according to some embodiments of the present disclosure.

[0047] Figure 15 This is a block diagram illustrating examples of radar chips and receive channel extender chips according to some embodiments of the present disclosure.

[0048] Note that in these figures, the same reference numerals always refer to the corresponding parts. Furthermore, multiple instances of the same part are designated by a common prefix separated from the instance number by a dash. Detailed Implementation

[0049] An integrated circuit including a receiver extender is described. This integrated circuit may include: N receive contacts coupled to N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receive contacts, wherein a given phase adjustment circuit among the N phase adjustment circuits is coupled to a given receive contact among the N receive contacts; an N:1 multiplexer coupled to the N phase adjustment circuits; an amplifier coupled to the N:1 multiplexer; an output contact coupled to the amplifier; and control circuitry controlling the N phase adjustment circuits. Furthermore, the integrated circuit may be coupled to a second integrated circuit, wherein the second integrated circuit performs phase shifting and / or frequency shifting of the output signal at least in part based on an oscillator signal. During operation, the integrated circuit can receive N receive signals at the N receive contacts. After phase adjustment of the N receive signals using the N phase adjustment circuits, the integrated circuit can combine the N receive signals using the N:1 multiplexer. The integrated circuit can then amplify the combined receive signals using the amplifier, and the output signal can be provided by the amplifier to the second integrated circuit at the output contact. Furthermore, the control signals between the control circuit and the second control circuit on the second integrated circuit can be synchronized, and the oscillator signals between the integrated circuit and the second integrated circuit can be asynchronous.

[0050] Furthermore, a third integrated circuit including a transmit extender is described. The third integrated circuit may include: input contacts; a 1:M demultiplexer coupled to the input contacts, where M is a non-zero integer; M phase adjustment circuits coupled to the 1:M demultiplexer; M power amplifiers coupled to the M phase adjustment circuits, wherein a given power amplifier among the M power amplifiers is coupled to a given phase adjustment circuit among the M phase adjustment circuits; M output contacts coupled to the M power amplifiers and M transmit antennas, wherein a given output contact among the M output contacts is coupled to a given power amplifier; and a third control circuit for controlling the M phase adjustment circuits. Furthermore, this integrated circuit may be coupled to a second integrated circuit, wherein the second integrated circuit performs phase shifting and / or frequency shifting of the transmit signal at least partially based on an oscillator signal. During operation, the third integrated circuit may receive the transmit signal from the second integrated circuit at the input contacts. The third integrated circuit can then use the 1:M demultiplexer to separate the transmit signal into M transmit signals. Furthermore, the third integrated circuit can use the M phase adjustment circuits to perform phase adjustment on the M transmit signals. Next, the third integrated circuit can use M power amplifiers to amplify M transmit signals and can output M transmit signals at M output contacts. Furthermore, the control signals between the third control circuit and the second control circuit on the second integrated circuit can be synchronized, and the oscillator signals between the second and third integrated circuits can be asynchronous.

[0051] Furthermore, a fourth integrated circuit, including a receiver extender and a transmitter extender, is described.

[0052] By implementing receive spread and / or transmit spread, these circuitry techniques can reduce the cost and complexity of MIMO radar systems, including the aforementioned integrated circuit, second integrated circuit, third integrated circuit, and / or fourth integrated circuit. For example, compared to the second integrated circuit, the integrated circuit, third integrated circuit, and / or fourth integrated circuit can be smaller and consume less power. Furthermore, the circuitry techniques can improve the performance of the MIMO radar system. In particular, the integrated circuit and / or fourth integrated circuit can increase the number of receive antennas coupled to the second integrated circuit, and the third integrated circuit and / or fourth integrated circuit can increase the number of transmit channels output by the second integrated circuit. Therefore, these circuitry techniques enable the use of MIMO and its application in various applications such as automotive applications.

[0053] In the following discussion, a vehicle may include: a car, a sport utility vehicle, a truck, a motorcycle, a train, an airplane, a boat, or another type of transport. However, in the following discussion, a car is used as an illustrative example of a vehicle.

[0054] Furthermore, in the discussion below, the vehicle may use one or more types of sensors to perform measurements associated with objects in the surrounding environment. While a wide variety of sensor types can be used, radar sensors are used as illustrative examples in the discussion below. Radar sensors may perform measurements using at least one of a wide variety of operating modes, such as pulse or continuous wave, and may involve the use of one or more types of modulation, such as amplitude, frequency, and / or phase modulation. In some embodiments, frequency-modulated continuous wave (FMCW) radar is used. Additionally, transmitted and received radar signals (e.g., having a carrier frequency in a radar band such as between 3 MHz and 100 GHz) may be generated and / or processed in the analog and / or digital domains.

[0055] Furthermore, in the following discussion, the terms "approximately" or "substantially" mean that the expected value is close to the stated value. However, minor variations may occur that prevent the value from being exactly as stated. Therefore, an expected variance such as a 10% difference is a reasonable and known acceptable variance relative to the statements or desired objectives of one or more embodiments of this disclosure. Additionally, the terms "first," "second," "next," "previous," "before," "after," and other similar terms are used for descriptive and illustrative purposes only and are not intended to limit any configuration of elements or sequences of operations used in the various embodiments of this disclosure. Note that the terms "coupled," "connected," or others are not intended to limit such interaction and signal transmission between two or more devices, systems, components, or others to direct interaction; indirect coupling and connections may also occur.

[0056] An embodiment of the circuit technology will now be described. Figure 1 An illustration shows an example of a vehicle 110 equipped with a radar antenna array, which includes: an antenna 112 for short-range sensing (e.g., for parking assistance), an antenna 114 for medium-range sensing (e.g., for monitoring stop-and-go traffic and overtaking events), and an antenna 116 for long-range sensing (e.g., for adaptive cruise control and collision warning). These antennas can all be positioned behind the front bumper. An antenna 118 for short-range sensing (e.g., for reversing assistance) and an antenna 120 for medium-range sensing (e.g., for rear-end collision warning) can be positioned behind the rear bumper. Furthermore, an antenna 122 for short-range sensing (e.g., for blind spot monitoring and side obstacle detection) can be positioned behind the vehicle's fenders. Each antenna and each antenna set can be grouped into one or more arrays. Additionally, each array can be controlled by a radar array controller 205. Figure 2 Control. In some embodiments, a given antenna set can perform MIMO radar sensing. The type, number, and configuration of sensors vary in sensor arrangements for vehicles with driver assistance and autonomous driving features. Vehicles may employ sensor arrangements to detect and measure the distance / direction to / pointed to objects in various detection areas, enabling the vehicle to navigate while avoiding other vehicles and obstacles. While the foregoing discussion exemplifies a vehicle 110 with radar sensors, in other embodiments, vehicle 110 may include additional types of sensors such as LiDAR, ultrasonic sensors, cameras, etc.

[0057] Figure 2A block diagram illustrating an example of a driver assistance system is presented. This driver assistance system may include an electronic control unit (ECU) 210 at the center of a star topology, coupled to various sensors 212 and a radar array controller 214. However, other topologies may include serial, parallel, and hierarchical (tree) topologies. The radar array controller 214 may couple a radio frequency (RF) front end to transmitting and receiving antennas (e.g., in antenna 114) to transmit electromagnetic waves, receive reflections, and determine the spatial relationship between the vehicle and its surroundings. Furthermore, the radar array controller 214 may be coupled to carrier signal generators. In some embodiments, the radar array controller 214 may control the timing and sequence of actuation of multiple carrier signal generators.

[0058] To provide automatic parking assistance, the ECU 210 can be coupled to a set of actuators, such as: a turn signal actuator 216, a steering actuator 218, a brake actuator 220, and / or a throttle actuator 222. Furthermore, the ECU 210 can be coupled to an interactive user interface 224 to accept user input and display various measurements and system statuses.

[0059] Using user interface 224, sensors, and actuators, ECU 210 can provide: automatic parking, assisted parking, lane change assist, obstacle and blind spot detection, autonomous driving, and / or other desired features. In vehicle 110 ( Figure 1 During operation, sensor measurements can be acquired by ECU 210 and used by ECU 210 to determine the state of vehicle 110. Furthermore, ECU 210 can act on the state and incoming information to actuate signaling and control transducers to regulate and maintain the operation of vehicle 110. For example, operations that ECU 210 can provide include driver assistance features such as automatic parking, lane following, automatic braking, and automatic driving.

[0060] Furthermore, to obtain measurement results, ECU 210 can employ a MIMO radar system. The radar system operates by emitting electromagnetic waves that travel outward from the transmitting antenna and are then reflected back to the receiving antenna. The reflector can be any object that moderately reflects the electromagnetic waves along their path. By measuring the travel time of the electromagnetic waves from the transmitting antenna to the reflector and back to the receiving antenna, the radar system can determine the distance to the reflector. Additionally, by measuring the Doppler shift of the electromagnetic waves, the radar system can determine the distance of the reflector relative to vehicle 110. Figure 1 The speed of the reflector. When using multiple transmitting or receiving antennas, or when multiple measurements are taken at different locations, the radar system can determine the direction pointing at the reflector and thus track the reflector relative to the vehicle 110 ( Figure 1The location of the radar is determined by more sophisticated processing. Multiple reflectors can be tracked. In some embodiments, the radar system may employ array processing to "scan" a directional beam of electromagnetic waves and construct the vehicle 110 ( Figure 1 Images of surrounding objects in the environment. Typically, radar systems can be implemented using pulse and / or continuous wave methods.

[0061] Figure 3 A block diagram illustrating an example radar system 310 with a MIMO configuration is presented, wherein J transmitters are jointly coupled to M transmit antennas 312 to transmit transmit signals 316 (e.g., simultaneously), where J and M are non-zero integers. The M possible transmit signals 316 can be reflected from one or more reflectors or targets 314 to be received as receive signals 318 via N receive antennas 320 coupled to P receivers, where N and P are non-zero integers. Each receiver can extract the amplitude and phase or travel delay associated with each of the M transmit signals 316, thereby enabling the system to obtain N·M spatially distinct measurements (but only J·P of these measurements can be obtained simultaneously). Note that each measurement can indicate the distance to multiple targets, and when combined in various ways, can further indicate the direction and / or velocity of each target. By using time-division multiplexing and / or orthogonal coding, the processing requirements associated with each receiver extracting the J measurements can be reduced. Furthermore, available antennas can be systematically reused with available transmitters and receivers to collect a complete set of measurements for radar imaging.

[0062] Figure 4 The illustrated radar transceiver circuit 410 is shown (e.g., Figure 3A block diagram of an example of a radar system 310. In some embodiments, the radar transceiver circuit 410 is implemented as an integrated circuit in a packaged chip. The radar transceiver circuit 410 may include: a carrier signal (chirp) generator 412 that converts a local oscillator (LO) signal into an FMCW signal (such as a signal with a linearly swept chirp sequence), a phase shifter 414 (and more generally, an encoder circuit that can implement Doppler code multiplexing), an amplifier 416, and / or a transmit antenna 312 that can transmit a signal 316 based at least in part on the output of the carrier signal generator 412. Furthermore, the radar transceiver circuit 410 may include: a receiver antenna 320, a low-noise amplifier (LNA) 418, and / or a mixer 420 (which, in some embodiments, can implement Doppler code multiplexing). The mixer 420 can mix the received signal 318 detected by the receiver antenna 312 with the signal from the carrier signal generator 412. Furthermore, a low-noise amplifier 418 can be used to amplify the received signal 318 detected by the receiving antenna 320. In some embodiments, the radar transceiver circuit 410 may include: a sensitivity time controller and equalizer (not shown), a wideband (BB) filter 422, an ADC 424, and / or a processor 426 that can perform further processing (such as Fourier transform) on the received signal (e.g., Figure 2 (ECU 210 and / or radar array controller 214 in the embodiment). In some embodiments, processor 426 and low-noise amplifier 418 can be coupled for bidirectional communication.

[0063] Additionally, in some embodiments, the carrier signal generator 412 may be coupled to the radar array controller 214. Figure 2 The carrier signal generator 412 may include a chirp generator to form an FMCW signal. The chip rate of the carrier signal generator 412 may be determined by the radar array controller 214. Figure 2 In some embodiments, the carrier signal generator 412 can be controlled by the radar array controller 214. Figure 2 The carrier signal generator 412 can be deactivated to provide an unmodulated carrier signal. Furthermore, the carrier signal generator 412 can be implemented as a local oscillator (LO) signal generator, a fractional N phase-locked loop (PLL) with a ΣΔ controller, or a direct digital synthesis generator.

[0064] Furthermore, the carrier signal generator 412 can be coupled to the transmit antenna 312 via the phase shifter 414 and the amplifier 416. The carrier signal generator 412 can also be coupled to the receive antenna 312 via the mixer 420 and the low-noise amplifier 418. Additionally, the carrier signal generator 412 can generate a transmit signal (e.g., a chirped signal). The amplifier 416 can receive the transmit signal from the carrier signal generator 412 and can use the transmit antenna 312 to transmit a transmit signal 316 corresponding to the transmit signal from the carrier signal generator 412.

[0065] In some embodiments, the radar transmitter may include: a phase rotator, a biphase modulator, a variable gain amplifier, a switch, a power amplifier driver, a power amplifier, and / or a digital signal processor (DSP). Furthermore, in some embodiments, the radar transmitter may include a digital controller. This digital controller may be included within the DSP or may be a separate component. Additionally, the phase rotator may be used for digital phase modulation. Furthermore, the radar transmitter may utilize a wave-modulated power amplifier in a digital envelope modulation technique.

[0066] Figure 5 A block diagram illustrating an example of a radar transceiver chip 502, or "RF front-end" chip, used in a MIMO radar system is presented. Transceiver chip 502 may include a chirp generator 404 that converts the LO signal into an FMCW signal, such as a signal with a linearly swept chirp sequence. Furthermore, a power divider 506 can divide a portion of the FMCW signal power to supply a copy of the FMCW signal to a down-conversion mixer 507. Additionally, the remainder of the FMCW signal may be passed to a set of phase shifters 508, which a controller 509 can use to independently phase-shift the FMCW signal for each individual element in the RF output.

[0067] In some embodiments, phase shifting can be used in various ways to enable virtual beam steering, such as coherent beam steering or channel separation. Channel separation can be provided using orthogonal coded phase modulation with different code modes for each channel. Alternatively or additionally, phase shifting can provide channel separation by using different frequency shifts, different sweep rates, and / or spreading codes (e.g., Barker codes, maximum length sequence codes, etc.). Phase modulation can be 1-bit (e.g., bipolar phase shift keying), 2-bit (e.g., quadrature phase shift keying), or higher order (N-bit). Power amplifier 510 can receive the phase-shifted FMCW signal and drive three transmit signals (Tx0 to Tx2) on the output contacts. Although the radar transceiver chip is illustrated as having three transmit signals, in other embodiments, more or fewer transmit signals may be present. The transmit signals can be provided to transmit antennas, or, as discussed further below, can be provided to a transmit-side extender chip to increase the number of transmit antennas driven from transceiver chip 502.

[0068] Transceiver chip 502 may include contacts for obtaining four received signals (Rx0 to Rx3) from a receiving antenna or, as discussed further below, from a receiver-side extender chip (to increase the number of receiving antennas supported by transceiver chip 502). Down-conversion mixer 507 can multiply the received signal with a copy of the FMCW signal, thereby converting the received signal to a near-baseband frequency after passing through low-pass filter 512. Furthermore, gain control amplifier 514 can adaptively adjust the signal amplitude to optimize the use of the dynamic range of ADC 516. Additionally, ADC 516 can digitize the received signal for processing by controller 509. Controller 509 may be a programmable digital signal processor with fast memory (e.g., SRAM) and a serial peripheral interface (SPI), thereby enabling it to communicate with other chips in the MIMO radar system.

[0069] At signal frequencies used in automotive radar (e.g., 80 GHz), it may be preferable to keep the antenna feed line short to minimize attenuation and electromagnetic interference. However, once the antenna array size exceeds approximately seven or eight antennas, the relationship between the physical size of the transceiver chip and the pitch of the antenna array can make it difficult to keep the antenna feed line acceptablely short. When using additional chips (such as extender chips) that each support a small number of antennas (e.g., three or four), the extender chips can be positioned near the corresponding antennas to minimize feed line length, and inter-chip communication can be at least partially protected by using amplifiers and additional shielding.

[0070] Figure 6A block diagram illustrating an example radar system with extender chips is presented. The extender chips can increase the number of transmitter and receiver antennas supported by a given transceiver chip 502. Note that each of the four receive signal contacts can be coupled to a given receive-side extender chip 602A to 602D. Each of the receive-side extender chips can receive input signals from a corresponding set of receive antennas 604A to 604D, can provide them with adjustable phase shifts, and can combine the phase-shifted signals to provide a received signal to transceiver chip 502. Figure 6 In this embodiment, each of the receiver-side extender chips can combine four input signals to form a received signal. However, in other embodiments, the number of input signals can be larger or smaller.

[0071] Furthermore, each of the three transmit signal contacts of transceiver chip 502 can be coupled to a given transmit-side extender chip 606A to 606C. Each of the transmit-side extender chips can convert the transmit signal into multiple output signals for a corresponding set of transmit antennas 608A to 608C, and each output signal can be phase-shifted or frequency-shifted by a desired amount and / or modulated with a desired channel code using a controllable phase shifter. Figure 6 In this embodiment, each of the transmitter-side extender chips can convert the transmitted signal into three output signals. However, in other embodiments, the number of output signals can be larger or smaller.

[0072] Transceiver chip 502 can be coupled to each of the expander chips via digital control signal lines 610, which may include an SPI bus. Signal lines 610 enable transceiver chip 502 to program the expander chips with desired phase shifts and / or channel codes, and enable transceiver chip 502 to control the timing of any transitions in the phase shift.

[0073] Although Figure 6 Although not shown, extender chips can be used in a hierarchical manner. For example, instead of coupling the inputs of receiver-side extender chip 602A to antenna 604A, each of these inputs can be coupled to an additional, given receiver-side extender chip to increase the number of antennas multiplexed onto the Rx0 channel of transceiver chip 502 from four to sixteen. This process can be repeated for each of receiver-side extender chips 602B to 602D, thereby increasing the total number of receive antennas from 16 to 64. Note that transmit-side extender chips 606A to 606C can similarly be coupled to second-stage transmit-side extender chips, thereby increasing the number of supported transmit antennas from 9 to 27. Additional hierarchies can be added until limited by, for example, the processing capabilities of transceiver chip 502.

[0074] Figure 7 A block diagram illustrating an example of an input or receive-side extender chip 602 is presented. This receive-side extender chip may have three input contacts (RF_IN1 to RF_IN3) for receiving antenna signals. Each input signal may be coupled to one of a plurality of controllable phase shifters 702, and a power combiner 704 may sum the phase shifter outputs to provide a composite received signal to a low-noise amplifier 706. The LNA 706 may drive the composite received signal to a downstream chip such as a transceiver 502 via an output contact RF_OUT. Note that the receive-side extender chip 602 may include an on-chip controller 710 (or control circuitry) for controlling the phase shifters 702 using a given sequence of adjustable phase shifts from on-chip memory 708. While the timing of the phase shift adjustment can vary, some embodiments may apply a fixed phase shift to each chirp, switching to the next phase shift for the next chirp. This approach avoids bandwidth expansion of the composite received signal but may require multi-chirp measurements to separate the contributions of various antennas, which could potentially affect the time or velocity resolution of the measurements. Alternatively or additionally, phase shift adjustments can be performed multiple times during each chirp to provide different frequency shifts, different sweep rates, and / or coded modulation to extend the input signal energy across a larger spectrum. While transceiver chip 502 may need to increase the digitization rate, multi-line chirp measurements can be avoided. In some embodiments, the timing of phase shift adjustments can be coordinated by transceiver chip 502 for the extender chip via SPI bus 712 or via another shared clock signal line.

[0075] In some embodiments, the automotive electronics may preferably include a circuitry for verifying correct operation. Therefore, the receiver-side extender chip 602 may include an optional power supply voltage monitor 714 for detecting undervoltage and overvoltage, and may include an optional test input (RF_INJECT) via which a test signal can be coupled to the antenna input contacts. When a test signal is applied, the transceiver chip 502 can verify that the test signal can be detected from each of the antenna inputs.

[0076] Figure 8A block diagram illustrating an example of a transmit-side extender chip 606 is presented. This transmit-side extender chip may have an input contact that accepts a transmit signal (RF_IN). A power divider may divide the transmit signal into multiple copies, thereby supplying one copy to each of a plurality of controllable phase shifters 804. The output of each phase shifter 804 may be coupled to a given transmit signal contact via a corresponding power amplifier 806. Note that the transmit signal contact may be adapted to connect to a transmit antenna. The transmit-side extender chip 606 may include an on-chip controller 810 (or control circuitry) that controls the phase shifters 804 using a given sequence of phase shift adjustments from on-chip memory 808. Similar to the receive-side extender, in some embodiments, the timing of the phase shift adjustments may be coordinated by the transceiver chip 502 via SPI bus 812 or another shared clock signal line. Furthermore, to avoid bandwidth expansion, the transmit-side code symbol (phase shift) for each chirp may remain fixed, for example, switching only between chirs. Alternatively or additionally, phase shifters can be used to provide output signals with different frequency shifts, different sweep rates, and / or different spreading codes.

[0077] Similar to the receiver-side extender, the transmitter-side extender may include circuitry for verifying correct operation. For example, an optional power supply voltage monitor 814 may detect undervoltage or overvoltage that could potentially affect component operation. Additionally, an optional phase difference detector 816 may be included to compare the phases of adjacent phase shifters 804, and an optional power detector 818 may be included to monitor the output of the power amplifier 806 for correct operation. As described in co-owned patent application US 16 / 660,370, filed October 22, 2019, entitled “Radar Array Phase Shifter Verification”, by inventors Tom Heller et al., the operation of the phase shifter can be periodically verified by incrementally traversing each possible combination of phase shifter settings and verifying that the phase difference detector 816 measures the expected phase difference. Note that the extender chip may notify the transceiver chip 602 of detected faults via the SPI bus.

[0078] Figure 9A and Figure 9B A block diagram is presented illustrating an example of a data cube representing both the acquired set of radar measurements and the transformed set of radar measurements. Note that... Figure 9AThe diagram illustrates a data cube representing a portion of the digital signal measurements that can be collected by transceiver chip 502. Typically, each chirp can be considered a measurement period. However, when using code multiplexing, the measurement period can be extended to multiple chirs. During the measurement period, the RF receiver front end can digitize and isolate the down-converted received signal from the selected receiving antenna, thereby providing a time series of digitized received signal samples. Due to chirp modulation, the signal energy reflected by the target can arrive at the receiving antenna with a frequency offset depending on the round-trip time (and therefore the distance to the target). The Fast Fourier Transform (FFT) of the time series collected in a given period can isolate the energy associated with each frequency offset, thereby producing a function of the reflected energy as a function of the target distance. This operation, sometimes referred to as the "range FFT," can be performed for each transmit-receive antenna pair in each measurement period. The range FFT can produce a peak value for each target at a given distance.

[0079] Note that the motion of the target relative to the antenna array adds a Doppler shift to the reflected signal energy. This Doppler shift can be proportional to the relative velocity. While the Doppler shift is typically small relative to the frequency offset caused by range, it can be observed as a phase change in the associated frequency coefficients in subsequent measurement cycles. (Recall that FFT coefficients are complex values ​​with both amplitude and phase.) Applying the FFT to the corresponding frequency coefficients in the measurement cycle sequence isolates the energy associated with each relative velocity, thus producing a function of the reflected energy as a function of the target velocity. This operation, sometimes called "rate FFT," can be performed for each range and each transmit-receive antenna pair. The resulting two-dimensional data array can include "peaks" for each target at a given range and relative velocity.

[0080] Furthermore, reflected energy from a given target can reach individual receiving antennas in the antenna array, with its phase depending on the direction of arrival of the reflected energy (sometimes referred to as the "approach angle"). Applying an FFT to the corresponding frequency coefficients associated with a uniformly spaced sequence of antennas isolates the energy associated with each angle of incidence, thereby producing a function of reflected energy versus the approach angle (AoA). This operation, sometimes called "AoA FFT," can be performed for each distance and velocity using a given transmitting antenna.

[0081] Therefore, the digitized signal measurement results arranged in the measurement data cube can be transformed into the target data cube, where the three dimensions of the measurement data cube represent functions of time, measurement period, and antenna position (e.g., ...). Figure 9A As shown in the figure, the three dimensions of the target data cube represent functions of distance, velocity, and AoA (as shown in the figure). Figure 8(As shown in B). Because these operations (channel separation, range FFT, velocity FFT, and AoA FFT) are linear, they can be performed in any order. Furthermore, the FFT operations are independent (meaning, for example, the range FFT for a given antenna and period can be independent of the range FFT for other antennas and other periods, and the velocity FFT for a given distance and antenna can be independent of the velocity FFT for other distances and antennas), thus allowing FFT processing to be performed in parallel (if desired).

[0082] Another desired processing operation is the separation of signal energy from noise energy. A wide variety of suitable noise suppression or target detection techniques can be used. One technique (which includes many variations) is constant false alarm rate (CFAR) detection. CFAR detection can be adapted to a detection threshold based at least in part on the measured energy values ​​within a sliding window near or around the measurement being evaluated (sometimes referred to as the "test cell"). CFAR techniques and their variations offer various trade-offs between performance and computational complexity by deriving the detection threshold from the measurements within the sliding window using different statistical methods. Note that CFAR detection is a non-linear technique because measurements below the threshold can be zeroed out or ignored, but their position in the processing sequence can be modified, since zeroing out the frequency coefficient generally does not prevent subsequent FFTs from utilizing the relevant phase / frequency information representing the energy peaks of the target.

[0083] Figure 10 A flowchart of an example data stream 1000 in a radar system is presented, which can be executed by transceiver chip 502 or can be split between transceiver chip 502 and ECU 210. Note that the digitized received signal x is obtained... k In this case, controller 509 may optionally use phase shift adjustment applied in transceiver chip 502, any transmit-side extender, and / or any receive-side extender to demultiplex the receive antenna signal and isolate contributions from each transmit antenna, thereby separating the channel corresponding to each transmit-receive antenna pair. (If the phase shift is being used for beam steering, this channel separation may not be necessary.) Furthermore, controller 509 may, for example, perform a range FFT 1002 for each channel upon signal acquisition, thereby storing the resulting frequency coefficients as range data in frame buffer 1004. Frame buffer 1004 may accumulate range data from multiple measurement periods, thereby enabling controller 509 to then perform a velocity FFT 1006 to generate target range and velocity data for each channel, as previously discussed.

[0084] The CFAR detector 1008 can manipulate target distance and velocity data to remove noise energy below an adaptive threshold. Furthermore, the CFAR detector 1008 can zero out values ​​below the threshold, leaving only values ​​above the threshold representing the distance and velocity of the potential target (radar energy reflector). In some embodiments, the CFAR detection process can compress the data volume by omitting at least some of the values ​​below the threshold and / or by employing more sophisticated data compression techniques to reduce buffer size requirements and / or bus bandwidth requirements. Additionally, the controller 509 and / or ECU 210 can perform an AoA FFT 1010 to determine the relative orientation associated with the potential target and can analyze any peaks in the data volume to detect and track 1012 the target's relative position and velocity relative to the vehicle.

[0085] Figure 11 A flowchart illustrating an example of a method 1100 for radar detection according to some embodiments of the present disclosure is presented, which can be performed by a MIMO radar system with an extender. Note that the chirp generator 504 can generate a chirp signal (operation 1102) having a frequency range that linearly increases from a start frequency to an end frequency. The chirp signal can be an up-chirp, a down-chirp, or even a triangular up-then-down chirp signal. Furthermore, the chirp signal can be divided into multiple transmit signals. The transceiver chip 502 can then optionally apply an adjustable phase shift (operation 1104) to the different transmit signals, for example, to provide phase shift, beamforming, orthogonal code modulation, and / or frequency shift. Additionally, the MIMO system can use a transmit-side extender chip to divide each transmit signal (operation 1106) into multiple output signals, which can be further phase-shifted using different phase-shift-adjusted sequences before being supplied to the transmit antenna.

[0086] Next, the input signal from the receiving antenna can optionally be phase-shifted (operation 1108) to provide phase shift, beam steering, quadrature coding, and / or frequency shift, and the phase-shifted signals can be combined to form a received signal for digitization. Furthermore, controller 509 can optionally use a phase-shift sequence to separate the signals from each transmit-receive antenna pair (operation 1110). Additionally, controller 509 and / or ECU 210 can transform the signal (operation 1112) to extract an energy peak indicating the target, which can then be used to detect and track the target relative to the vehicle (operation 1114). ECU 210 can assess whether the target requires actions such as warning the driver or automatic braking and steering to avoid a collision (operation 1116), and can act accordingly if necessary.

[0087] In some embodiments of method 1100, there may be additional or fewer operations. Furthermore, the order of operations may be changed, and / or two or more operations may be combined into a single operation. Although the operations in method 1100 have been described sequentially for illustrative purposes, at least some of these operations may be implemented simultaneously or in a pipelined manner. Alternatively, at least some of these operations may be performed asynchronously.

[0088] Note that using a receive-side expander to combine input signals from multiple receive antennas enables the transceiver to support additional receive antennas. Furthermore, using a transmit-side expander to reverse-segment the transmit signal enables the transceiver to support additional transmit antennas. Additionally, a phase modulator allows the transceiver to distinguish the contributions of each transmit and receive antenna. In some embodiments, the phase modulator can be implemented as a bipolar phase-shift keying (BPSK) modulator, a quadrature phase-shift keying (QPSK) modulator, and / or a higher-order phase-shift keying modulator.

[0089] As previously discussed, MIMO radar employs multiple transmit and receive radio channels to enhance functionality. For example, increasing the number of channels can increase radar range and angular resolution. However, radar RF front-end chips typically have limited capacity to host channels on a single die due to trade-offs such as RF interconnect losses (towards the antenna) and die area limitations, complexity, and cost. These issues can be addressed by connecting multiple chips in a cascaded configuration (e.g., star topology), which often requires synchronization of signals such as LO, clock, and control signals.

[0090] Figure 12 A block diagram illustrating an example of a cascaded chip is presented. Specifically, a single radar chip (or transceiver chip) with four receivers and three transmitters is used as the master chip, which is cascaded with two slave radar chips to have 12 receivers and 9 transmitters. Note that... Figure 12 The master chip and slave chip in the system are the same. Furthermore, Figure 12 The master and slave chips in the process are synchronized and coordinated, which increases overhead and adds redundant or unnecessary components.

[0091] In contrast, in the disclosed circuit technology, extender chips can be used to expand the number of transmit and receive channels available for a single radar chip. This is in Figure 13 The diagram shows a block diagram of an example of a radar chip (or transceiver chip) and an extender chip. Figure 13The configuration increases the number of antennas (such as patch antennas) on the receiving side and the number of physical channels on the transmitting side. Note that this configuration is equivalent to a radar chip with 16 receivers and 9 transmitters. Furthermore, instead of cascaded radar chips relying on LO synchronization (which can involve communication at tens of gigahertz on a printed circuit board), only digital control signals (which can involve communication at hundreds of megahertz on a printed circuit board) can be synchronized. Therefore, the extender in the disclosed circuit technology can be smaller, cheaper, and easier to integrate into a MIMO radar system.

[0092] In some embodiments, the loss on the RF trace from the chip to the antenna array (which is in Figures 12 to 13 (As may be unavoidable in the embodiments shown) can be compensated for by an amplifier operating in the extender chip. Furthermore, signal processing for separating the channels can be used for transmission using MIMO, and for reception using the previously described MIMO techniques. Additionally, phase coding can allow beam steering, simultaneous channel operation (such as simultaneous reception), and / or interference mitigation (as opposed to on / off switching that may require time-division multiplexing).

[0093] Note that an extender chip does not have to be a complete replica of a radar chip. Instead, an extender chip can be simpler than a radar chip. For example, a given extender can have a smaller area, can include fewer components, and can use fewer control signals. Furthermore, an extender chip can increase the number of channels carrying “independent” information (which, in contrast to increasing the number of antennas per channel, may only provide an increase in channel gain).

[0094] Although Figure 13 The illustration shows an expander chip including a multiplexer, but in other embodiments, at least a demultiplexer from the transmit expander chip may be included on the radar chip. However, in some embodiments, a multiplexer from the receive expander chip may be included on the radar chip. Furthermore, although... Figure 13 The illustration shows separate transmit extender and receive extender chips, but in some embodiments, the transmit extender and receive extender chips may be included in a single extender chip. Therefore, in some embodiments, instead of... Figure 13 The seven chips shown can include fewer combined transmit / receive extender chips. Note that demultiplexing in the transmit extender chip and / or multiplexing in the receive extender chip can be performed coherently. Furthermore, note that the receive extender chip may not perform frequency shifting. Alternatively, frequency shifting or mixing can be performed by the radar chip.

[0095] In some embodiments, these circuit technologies provide a transmit channel extender chip (sometimes referred to as a "transmit extender chip"). Note that a transmit channel extender chip may include two signal domains: an RF path and a digital path. The RF path may include: a 1:N power divider, N phase shifters, and / or N power amplifiers. Furthermore, the digital path may include: an SPI data interface, SRAM for storing the phase profile, and / or a controller.

[0096] Refer back Figure 8 When the transmit channel extender chip is connected to the radar chip, RF_IN can be coupled to the power amplifier output of the radar chip (e.g., Tx0). Furthermore, each RF_OUT of the transmit channel extender chip can be coupled to an antenna element.

[0097] During operation of the transmit channel extender chip, at startup, the user can load the initial phase settings, power amplifier bias, and channel on / off states via the SPI data interface. Additionally, a phase distribution table can be loaded into SRAM. Then, during radar operation, on each chirp, the transmit channel extender chip can point to the subsequent row in the lookup table, and each extender channel can receive different phase settings for the purpose of separating each transmitted signal. Note that the power amplifier gain can be selected to compensate for RF trace losses on the printed circuit board including the radar chip and one or more transmit channel extender chips, as well as losses associated with the one or more transmit channel extender chips. Figure 14 A block diagram illustrating an example of a radar chip and a transmit channel extender chip is presented.

[0098] In some embodiments, these circuit techniques provide a receive channel extender chip (sometimes referred to as a "receive extender chip"). Note that the receive channel extender chip may include two signal domains: an RF path and a digital path. The RF path may include: N phase shifters, a 1:N power combiner, and / or a low-noise amplifier. Furthermore, the digital path may include: an SPI data interface, SRAM for storing the phase distribution, and / or a controller.

[0099] Refer back Figure 7 When the receive channel extender chip is connected to the radar chip, each RF_in can be coupled to an antenna element. Furthermore, the RF_OUT of the receive channel extender chip can be coupled to the RF input of the radar chip.

[0100] During operation of the receive channel extender chip, at startup, the user can load the initial phase settings, low-noise amplifier bias, and channel on / off states via the SPI data interface. Additionally, a phase distribution table can be loaded into SRAM. Then, during radar operation, on each chirp, the receive channel extender chip can point to the subsequent row in the lookup table, and each extender channel can receive different phase settings for the purpose of separating each received signal. Note that the low-noise amplifier gain can be selected to compensate for RF trace losses on the printed circuit board including the radar chip and one or more receive channel extender chips, as well as losses associated with the one or more receive channel extender chips. Figure 15 A block diagram illustrating an example of a radar chip and a receive channel extender chip is presented.

[0101] In addition, such as Figure 7 As shown, note that the combination of received signals in the receiver extender chip can occur after the analog phase shift. However, in some embodiments, this can be implemented in a digital signal processor after analog-to-digital conversion in the radar chip. In these embodiments, different phase codes can be used in the receiver extender chip (e.g., to allow received signals for different channels to be separated). This coding can occur after input to the receiver extender but before analog-to-digital conversion.

[0102] As previously described, when used in automotive applications, safety components can be included in the extender chip. For example, such as Figure 8 As shown, a given transmit channel extender chip may include: N power detectors (PDs) 818 at the output of a power amplifier, and / or N-1 phase detectors (ΦDs) 816 between adjacent power amplifiers. Furthermore, as... Figure 7 As shown, a given receive channel extender chip may include an RF injection port and N couplers at the input port. In some embodiments, a given receive channel extender chip may include a voltage monitor 714 for power supply, and / or a given transmit channel extender chip may include a voltage monitor 814 for power supply.

[0103] In some embodiments, the transmit channel extender chip and / or the receive channel extender chip may include fewer or additional components, the positions of one or more components may be changed, two or more components may be combined into a single component, and / or a single component may be divided into two or more components.

[0104] The disclosed circuitry techniques can increase the size scalability of RF radar chips at low cost. Furthermore, these circuitry techniques can improve performance. For example, positioning the gain stage close to the antenna can compensate for losses in the printed circuit board traces, which can increase the signal-to-noise ratio. Additionally, in some embodiments, extender chips can be used in a cascaded configuration, thereby further increasing channel spread. Note that, for cost-effectiveness, receive channel extender chips and / or transmit channel extender chips can be implemented in CMOS technology. In some embodiments, the extender chips can be compatible with existing radar chips, which include radar chips from multiple different vendors or manufacturers.

[0105] The disclosed integrated circuits and circuit technologies can be (or may be included in) any electronic device or system. For example, electronic devices may include: cellular phones or smartphones, tablet computers, laptop computers, notebook computers, personal or desktop computers, netbook computers, media player devices, e-book devices, MiFi® devices, smartwatches, wearable computing devices, portable computing devices, consumer electronics devices, access points, routers, switches, communication equipment, test equipment, vehicles, ships, aircraft, automobiles, trucks, buses, motorcycles, manufacturing equipment, farm equipment, construction equipment, or another type of electronic device.

[0106] Although specific components are used to describe embodiments of an integrated circuit and / or an integrated circuit including the integrated circuit, in alternative embodiments, different components and / or subsystems may exist in the integrated circuit and / or the integrated circuit including the integrated circuit. Therefore, embodiments of the integrated circuit and / or the integrated circuit including the integrated circuit may include fewer components, additional components, different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more locations of one or more components may be changed, and / or different types of components may exist.

[0107] Furthermore, the circuits and components in embodiments of the integrated circuit and / or the integrated circuit including the integrated circuit can be implemented using any combination of analog and / or digital circuit systems including bipolar, PMOS, and / or NMOS gates or transistors. Additionally, the signals in these embodiments can include digital signals with approximately discrete values ​​and / or analog signals with continuous values. Furthermore, these components and circuits can be single-ended or differential, and the power supply can be unipolar or bipolar. Note that the electrical coupling or connection in the foregoing embodiments can be direct or indirect. In the foregoing embodiments, a single line corresponding to a trace can indicate one or more single lines or traces.

[0108] As previously stated, at least an integrated circuit can implement some or all of the functions of the circuit technology. The integrated circuit may include hardware and / or software mechanisms for implementing the functions associated with the circuit technology. However, in other embodiments, the disclosed circuit technology may be implemented at least partially using discrete components.

[0109] In some embodiments, the output of a process for designing an integrated circuit or a portion thereof that includes one or more of the circuits described herein may be a computer-readable medium such as, for example, magnetic tape, optical disc, or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing a circuit system that can be physically instantiated as an integrated circuit or a portion thereof. Although such encoding may be performed in various formats, these data structures are generally written in the following formats: Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Exchange Format (EDIF), Open Access (OA), or Open Artwork System Interchange Standard (OASIS). Those skilled in the art of integrated circuit design can develop such data structures from schematic diagrams and corresponding descriptions of the types detailed above and encode the data structures on a computer-readable medium. Those skilled in the art of integrated circuit manufacturing can use such encoded data to manufacture integrated circuits that include one or more of the circuits described herein.

[0110] While some operations in the foregoing embodiments are implemented in hardware or software, they can generally be implemented in a wide variety of configurations and architectures. Therefore, some or all of the operations in the foregoing embodiments can be performed in hardware, software, or both. For example, at least some operations in circuit technology can be implemented using program instructions executed by a processor or in firmware within an integrated circuit.

[0111] Furthermore, while examples of numerical values ​​have been provided in the foregoing discussion, different numerical values ​​are used in other embodiments. Therefore, the numerical values ​​provided are not intended to be limiting.

[0112] In the foregoing description, "some embodiments" refers to a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0113] The foregoing description is intended to enable any person skilled in the art to make and use this disclosure, and is provided in the context of a particular application and its requirements. Furthermore, the foregoing description of embodiments of this disclosure has been provided for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit this disclosure to the forms disclosed. Therefore, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. Additionally, the discussion of the foregoing embodiments is not intended to limit this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown, but is to be given the broadest scope consistent with the principles and features disclosed herein.

Claims

1. A first integrated circuit, comprising: Receiver extender; and Transmitter extender, wherein the receiver extender includes: N receiving contacts are configured to be coupled to N receiving antennas and configured to receive N received signals associated with the N receiving antennas, where N is a non-zero integer; N phase adjustment circuits, coupled to the N receiving contacts, are configured to adjust the phase of the N received signals; An N:1 multiplexer, coupled to the N phase adjustment circuits, is configured to combine the N received signals into an output signal; and The output contact, coupled to the N:1 multiplexer, is configured to provide the output signal to the second integrated circuit; and The emitter extender includes: An input contact is configured to receive a transmit signal associated with the second integrated circuit, wherein the second integrated circuit is configured to perform a phase shift of the output signal, the transmit signal, or both based at least in part on an oscillator signal; 1:M demultiplexer, coupled to the input contact, is configured to separate the transmitted signal into M transmitted signals, where M is a non-zero integer; M phase adjustment circuits, coupled to the 1:M demultiplexer, are configured to adjust the phases of the M transmitted signals; and M transmitting contacts, coupled to the M phase adjustment circuits, are configured to couple to the M transmitting antennas and provide the M transmitting signals to the M transmitting antennas, wherein the control signals for the N phase adjustment circuits, the M phase adjustment circuits, or both are synchronized between the first integrated circuit and the second integrated circuit, and the oscillator signals are desynchronized between the first integrated circuit and the second integrated circuit.

2. The first integrated circuit of claim 1, wherein, The N:1 multiplexer is configured to coherently combine the N received signals.

3. The first integrated circuit of claim 1, wherein, The 1:M demultiplexer is configured to coherently separate the M transmitted signals.

4. The first integrated circuit according to claim 1, wherein, N is different from M.

5. The first integrated circuit according to claim 1, wherein, The N phase adjustment circuits are configured to apply different phase adjustments to the N received signals.

6. The first integrated circuit according to claim 1, wherein, The M phase adjustment circuits are configured to apply different phase adjustments to the M transmitted signals.

7. The first integrated circuit according to claim 1, wherein, The configurations of the first integrated circuit and the second integrated circuit differ from those of a cascaded configuration.

8. The first integrated circuit according to claim 1, wherein, The first integrated circuit is different from the second integrated circuit.

9. The first integrated circuit according to claim 1, wherein, The second integrated circuit includes a transceiver chip.

10. A system comprising: The first integrated circuit includes: Receive extender; and Transmitter extender, wherein the receiver extender includes: N receiving contacts are configured to be coupled to N receiving antennas and configured to receive N received signals associated with the N receiving antennas, where N is a non-zero integer; N phase adjustment circuits, coupled to the N receiving contacts, are configured to adjust the phase of the N received signals; An N:1 multiplexer, coupled to the N phase adjustment circuits, is configured to combine the N received signals into an output signal; and The output contact, coupled to the N:1 multiplexer, is configured to provide the output signal to the second integrated circuit; and The emitter extender includes: The input contact is configured to receive a transmit signal associated with the second integrated circuit; 1:M demultiplexer, coupled to the input contact, is configured to separate the transmitted signal into M transmitted signals, where M is a non-zero integer; M phase adjustment circuits, coupled to the 1:M demultiplexer, are configured to adjust the phases of the M transmitted signals; and M transmitting contacts, coupled to the M phase adjustment circuits, are configured to couple to the M transmitting antennas and provide the M transmitting signals to the M transmitting antennas; and The second integrated circuit is coupled to the first integrated circuit, wherein the second integrated circuit is configured to perform a phase shift of the output signal, the transmitted signal, or both, at least in part based on an oscillator signal; and The control signals for the N phase adjustment circuits, the M phase adjustment circuits, or both are synchronized between the first integrated circuit and the second integrated circuit, while the oscillator signals are not synchronized between the first integrated circuit and the second integrated circuit.

11. The system according to claim 10, wherein, The N:1 multiplexer is configured to coherently combine the N received signals.

12. The system according to claim 10, wherein, The 1:M demultiplexer is configured to coherently separate the M transmitted signals.

13. The system according to claim 10, wherein, N is different from M.

14. The system according to claim 10, wherein, The N phase adjustment circuits are configured to apply different phase adjustments to the N received signals.

15. The system according to claim 10, wherein, The M phase adjustment circuits are configured to apply different phase adjustments to the M transmitted signals.

16. The system according to claim 10, wherein, The configurations of the first integrated circuit and the second integrated circuit differ from those of a cascaded configuration.

17. The system according to claim 10, wherein, The first integrated circuit is different from the second integrated circuit.

18. The system according to claim 10, wherein, The second integrated circuit includes a transceiver chip.

19. A method for extending a second integrated circuit, comprising: The receiver extender in the first integrated circuit: Receive N signals from N receiving antennas, where N is a non-zero integer; N phase adjustment circuits are used to adjust the phase of the N received signals; The N received signals are combined into an output signal using an N:1 multiplexer. and The output signal is provided to the second integrated circuit; or The emitter extender in the first integrated circuit: Receive a transmit signal associated with the second integrated circuit, wherein the second integrated circuit performs a phase shift of the output signal, the transmit signal, or both based at least in part on an oscillator signal; The transmitted signal is separated into M transmitted signals using a 1:M demultiplexer, where M is a non-zero integer; M phase adjustment circuits are used to adjust the phase of the M transmitted signals; and The M transmitted signals are provided to the M transmitted antennas; Between the first integrated circuit and the second integrated circuit, control signals for the N phase adjustment circuits, the M phase adjustment circuits, or both are synchronized, and The oscillator signals are not synchronized between the first integrated circuit and the second integrated circuit.

20. The method according to claim 19, wherein, The combination of the N received signals or the separation of the M transmitted signals are performed coherently.

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