Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device (1) has: an electron traveling layer (103); an electron supply layer (104) provided on the electron traveling layer (103); a gate electrode (303) provided on the electron supply layer (104); a contact layer (212) buried in a through-hole recess (211) that penetrates the electron supply layer (104) at a position apart from the gate electrode (303); an electron supply auxiliary layer (401) provided in contact with the electron supply layer (104) and in contact with the contact layer (212) and not in contact with the gate electrode (303), which is an example of an n-type semiconductor layer composed of an n-type semiconductor containing Si; a first insulating layer (201) provided on the electron supply auxiliary layer (401) and provided in contact with an alloy layer (402) containing Si and the gate electrode (303) and not in contact with the contact layer (212); and a source electrode (301) and / or a drain electrode (302) provided on the contact layer (212) and on the alloy layer (402).

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same, and particularly to group III nitride semiconductor devices using group III nitride semiconductors and methods for manufacturing the same. Background Technology

[0002] Group III nitride semiconductor devices, particularly gallium nitride (GaN) or aluminum gallium nitride (AlGaN), exhibit high insulation breakdown voltages due to the wide band gap of the materials. Furthermore, heterostructures such as AlGaN / GaN can be readily formed in group III nitride semiconductor devices.

[0003] In AlGaN / GaN heterostructures, due to the difference in piezoelectric polarization caused by the lattice constant difference between the materials and the difference in spontaneous polarization between AlGaN and GaN, a high concentration of electrons (two-dimensional electron gas) is generated on the GaN layer side at the interface between the AlGaN and GaN layers, forming a channel of the two-dimensional electron gas layer. Group III nitride semiconductor devices utilizing this two-dimensional electron gas-based channel are used in high-frequency power devices and other applications due to their high electron saturation velocity, high insulation resistance, and high thermal conductivity.

[0004] In these group III nitride semiconductor devices, in order to improve characteristics, it is preferable to minimize parasitic resistance components such as the contact between the ohmic electrode and the two-dimensional electron gas layer (hereinafter referred to as "ohmic contact") and the resistance of the channel based on the two-dimensional electron gas within the group III nitride semiconductor device.

[0005] Previously, techniques for reducing ohmic contact resistance have been proposed in group III nitride semiconductor devices that utilize channels based on two-dimensional electron gas. For example, Patent Document 1 discloses a technique in which, in order to reduce ohmic contact resistance, an ohmic electrode is formed by forming a recess (hereinafter referred to as a "through recess") that penetrates an electron supply layer made of AlGaN in the portion of the group III nitride semiconductor device in which the ohmic electrode is formed.

[0006] Existing technical documents Patent documents Patent Document 1: International Publication No. 2021 / 246227 Summary of the Invention

[0007] The problem that the invention aims to solve However, if a through-recess is formed in the electron supply layer as disclosed in Patent Document 1, it is inevitable that the two-dimensional electron gas layer and the contact layer embedded in the through-recess will essentially become point-connected. Furthermore, if a through-recess is formed in the electron supply layer, not only will crystal defects be generated at the interface between the GaN-based two-dimensional electron gas layer (channel layer) and the contact layer during the formation of the through-recess, but also, due to atmospheric pollutants and bonding defects, a region with reduced carrier (electron) concentration will be created on the side adjacent to the through-recess in the electron supply layer, resulting in a decrease in the maximum drain current.

[0008] This disclosure was made in view of such a problem, with the aim of providing a semiconductor device and a method thereof capable of suppressing the reduction of maximum drain current.

[0009] Methods for solving problems To achieve the above objectives, one embodiment of the semiconductor device disclosed herein includes: an electron travel layer; an electron supply layer disposed on the electron travel layer, having a band gap larger than that of the electron travel layer; a gate electrode disposed on the electron supply layer; a source-side contact layer and a drain-side contact layer, embedded in a recess that penetrates the electron supply layer at a position separated from the gate electrode; an n-type semiconductor layer composed of an n-type semiconductor containing Si, connected to the electron supply layer, and connected to the source-side contact layer and / or the drain-side contact layer but not connected to the gate electrode; an alloy layer disposed on the n-type semiconductor layer, containing Si, and having a thickness of 2 nm or less; an insulating layer disposed on the portion of the electron supply layer where the gate electrode is not disposed, connected to the gate electrode but not connected to the source-side contact layer and / or the drain-side contact layer; and a source electrode and / or a drain electrode disposed on the source-side contact layer and / or the drain-side contact layer and on the alloy layer. Additionally, one aspect of the first method for manufacturing a semiconductor device disclosed herein includes the following steps: forming an electron supply layer on an electron travel layer with a larger bandgap than the electron travel layer; forming a Si-containing insulating layer on the electron supply layer without exposure to the atmosphere; thinning a portion of the insulating layer to form a thin portion on the insulating layer; leaving a portion of the thin portion as an insulating layer residue and forming a through recess that extends through the thin portion of the insulating layer and the electron supply layer to the electron travel layer; embedding and forming a contact layer in the through recess; forming a source electrode and / or a drain electrode across the insulating layer residue and the contact layer; performing heat treatment to form an alloy layer and an electron supply auxiliary layer on the insulating layer residue and the electron supply layer; and removing portions of the insulating layer that are separated from the source electrode and / or the drain electrode to form a gate electrode.

[0010] Additionally, one aspect of the second manufacturing method of the semiconductor device disclosed herein includes the following steps: forming an electron supply layer on an electron travel layer with a larger bandgap than the electron travel layer; forming an insulating layer containing Si on the electron supply layer without exposing it to the atmosphere; thinning a portion of the insulating layer to form a thin portion on the insulating layer; leaving a portion of the thin portion as an insulating layer residue and forming a through-hole recess that extends through the thin portion of the insulating layer and the electron supply layer to the electron travel layer; forming a source electrode and / or a drain electrode across the insulating layer residue and the through-hole recess; performing heat treatment to form an alloy layer and an electron supply auxiliary layer on the insulating layer residue and the electron supply layer; and removing portions of the insulating layer that are separated from the source electrode and / or the drain electrode to form a gate electrode.

[0011] Invention Effects According to this disclosure, a semiconductor device capable of suppressing the reduction of maximum drain current can be obtained. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1.

[0013] Figure 2 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device according to Embodiment 1.

[0014] Figure 3A This is a cross-sectional view showing the process of forming a semiconductor laminate structure, a first insulating layer, and a second insulating layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0015] Figure 3B This is a cross-sectional view showing the process of forming a thin portion of the first insulating layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 3C This is a cross-sectional view showing the process of forming a through recess in the manufacturing method of the semiconductor device according to Embodiment 1.

[0017] Figure 3D This is a cross-sectional view showing the process of forming a contact layer in the manufacturing method of the semiconductor device according to Embodiment 1.

[0018] Figure 3E This is a cross-sectional view showing the process of forming source and drain electrodes in the manufacturing method of the semiconductor device according to Embodiment 1.

[0019] Figure 3F This is a cross-sectional view showing the heat treatment process in the manufacturing method of the semiconductor device according to Embodiment 1.

[0020] Figure 3G This is a cross-sectional view showing the process of forming a gate electrode in the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 2.

[0022] Figure 5A This is a cross-sectional view showing the process of forming a semiconductor laminate structure, a first insulating layer, and a second insulating layer in the semiconductor device manufacturing method of Embodiment 2.

[0023] Figure 5B This is a cross-sectional view showing the process of forming a thin portion of the first insulating layer in the manufacturing method of the semiconductor device in Embodiment 2.

[0024] Figure 5C This is a cross-sectional view showing the process of forming a through recess in the manufacturing method of the semiconductor device according to Embodiment 2.

[0025] Figure 5D This is a cross-sectional view showing the process of forming the source electrode and the drain electrode in the manufacturing method of the semiconductor device in Embodiment 2.

[0026] Figure 5E This is a cross-sectional view showing the heat treatment process in the semiconductor device manufacturing method of Embodiment 2.

[0027] Figure 5F This is a cross-sectional view showing the process of forming a gate electrode in the manufacturing method of the semiconductor device according to Embodiment 2. Detailed Implementation

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown herein represent specific examples of the present disclosure. Therefore, the numerical values, shapes, constituent elements, arrangements and connections of constituent elements, and steps (processes) and their order shown in the following embodiments are examples and are not intended to limit the present disclosure. Therefore, any constituent elements in the following embodiments that are not described in the independent claims representing the highest-level concept of the present disclosure will be described as arbitrary constituent elements.

[0029] Furthermore, these figures are schematic diagrams and may not be strictly representational. Therefore, the scales and other parameters may not be consistent across different figures. In each figure, substantially identical structures are labeled with the same reference numerals, and repetitive descriptions are omitted or simplified.

[0030] Furthermore, in this specification, the terms "upper," "above," "lower," and "below" in the context of semiconductor device structure do not refer to "upper" (vertically above) and "lower" (vertically below) in absolute spatial identification, but rather to terms defined by relative positional relationships based on the stacking order in a stacked structure. Additionally, the terms "upper" and "lower" apply not only to cases where two constituent elements are arranged spaced apart from each other and other constituent elements exist between them, but also to cases where two constituent elements are arranged close together and connected.

[0031] Furthermore, in this specification and accompanying drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. In various embodiments, the two axes parallel to the upper surface of the substrate of the semiconductor device are designated as the x-axis and y-axis, and the direction orthogonal to the upper surface is designated as the z-axis direction. In the embodiments described below, the positive z-axis direction is sometimes referred to as "up" and the negative z-axis direction as "down." Additionally, in this specification, "top view" refers to the view of the substrate of the semiconductor device from the positive z-axis direction.

[0032] (Implementation Method 1) First, use Figure 1 The semiconductor device 1 of Embodiment 1 will be described. Figure 1 This is a cross-sectional view showing the structure of the semiconductor device 1 according to Embodiment 1.

[0033] In this embodiment, the case where the semiconductor device 1 is a high electron mobility transistor (HEMT) having a Schottky junction gate structure will be described.

[0034] like Figure 1As shown, the semiconductor device 1 includes a substrate 101, a buffer layer 102, an electron travel layer 103, an electron supply layer 104, a first insulating layer 201, a second insulating layer 202, a source electrode 301, a drain electrode 302, a gate electrode 303, an electron supply auxiliary layer 401, and an alloy layer 402. The substrate 101 is, for example, a silicon substrate made of Si. In this embodiment, the substrate 101 is, for example, a silicon substrate made of a single crystal of Si with a (111) plane as its main surface. In addition, the substrate 101 is not limited to a silicon substrate, and may also be a substrate made of sapphire, SiC, GaN, or AlN, which serves as the substrate for forming a nitride semiconductor layer. The resistivity of the substrate 101 is, for example, 1 kΩ or more. In addition, a substrate with a resistivity of 20 Ω or less may also be used as the substrate 101.

[0035] A buffer layer 102 is disposed on the substrate 101. The buffer layer 102 is, for example, a 2 μm thick group III nitride semiconductor layer composed of multiple stacked layers of AlN and AlGaN. In this case, 20 to 100 pairs of AlN and AlGaN can be stacked as one pair. Alternatively, the buffer layer 102 may also be composed of Al... 1-α Ga α The structure is composed of multiple N (0 ≤ α < 0.8) stacked layers, and includes a superlattice structure. Furthermore, the buffer layer 102 can also be composed of a single layer or multiple layers of group III nitride semiconductors such as InGaN or AlInGaN. Additionally, the carbon concentration of the buffer layer 102 can be set to 1 × 10⁻⁶. 19 atoms / cm 3 The buffer layer 102 is made highly resistive as described above. An electron travel layer 103 is disposed on top of the buffer layer 102. In this embodiment, the electron travel layer 103 is, for example, a GaN layer made of GaN with a thickness of 150 nm. Furthermore, the group III nitride semiconductor constituting the electron travel layer 103 is not limited to GaN. The electron travel layer 103 can be made of group III nitride semiconductors such as InGaN, AlGaN, and AlInGaN. In addition, the electron travel layer 103 may contain n-type impurities.

[0036] An electron supply layer 104 is disposed above the electron travel layer 103. The electron supply layer 104 has a larger band gap compared to the electron travel layer 103. In this embodiment, the electron supply layer 104 is, for example, an AlGaN layer with a thickness of 13 nm composed of AlGaN with an Al composition ratio of 30%. A high concentration of two-dimensional electron gas is generated on the electron travel layer 103 side of the heterojunction interface between the electron supply layer 104 and the electron travel layer 103, forming a channel for a two-dimensional electron gas layer 105. Therefore, the semiconductor device 1 has a two-dimensional electron gas layer 105. The two-dimensional electron gas layer 105 is composed of a first two-dimensional electron gas layer 105A and a second two-dimensional electron gas layer 105B with different electron concentrations, as detailed later.

[0037] Furthermore, the Al content in the electron supply layer 104, which is composed of AlGaN, is not limited to 30%. The Al content in the electron supply layer 104 can be 20% to 100%. Additionally, the group III nitride semiconductor constituting the electron supply layer 104 is not limited to AlGaN. The electron supply layer 104 can be composed of a group III nitride semiconductor such as AlInGaN containing In. Furthermore, the electron supply layer 104 can contain n-type impurities.

[0038] A cap layer may be provided on the electron supply layer 104. For example, a GaN layer with a thickness of approximately 1-2 nm made of GaN can be used as the cap layer. Furthermore, a spacer layer may be provided between the electron travel layer 103 and the electron supply layer 104. For example, an AlN layer with a thickness of approximately 1 nm made of AlN can be used as the spacer layer.

[0039] A first insulating layer 201 is disposed on the electron supply layer 104. The first insulating layer 201 is an insulating layer containing Si (silicon). In this embodiment, the first insulating layer 201 is a SiN layer composed of SiN. Specifically, the first insulating layer 201 is a 2nm thick SiN layer composed of In-situ SiN. Furthermore, "In-situ" refers to a layer formed without exposure to the atmosphere. Therefore, the first insulating layer 201 composed of In-situ SiN is a SiN layer formed without exposure to the atmosphere after the formation of the electron supply layer 104.

[0040] By constructing the first insulating layer 201 from In-situ SiN, the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 can be eliminated. By eliminating the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104, the generation of interface states is suppressed. This prevents an increase in the interface potential and suppresses the decrease in the electron concentration of the two-dimensional electron gas.

[0041] The thickness of the first insulating layer 201 is preferably 2 nm or more and 30 nm or less. By making the thickness of the first insulating layer 201 2 nm or more, it is possible to suppress the uneven distribution of oxygen at the interface between the first insulating layer 201 and the electron supply layer 104 due to natural oxidation. On the other hand, if the thickness of the first insulating layer 201 exceeds 30 nm, wafer warping will occur during the fabrication of the semiconductor device 1, and the quality of the semiconductor device 1 will be reduced. Therefore, the thickness of the first insulating layer 201 is preferably 30 nm or less. In other words, by making the thickness of the first insulating layer 201 30 nm or less, wafer warping can be suppressed.

[0042] Furthermore, the first insulating layer 201 is preferably oxygen-free. If the first insulating layer 201 contains oxygen, the interface states at the interface between the first insulating layer 201 and the electron supply layer 104 increase, the potential at the interface between the first insulating layer 201 and the electron supply layer 104 rises, and the electron concentration of the two-dimensional electron gas decreases. By making the first insulating layer 201 oxygen-free, the decrease in the electron concentration of the two-dimensional electron gas can be suppressed.

[0043] The second insulating layer 202 is disposed on top of the first insulating layer 201. In this embodiment, the second insulating layer 202 is in contact with the first insulating layer 201. The thickness of the second insulating layer 202 is greater than the thickness of the first insulating layer 201, but it is not limited thereto. That is, the thickness of the second insulating layer 202 may also be thinner than the thickness of the first insulating layer 201. The second insulating layer 202 is, for example, a silicon oxide layer with a thickness of 50 nm made of SiO2. In addition, the second insulating layer 202 is not limited to SiO2, and may also be made of SiN or SiON, etc.

[0044] An opening 201a is provided in the first insulating layer 201. The opening 201a is formed in the first insulating layer 201 in the region where the gate electrode 303 is disposed. Therefore, the first insulating layer 201 is disposed on the portion of the electron supply layer 104 where the gate electrode 303 is not disposed.

[0045] Furthermore, an opening 202a is provided in the second insulating layer 202. The opening 202a is formed in the second insulating layer 202 in the region where the gate electrode 303 is disposed. Therefore, the second insulating layer 202 is disposed on the portion of the first insulating layer 201 where the gate electrode 303 is not disposed.

[0046] The first insulating layer 201 and the second insulating layer 202 are connected to the gate electrode 303. Furthermore, the first insulating layer 201 and the second insulating layer 202 are not connected to the contact layer 212. In this embodiment, the first insulating layer 201 and the second insulating layer 202 are not connected to either the source-side contact layer 212A or the drain-side contact layer 212B, but are not limited thereto. For example, the first insulating layer 201 may not be connected to one of the source-side contact layer 212A or the drain-side contact layer 212B, but may be connected to the other. Similarly, the second insulating layer 202 may not be connected to either the source-side contact layer 212A or the drain-side contact layer 212B, but may be connected to the other.

[0047] A through recess 211 is provided in the electron supply layer 104. In this embodiment, the through recess 211 is provided in such a way that it penetrates the first insulating layer 201 and the electron supply layer 104 and reaches the electron travel layer 103. The through recess 211 reaches the interior of the electron travel layer 103, and a recess is provided in the electron travel layer 103.

[0048] The distance from the upper surface of the electron travel layer 103 to the bottom of the bottom surface of the through-recess 211 is preferably 10 nm or less. For example, the distance from the upper surface of the electron travel layer 103 to the bottom of the bottom surface of the through-recess 211 is 5 nm. Furthermore, the elevation angle of the bottom surface of the through-recess 211 from the center to the side is preferably 10 degrees or less, more preferably 5 degrees or less. Therefore, when forming the through-recess 211 by dry etching, the occurrence of crystal defects on the side of the through-recess 211 can be reduced, and the decrease in maximum drain current can be suppressed.

[0049] The through-recess 211 is provided corresponding to the area where the source electrode 301 and the drain electrode 302 are provided. Specifically, a pair of through-recesses 211 are provided opposite each other with the gate electrode 303 in between.

[0050] A contact layer 212 is provided in the through-recess 211. The contact layer 212 is provided in such a way that it is embedded in the through-recess 211. The contact layer 212 provided on one side of the pair of through-recesses 211 is a source-side contact layer 212A, and the contact layer 212 provided on the other side of the pair of through-recesses 211 is a drain-side contact layer 212B. The source-side contact layer 212A and the drain-side contact layer 212B are provided at a position separated from the gate electrode 303.

[0051] Furthermore, the through recess 211 is provided separately from the first insulating layer 201 and the second insulating layer 202. Therefore, the contact layer 212 embedded in the through recess 211 is also separate from the first insulating layer 201 and the second insulating layer 202, and the contact layer 212 is not in contact with the first insulating layer 201 and the second insulating layer 202.

[0052] The contact layer 212 is, for example, an n-GaN layer composed of n-type GaN. Furthermore, the material constituting the contact layer 212 is not limited to n-type GaN; it can also be composed of group III nitride semiconductors such as InGaN, AlGaN, and AlInGaN, which contain Si, Ge, or other donors as n-type impurities. Alternatively, it can be composed of a multilayer electrode film consisting of sequentially stacked Ti and Al layers. Additionally, the material constituting the contact layer 212 can also be Ti, Ta, Al, Au, Hf, Ru, and Cu.

[0053] A source electrode 301 or a drain electrode 302 is disposed on the contact layer 212. Specifically, the source electrode 301 is disposed on the source-side contact layer 212A, and the drain electrode 302 is disposed on the drain-side contact layer 212B. The source electrode 301 and the drain electrode 302 are disposed opposite each other with the gate electrode 303 in between.

[0054] Furthermore, source electrode 301 and drain electrode 302 are disposed on contact layer 212 and alloy layer 402, respectively. In this embodiment, source electrode 301 and drain electrode 302 also cover a portion of second insulating layer 202. Specifically, source electrode 301 is configured to cover a portion of source-side contact layer 212A, alloy layer 402, and second insulating layer 202. Similarly, drain electrode 302 is configured to cover a portion of drain-side contact layer 212B, alloy layer 402, and second insulating layer 202.

[0055] The source electrode 301 and drain electrode 302 are, for example, composed of a multilayer electrode film, which is formed by sequentially stacking a Ti film with a thickness of 30 nm and an Al film with a thickness of 200 nm, but is not limited thereto. Alternatively, the source electrode 301 and drain electrode 302 may also be composed of Ti, Ta, W, Al, Au, Hf, Ru, and Cu.

[0056] A gate electrode 303 is disposed on the electron supply layer 104. Specifically, the gate electrode 303 is disposed on the electron supply layer 104 via an opening 201a in the first insulating layer 201 and an opening 202a in the second insulating layer 202. Furthermore, the opening width of the opening 201a in the first insulating layer 201 is the same as the opening width of the opening 202a in the second insulating layer 202, but this is not a limitation.

[0057] The gate electrode 303 is, for example, a multilayer electrode film composed of a TiN film and an Al film sequentially stacked. However, the gate electrode 303 is not limited to a TiN and Al film stack; it can also be composed of transition metal nitrides and carbides. Specifically, the gate electrode 303 can also be composed of TiN, WN, TaN, or HfN. Furthermore, the gate electrode 303 can also be composed of Ti, Ta, W, Al, Pd, Pt, Hf, Ru, and Cu, or compounds containing these elements, and can be a multilayer electrode film composed of multiple stacked structures. Additionally, other insulating layers or p-type nitride semiconductor layers can be provided between the electron supply layer 104 and the gate electrode 303.

[0058] The electron supply auxiliary layer 401 is an n-type semiconductor layer composed of an n-type semiconductor containing Si. The thickness of the electron supply auxiliary layer 401 is preferably 2 nm or less, but is not limited thereto. In this embodiment, the electron supply auxiliary layer 401 is an n-AlGaN layer composed of an n-type AlGaN containing Si and with a thickness of 1 nm.

[0059] The electron supply auxiliary layer 401 is not connected to the gate electrode 303, but is connected to the electron supply layer 104 and the contact layer 212. In top view, the electron supply auxiliary layer 401 is disposed between the contact layer 212 and the first insulating layer 201. In cross-sectional view, the electron supply auxiliary layer 401 is disposed in the end of the electron supply layer 104 on the contact layer 212 side. Specifically, in cross-sectional view, the electron supply auxiliary layer 401 is configured such that its upper surface is coplanar with the upper surface of the electron supply layer 104, and its lower surface is located between the upper and lower surfaces of the electron supply layer 104.

[0060] In this embodiment, the electron supply auxiliary layer 401 is connected to both the source-side contact layer 212A and the drain-side contact layer 212B. Specifically, the electron supply auxiliary layer 401 is embedded in the ends of the electron supply layer 104 on the source-side contact layer 212A side and the drain-side contact layer 212B side. Alternatively, the electron supply auxiliary layer 401 may be connected to only one of the source-side contact layer 212A and the drain-side contact layer 212B. Furthermore, the electron supply auxiliary layer 401 may be divided into multiple layers. In this case, the electron supply auxiliary layer 401 on the source electrode 301 side of the multiple electron supply auxiliary layers 401 may be connected to the source-side contact layer 212A, and the electron supply auxiliary layer 401 on the drain electrode 302 side of the multiple electron supply auxiliary layers 401 may be connected to the drain-side contact layer 212B.

[0061] The width of the electron supply auxiliary layer 401 can be smaller than the distance L between the end of the electron supply auxiliary layer 401 on the gate electrode 303 side and the gate electrode 303. As an example, the width of the electron supply auxiliary layer 401 is less than 1 μm in cross-section. As a result, the increase in leakage current between the gate electrode 303 and the drain electrode 302 can be effectively suppressed.

[0062] Alternatively, one of the electron supply auxiliary layer 401 on the source electrode 301 side and the electron supply auxiliary layer 401 on the drain electrode 302 side may not be connected to the gate electrode 303, while the other is connected to the gate electrode 303. For example, if the width of the electron supply auxiliary layer 401 on the drain electrode 302 side is within the aforementioned distance L, the electron supply auxiliary layer 401 on the source electrode 301 side may be connected to the gate electrode 303. This reduces the access resistance between the source electrode 301 and the gate electrode 303, thereby increasing the maximum drain current.

[0063] The alloy layer 402 is disposed on the electron supply auxiliary layer 401, which is an n-type semiconductor layer. Specifically, the alloy layer 402 is disposed directly above the electron supply auxiliary layer 401 and is in contact with the electron supply auxiliary layer 401.

[0064] Alloy layer 402 is a Si-based alloy layer containing Si. Alloy layer 402 is obtained by reacting the elements constituting the first insulating layer 201 with the elements constituting the source electrode 301 and / or drain electrode 302. In this case, the Si constituting alloy layer 402 originates from the Si contained in the first insulating layer 201. In this embodiment, the first insulating layer 201 is a SiN layer, and the source electrode 301 and drain electrode 302 are laminated films of Ti and Al films; therefore, alloy layer 402 is an alloy layer composed of Ti, Al, Si, and N. Specifically, alloy layer 402 is a TiAlSiN alloy layer with a thickness of 1 nm, composed of a TiAlSiN alloy. The thickness of alloy layer 402 is not limited to 1 nm, but is preferably 2 nm or less. This allows for an increase in the Si concentration diffused into the electron supply layer 104.

[0065] Furthermore, the alloy constituting the alloy layer 402 is not limited to a TiAlSiN alloy, and various combinations of alloys can be considered depending on the types of elements constituting the first insulating layer 201 and the types of elements constituting the source electrode 301 and the drain electrode 302. Specifically, the alloy layer 402 may be composed of an alloy containing at least one of the elements Ti, Ta, Al, Au, Hf, Ru and Cu and Si.

[0066] Furthermore, the alloy layer 402 is not connected to the gate electrode 303, but is connected to the contact layer 212. In a top view, the alloy layer 402 is disposed between the contact layer 212 and the first insulating layer 201. In this embodiment, the alloy layer 402 is connected not only to the contact layer 212 but also to the first insulating layer 201.

[0067] In this embodiment, the alloy layer 402 is in contact with both the source-side contact layer 212A and the drain-side contact layer 212B. Alternatively, the alloy layer 402 may be in contact with only either the source-side contact layer 212A or the drain-side contact layer 212B. Furthermore, the alloy layer 402 may be divided into multiple layers. In this case, the alloy layer 402 on the source electrode 301 side of the multiple alloy layers 402 may be in contact with the source-side contact layer 212A, and the alloy layer 402 on the drain electrode 302 side of the multiple alloy layers 402 may be in contact with the drain-side contact layer 212B.

[0068] By configuring the semiconductor device 1 with this structure, the electron concentration of the two-dimensional electron gas layer 105 can be made different in the portion where the electron supply auxiliary layer 401 and alloy layer 402 are present and in the portion where the electron supply auxiliary layer 401 and alloy layer 402 are not present. Specifically, the two-dimensional electron gas layer 105 has a first two-dimensional electron gas layer 105A located not below the electron supply auxiliary layer 401 and alloy layer 402, and a second two-dimensional electron gas layer 105B located in the portion of the electron supply auxiliary layer 401 and alloy layer 402. The electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. In addition, the contact layer 212 and the second two-dimensional electron gas layer 105B are ohmically connected.

[0069] Here, use Figure 2 Explain the mechanism by which the electron concentration of the second two-dimensional electron gas layer 105B is higher than that of the first two-dimensional electron gas layer 105A. Figure 2 This is a schematic diagram showing the conduction band of the energy band of the semiconductor device 1 according to Embodiment 1.

[0070] exist Figure 2 In the middle, the solid line A is parallel to... Figure 1 The diagram shows the part corresponding to the single-dotted line A, and the dashed line B is the part corresponding to... Figure 1 The diagram shows the portion corresponding to the dashed line B. That is, Figure 2 The solid line A in the diagram represents the adjacent portion of the gate electrode 303, i.e., the gate adjacent portion (i.e., the portion without the electron supply auxiliary layer 401 and alloy layer 402). The name of the corresponding layer is indicated by the column (A) with double arrows at the bottom. Additionally, Figure 2The dashed line B in the diagram represents the adjacent portion of the contact layer 212, i.e., the contact adjacent portion (i.e., the portion where the electron supply auxiliary layer 401 and the alloy layer 402 are disposed). The name of the corresponding layer is indicated by the column (B) with double arrows on the upper side. In addition, the dashed line above the electron supply auxiliary layer 401 (on the left side of the diagram) indicates that the Fermi level of the drain electrode 302, which is a metal, coincides with the conduction band.

[0071] As described above, in the semiconductor device 1 according to this embodiment, an electron supply auxiliary layer 401 made of an n-type semiconductor is disposed inside the electron supply layer 104. Consequently, the potential of the electron supply layer 104 is relatively lower in the portion where it is disposed, thus reducing the potential at the interface between the electron supply layer 104 and the electron travel layer 103. As a result, the electron concentration of the second two-dimensional electron gas layer 105B increases. That is, the electron concentration of the second two-dimensional electron gas layer 105B located below the electron supply auxiliary layer 401 is relatively larger than the electron concentration of the first two-dimensional electron gas layer 105A not located below the electron supply auxiliary layer 401.

[0072] In this way, by making the electron concentration of the second two-dimensional electron gas layer 105B higher than that of the first two-dimensional electron gas layer 105A, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be mitigated. As a result, the decrease in the maximum drain current can be suppressed. Moreover, since the electron concentration at the gate adjacent portion corresponding to the first two-dimensional electron gas layer 105A is maintained, the leakage current between the gate electrode 303 and the drain electrode 302 can also be reduced. That is, with the structure of the semiconductor device 1 of this embodiment, the gate-drain leakage current can be reduced while suppressing the decrease in the maximum drain current. In addition, the current increases not only through the contact layer 212 but also through the electron supply auxiliary layer 401 and the alloy layer 402, thus further suppressing the decrease in the maximum drain current.

[0073] Furthermore, in the semiconductor device 1 of this embodiment, the width of the electron supply auxiliary layer 401 is preferably 1 μm or less. This effectively reduces the leakage current between the gate electrode 303 and the drain electrode 302.

[0074] In the semiconductor device 1 of this embodiment, the band gap of the electron supply auxiliary layer 401 side of the electron supply layer 104 below the electron supply auxiliary layer 401 may be smaller than the band gap of the electron travel layer 103 side of the electron supply layer 104. Specifically, when the electron supply layer 104 is made of AlGaN, the Al content of the electron supply auxiliary layer 401 side of the electron supply layer 104 may be smaller than the Al content of the electron travel layer 103 side of the electron supply layer 104. The higher the Al content, the lower the electron affinity of AlGaN, thus lowering the barrier height when the Si-containing alloy layer 402 contacts the electron supply auxiliary layer 401. Therefore, by making the band gap of the electron supply auxiliary layer 401 side of the electron supply layer 104 smaller than the band gap of the electron travel layer 103 side of the electron supply layer 104, the ohmic contact resistance can be reduced. Moreover, by reducing the ohmic contact resistance, the drain current deviation can be reduced.

[0075] Furthermore, in the semiconductor device 1 of this embodiment, the first insulating layer 201 and the electron supply auxiliary layer 401 may contain halogens such as fluorine (F) or chlorine (Cl), and the halogen concentration of both the first insulating layer 201 and the electron supply auxiliary layer 401 is preferably 1×10⁻⁶. 18 atoms / cm 3 The following is because the halogens contained in the semiconductor layer and the insulating layer have high electronegativity, thus becoming a negative fixed charge. Therefore, by making the halogen concentration of the first insulating layer 201 1×10⁻⁶, 18 atoms / cm 3 This reduces the negative fixed charge in the first insulating layer 201. Consequently, the potential rise at the interface between the electron supply layer 104 and the electron travel layer 103 can be eliminated, and the reduction in electron concentration in the second two-dimensional electron gas layer 105B due to halogens can be prevented.

[0076] Furthermore, in the semiconductor device 1 of this embodiment, the thickness of the first insulating layer 201 can be greater than the thickness of the alloy layer 402. This further reduces the leakage current between the gate electrode 303 and the drain electrode 302.

[0077] Next, use Figures 3A to 3G The manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 3A to 3G This is a cross-sectional view showing each step in the manufacturing method of the semiconductor device 1 according to Embodiment 1. Figure 3A The process of forming a semiconductor stacked structure 100 and a first insulating layer 201 and a second insulating layer 202 is shown. Figure 3B The process of forming a thin portion 201b in the first insulating layer 201 is shown. Figure 3C The process of forming the through recess 211 is shown. Figure 3DThe process of forming contact layer 212 is shown. Figure 3E The process of forming the source electrode 301 and the drain electrode 302 is shown. Figure 3F The process of heat treatment is shown. Figure 3G The process of forming the gate electrode 303 is shown.

[0078] First, such as Figure 3A As shown, a semiconductor stack structure 100 comprising a buffer layer 102, an electron travel layer 103, and an electron supply layer 104 is formed on a substrate 101 by metal-organic chemical vapor deposition (MOCVD) (semiconductor stack structure formation process).

[0079] In this embodiment, on the substrate 101 made of Si, in the +c plane direction ( <0001> A buffer layer 102 with a thickness of 2 μm and composed of AlN and AlGaN, an electron transport layer 103 with a thickness of 200 nm and composed of GaN, and an electron supply layer 104 with a thickness of 20 nm and composed of AlGaN with an Al composition ratio of 25% are epitaxially grown sequentially in the direction of the semiconductor stack, thereby forming a semiconductor stack structure 100.

[0080] Next, a first insulating layer 201 is formed on the semiconductor stack structure 100 as an insulating layer containing Si (first insulating layer formation process). Specifically, after forming the semiconductor stack structure 100, a first insulating layer 201 with a thickness of 2 nm made of SiN is formed in the same semiconductor crystal growth apparatus (MOCVD furnace). That is, the first insulating layer 201 is formed on the electron supply layer 104 without being exposed to the atmosphere. In this way, by forming the first insulating layer 201 directly above the electron supply layer 104 without being exposed to the atmosphere, oxygen will not be unevenly distributed between the electron supply layer 104 and the first insulating layer 201.

[0081] Next, a second insulating layer 202 is formed on the first insulating layer 201 (second insulating layer formation process). Specifically, after forming the first insulating layer 201, the substrate 101 on which the semiconductor stack structure 100 and the first insulating layer 201 are formed is transferred to another device to form a second insulating layer 202 with a thickness of 50 nm made of SiO2. In this structure, a high concentration of two-dimensional electron gas is generated on the electron travel layer 103 side of the heterogeneous interface between the electron supply layer 104 and the electron travel layer 103, forming a two-dimensional electron gas layer 105.

[0082] Furthermore, the film-forming conditions for forming the first insulating layer 201 and the second insulating layer 202 include, for example, a growth temperature of 900~1150°C and feed gases of SiH4 and NH3. Additionally, to prevent halogens from being introduced into the first insulating layer 201 as impurities, it is preferable not to use halogens during dry cleaning of the MOCVD furnace. Furthermore, even if halogens are used during dry cleaning, they can be removed from the MOCVD furnace after dry cleaning using N2, NH3, or the like.

[0083] Next, as Figure 3B As shown, a portion of the first insulating layer 201 is thinned to form a thin portion 201b in the first insulating layer 201 (thin portion forming process).

[0084] Specifically, after coating the second insulating layer 202 with a photoresist, the photoresist is patterned using photolithography, thereby forming a mask (resist mask) on the second insulating layer 202 except for the regions where the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402 are formed. That is, openings are formed in the regions of the photoresist where the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402 are formed. Specifically, openings are formed in regions including the regions where the source-side contact layer 212A and the drain-side contact layer 212B are formed.

[0085] Next, etching is performed using a resist with openings as a mask to remove a portion of the second insulating layer 202 and to thin a portion of the first insulating layer 201. In this case, by performing dry and wet etching using a resist with openings as a mask, the second insulating layer 202 can be selectively removed relative to the first insulating layer 201. That is, by performing dry and wet etching, the second insulating layer 202 is removed and the first insulating layer 201 is thinned in the areas where the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402 are formed. Thus, as Figure 3B As shown, a portion of the first insulating layer 201 (the area forming the contact layer 212, the electron supply auxiliary layer 401, and the alloy layer 402) can be thinned to form a thin portion 201b in the first insulating layer 201 as a residual film. Then, the mask (resist) and the polymer produced by dry etching are removed.

[0086] Furthermore, when performing wet etching on the first insulating layer 201 and the second insulating layer 202, the second insulating layer 202 can be selectively removed relative to the first insulating layer 201 by using DHF or BHF. Alternatively, when forming the second insulating layer 202 composed of SiO2, only a portion of the first insulating layer 201 can be selectively removed by oxidizing the surface of the first insulating layer 201.

[0087] Furthermore, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably 2 nm or less. In this case, the thickness of the thin portion 201b (residual film) of the first insulating layer 201 is preferably more than half the thickness of the first insulating layer 201 before thinning (i.e., preferably more than half remaining), but is not limited thereto. As an example, when the thickness of the first insulating layer 201 before thinning is 2 nm, the thin portion 201b (residual film) of the first insulating layer 201 is 1.5 nm.

[0088] Next, as Figure 3C As shown, a through recess 211 is formed by removing the end of the thin portion 201b of the first insulating layer 201 and a portion of the semiconductor stacked structure 100 (through recess formation process). Specifically, a portion of the thin portion 201b of the first insulating layer 201 is left as an insulating layer residue 201b1, and a through recess 211 is formed that penetrates the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103.

[0089] In this case, firstly, after applying a photoresist over the second insulating layer 202 and a portion of the thin portion 201b of the first insulating layer 201, the photoresist is patterned using photolithography, thereby forming a mask (photoresist mask) outside the region where the through-recess 211 is formed. That is, the photoresist forms an opening in the region where the through-recess 211 is formed. Specifically, the photoresist has openings in the regions where the source-side contact layer 212A and the drain-side contact layer 212B are formed, respectively.

[0090] Next, dry etching is performed using a resist with the opening as a mask, thereby leaving a portion of the thin portion 201b of the first insulating layer 201 as an insulating layer residue 201b1, and forming a through recess 211 that penetrates the end of the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103. Specifically, as Figure 3C As shown, two through-recesses 211 are formed corresponding to the regions forming the source-side contact layer 212A and the drain-side contact layer 212B. By forming the through-recesses 211, a portion of the electron travel layer 103 is exposed. Then, the mask (resist) and the polymer generated by dry etching are removed.

[0091] Furthermore, in this embodiment, the through-hole recess 211 is formed by dry etching, but it is not limited to this. Specifically, the through-hole recess 211 can also be formed by wet etching.

[0092] Alternatively, after thinning the first insulating layer 201 and forming the through-recess 211 by dry etching, the side surface of the electron supply layer 104 can be selectively wet-etched using SPM, APM, or KOH. This allows the side surface of the through-recess 211 to be an inclined surface. Specifically, the side surface of the through-recess 211 can be made to have an angle of less than 5 degrees in the direction from the center of the bottom surface of the through-recess 211 toward the side.

[0093] Next, as Figure 3D As shown, a contact layer 212 is embedded in the through recess 211 (contact layer forming process).

[0094] Specifically, using the residual insulating layer 201b1 of the second insulating layer 202 and the first insulating layer 201 as a mask, MOCVD is applied to embed n into the two through recesses 211. + -GaN growth. Therefore, it is possible to selectively embed n-GaN into the two through-recesses 211 respectively. + - A GaN-based contact layer 212. Furthermore, the contact layer 212 embedded in one of the two through-recesses 211 is a source-side contact layer 212A, and the contact layer 212 embedded in the other of the two through-recesses 211 is a drain-side contact layer 212B.

[0095] In this embodiment, Si is doped as an n-type impurity, with a thickness of 100 nm. + GaN is grown to form the contact layer 212. The Si doping concentration of the contact layer 212 is, for example, 2 × 10⁻⁶. 19 / cm 3 Furthermore, not limited to regrowth, the contact layer 212 can also be formed by sputtering, or it can be formed by ion implantation and plasma treatment without forming the through recess 211.

[0096] Next, as Figure 3E As shown, a source electrode 301 and a drain electrode 302 are formed across the insulating layer residue 201b1 of the first insulating layer 201 and the contact layer 212 (source electrode / drain electrode formation process).

[0097] Specifically, after forming a laminated film by sequentially depositing a 30 nm thick Ti film and a 200 nm thick Al film by evaporation or sputtering, the unwanted laminated film is removed by lift-off, thereby forming a source electrode 301 and a drain electrode 302 of a predetermined shape composed of the Ti and Al film laminated film on the contact layer 212. In this embodiment, the source electrode 301 is formed on the source-side contact layer 212A, and the drain electrode 302 is formed on the drain-side contact layer 212B. Then, the resist mask and polymer are removed.

[0098] In addition, in this embodiment, the source electrode 301 and the drain electrode 302 are formed by vapor deposition and stripping, but are not limited thereto. For example, after forming a stacked film by sequentially depositing Ti film and Al film by sputtering, the stacked film can be patterned using photolithography and dry etching to form the source electrode 301 and drain electrode 302 of a predetermined shape.

[0099] Next, as Figure 3F As shown, heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 in the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 (heat treatment process).

[0100] The heat treatment temperature is, for example, 400~600°C, preferably 500~550°C. Furthermore, the heat treatment is preferably performed in an oxygen-free atmosphere. In this embodiment, the heat treatment was carried out at 540°C in a N2 atmosphere.

[0101] By performing heat treatment in this way, the elements constituting the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 diffuse and alloy with the elements constituting the source electrode 301 and the drain electrode 302 due to heat, forming the electron supply auxiliary layer 401 and the alloy layer 402.

[0102] Specifically, in this embodiment, since the first insulating layer 201 is an insulating layer containing Si and the electron supply layer 104 is an AlGaN layer, in the upper portion of the electron supply layer 104 that is connected to the insulating layer residue 201b1 of the first insulating layer 201, nitrogen vacancies are formed due to the diffusion of Si constituting the first insulating layer 201, thus forming an n-type AlGaN layer as an electron supply auxiliary layer 401. That is, an electron supply auxiliary layer 401 as an n-type semiconductor layer is formed.

[0103] Furthermore, in this embodiment, since the source electrode 301 and drain electrode 302 contain Ti, nitrogen vacancies are formed due to the diffusion of Ti, thereby making the upper portion of the electron supply layer 104 n-type. That is, in this embodiment, the upper portion of the electron supply layer 104 is n-type through the diffusion of Si and Ti caused by heat treatment, forming an electron supply auxiliary layer 401 as an n-type semiconductor layer.

[0104] In this way, the upper portion of the electron supply layer 104 is n-type to form an electron supply auxiliary layer 401, which serves as an n-type semiconductor layer, thereby generating a second two-dimensional electron gas layer 105B with a higher electron concentration than the first two-dimensional electron gas layer 105A. As a result, the second two-dimensional electron gas layer 105B is ohmically connected to the source electrode 301 and the drain electrode 302.

[0105] Furthermore, in order to facilitate the diffusion of Si from the first insulating layer 201 to the electron supply layer 104 through heat treatment, the insulating layer residue 201b1, which is part of the thin portion 201b of the first insulating layer 201, is preferably thin. In this case, as described above, the thickness of the thin portion 201b of the first insulating layer 201 is preferably 2 nm or less. This increases the Si content in the upper portion of the electron supply layer 104, allowing for further n-type shaping of the upper portion of the electron supply layer 104.

[0106] Next, as Figure 3G As shown, the first insulating layer 201, the portion of which is separated from the source electrode 301 and the drain electrode 302, is removed to form the gate electrode 303 (gate electrode formation process). In this embodiment, since a second insulating layer 202 is formed on the first insulating layer 201, the portion of the first insulating layer 201 separated from the source electrode 301 and the drain electrode 302 in both the first insulating layer 201 and the second insulating layer 202 is removed to form the gate electrode 303.

[0107] Specifically, after applying a photoresist onto the second insulating layer 202, a mask (photoresist mask) is formed outside the area where the gate electrode 303 is formed (the predetermined area for gate electrode formation) using photolithography. Next, the second insulating layer 202 and the first insulating layer 201 are selectively removed using dry etching, forming an opening 201a in the first insulating layer 201 and an opening 202a in the second insulating layer 202 to expose the electron supply layer 104. Then, the mask (photoresist mask) and the polymer generated by dry etching are removed. Afterward, the gate electrode 303 is formed in the openings 201a and 202a. Specifically, after forming a stacked film consisting of a 50nm thick TiN film and a 450nm thick Al film sequentially deposited by sputtering, the stacked film is patterned using photolithography and dry etching to form... Figure 3F The gate electrode 303 is of the specified shape shown. Then, the mask and the polymer produced by dry etching are removed.

[0108] Thus, after Figures 3A to 3G A series of processes to complete Figure 1 The semiconductor device 1 shown has the following structure.

[0109] (Implementation Method 2) Next, use Figure 4 The semiconductor device 2 of Embodiment 2 will be described. Figure 4 This is a cross-sectional view showing the structure of the semiconductor device 2 according to Embodiment 2. Furthermore, the following description focuses on the differences from Embodiment 1, omitting or simplifying the description of commonalities.

[0110] The semiconductor device 2 of this embodiment differs from the semiconductor device 1 of Embodiment 1 in that the source electrode 301A and drain electrode 302A have different structures. Specifically, the source electrode 301A and drain electrode 302A in this embodiment are integrally formed with the contact layer 212 made of the same material as the source electrode 301 and drain electrode 302 in the semiconductor device 1 of Embodiment 1.

[0111] More specifically, in this embodiment, the source electrode 301A is a structure in which the source electrode 301 and the source-side contact layer 212A are made of the same material and are integrally formed, as in Embodiment 1. Furthermore, in this embodiment, the drain electrode 302A is a structure in which the drain electrode 302 and the drain-side contact layer 212B are made of the same material and are integrally formed, as in Embodiment 1. That is, the semiconductor device 2 of this embodiment does not have a contact layer made of a semiconductor material.

[0112] In this embodiment, the source electrode 301A and the drain electrode 302A are disposed in a manner that embeds them within the through-hole recess 211. Furthermore, the source electrode 301A and the drain electrode 302A are disposed such that a portion of the alloy layer 402 and the second insulating layer 202 are covered. The source electrode 301A and the drain electrode 302A are, for example, composed of a multilayer electrode film, which is a stacked structure formed by sequentially stacking a 30 nm thick Ti film and a 200 nm thick Al film, but are not limited thereto. Additionally, the source electrode 301A and the drain electrode 302A do not contain Au, but are not limited thereto. Furthermore, the materials constituting the source electrode 301A and the drain electrode 302A can be Ti, Ta, Al, Hf, Ru, and Cu.

[0113] The source electrode 301A and drain electrode 302A thus constructed are ohmically connected to the second two-dimensional electron gas layer 105B.

[0114] The semiconductor device 2 of this embodiment can also achieve the same effects as in Embodiment 1 described above. Specifically, in this embodiment, an electron supply auxiliary layer 401 and an alloy layer 402, which serve as n-type semiconductor layers, are also provided. Therefore, the electron concentration of the second two-dimensional electron gas layer 105B is greater than that of the first two-dimensional electron gas layer 105A. As a result, the decrease in electron concentration at the side adjacent portion of the through-recess 211 in the electron supply layer 104 can be mitigated, thereby suppressing the decrease in the maximum drain current.

[0115] Furthermore, in the semiconductor device 2 according to this embodiment, the source electrode 301A and the drain electrode 302A also function as contact layers, and no contact layer made of semiconductor material is provided. This reduces the number of steps involved in forming the contact layer. Additionally, in the semiconductor device 2 according to this embodiment, the source electrode 301A and the drain electrode 302A do not contain Au, thus reducing manufacturing costs.

[0116] Next, use Figures 5A to 5F The manufacturing method of the semiconductor device 2 in this embodiment will be described. Figures 5A to 5F This is a cross-sectional view showing each step in the manufacturing method of the semiconductor device 2 according to Embodiment 2. Figure 5A The process of forming a semiconductor stacked structure 100 and a first insulating layer 201 and a second insulating layer 202 is shown. Figure 5B The process of forming a thin portion 201b in the first insulating layer 201 is shown. Figure 5C The process of forming the through recess 211 is shown. Figure 5D The process of forming source electrode 301A and drain electrode 302A is shown. Figure 5E The process of heat treatment is shown. Figure 5F The process of forming the gate electrode 303 is shown.

[0117] First, such as Figure 5A As shown, using MOCVD, a semiconductor stack structure 100 comprising a buffer layer 102, an electron transport layer 103, and an electron supply layer 104 is formed on a substrate 101 (semiconductor stack structure formation process). This process is similar to that in Embodiment 1 described above. Figure 3A The procedures are the same.

[0118] Next, as Figure 5B As shown, a portion of the first insulating layer 201 is thinned to form a thin portion 201b in the first insulating layer 201 (thin portion forming process). This process is similar to that in Embodiment 1 described above. Figure 3B The procedures are the same.

[0119] Next, as Figure 5C As shown, a through-recess 211 is formed by removing the end of the thin portion 201b of the first insulating layer 201 and a portion of the semiconductor laminate structure 100 (through-recess formation process). Specifically, a portion of the thin portion 201b of the first insulating layer 201 is left as an insulating layer residue 201b1, and a through-recess 211 is formed that penetrates the thin portion 201b of the first insulating layer 201 and the electron supply layer 104 to reach the electron travel layer 103. This process is similar to that in Embodiment 1 described above. Figure 3C The procedures are the same.

[0120] Next, as Figure 5DAs shown, a source electrode 301A and a drain electrode 302A are embedded in the through recess 211 (source electrode / drain electrode formation process). Specifically, the source electrode 301A and the drain electrode 302A are formed across the insulating layer residue 201b1 of the first insulating layer 201 and the through recess 211.

[0121] In this embodiment, using the second insulating layer 202 and the first insulating layer 201 as masks, Ti films and Al films are sequentially deposited by sputtering to form a stacked film embedded in the through-recess 211. Then, a mask is formed in the region where the source electrode 301A and the drain electrode 302A are formed by photolithography. The region where the mask is formed spans the through-recess 211, the insulating layer residue 201b1 of the first insulating layer 201, and the second insulating layer 202 when viewed from above. Next, the Al and Ti films outside the region where the mask is formed are removed by dry etching, thereby forming the source electrode 301A and the drain electrode 302A across the insulating layer residue 201b1 of the first insulating layer 201 and the through-recess 211. Finally, the mask and polymer are removed.

[0122] Next, as Figure 5E As shown, heat treatment is performed to form an electron supply auxiliary layer 401 and an alloy layer 402 on the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 (heat treatment process). This process is the same as that in Embodiment 1 described above. Figure 3F The process is the same. That is, by performing heat treatment, the elements constituting the insulating layer residue 201b1 of the first insulating layer 201 and the electron supply layer 104 diffuse and alloy with the elements constituting the source electrode 301A and the drain electrode 302A due to heat, forming the electron supply auxiliary layer 401 and the alloy layer 402.

[0123] Next, as Figure 5F As shown, the first insulating layer 201, the portion of which is separated from the source electrode 301A and the drain electrode 302A is removed to form the gate electrode 303 (gate electrode formation process). In this embodiment, since the second insulating layer 202 is formed on the first insulating layer 201, the gate electrode 303 is formed by removing the portions of the first insulating layer 201 and the second insulating layer 202 that are separated from the source electrode 301A and the drain electrode 302A. This process is the same as in Embodiment 1 described above. Figure 3G The procedures are the same.

[0124] Thus, after Figures 5A to 5F A series of processes to complete Figure 4 Semiconductor device 2 with the structure shown.

[0125] (Modified example) The semiconductor device of this disclosure has been described above based on Embodiment 1 and Embodiment 2, but this disclosure is not limited to Embodiment 1 and Embodiment 2.

[0126] For example, in Embodiments 1 and 2 described above, the electron travel layer 103 and the electron supply layer 104 are made of group III nitride semiconductors, but are not limited thereto. Specifically, the electron travel layer 103 and the electron supply layer 104 may be made of other semiconductor materials such as group III arsenide semiconductors.

[0127] Furthermore, this disclosure also includes various modifications conceived by those skilled in the art to the above embodiments, and methods of arbitrarily combining the constituent elements and functions of the embodiments without departing from the spirit of this disclosure. Additionally, this disclosure also includes solutions obtained by arbitrarily combining two or more claims from the multiple claims recited in the claims at the time of filing this application, to the extent that they are not technically contradictory. For example, when a dependent claim recited in the claims at the time of filing this application is designated as a plurality of claims or a plurality of dependent claims by referencing all superior claims to the extent that they are not technically contradictory, the combination of all claims contained in such plurality of claims or plurality of dependent claims is also included in this disclosure.

[0128] Industrial applicability The technology disclosed herein can be used in semiconductor devices such as switching transistors for use in communication equipment, inverters, and power supply circuits that require high-speed operation. In particular, the technology disclosed herein is applicable to high-frequency power devices where heat generation caused by ohmic contact resistance has a significant impact.

[0129] Explanation of reference numerals in the attached figures 1, 2 Semiconductor Devices 100 Semiconductor Stacked Structure 101 substrate 102 Buffer Layer 103 Electronic Travel Layer 104 Electronic Supply Layer 105 Two-Dimensional Electron Gas Layer 105A First Two-Dimensional Electron Gas Layer 105B Second Two-Dimensional Electron Gas Layer 201 First Insulation Layer 201a opening 201b Thin section 201b1 Insulation layer residue 202 Second Insulation Layer 202a opening 211 Through-depression 212 contact layer 212A source-side contact layer 212B Drain-side Contact Layer 301, 301A source electrodes 302, 302A drain electrode 303 gate electrode 401 Electronic Supply Auxiliary Layer 402 alloy layer

Claims

1. A semiconductor device, characterized in that, have: Electronic travel layer; An electron supply layer is disposed on the electron travel layer, and its band gap is larger than that of the electron travel layer; A gate electrode is disposed on the electron supply layer; The source-side contact layer and the drain-side contact layer are buried in the recess that runs through the electron supply layer at a position separated from the gate electrode. An n-type semiconductor layer, composed of an n-type semiconductor containing Si, is connected to the electron supply layer and to the source-side contact layer and / or the drain-side contact layer, but is not grounded to the gate electrode. An alloy layer, disposed on the n-type semiconductor layer, contains at least one of the elements Ti, Ta, Al, Au, Hf, Ru and Cu, and Si, with a thickness of less than 2 nm; An insulating layer is disposed on the portion of the electron supply layer where the gate electrode is not disposed, and is in contact with the gate electrode but not in contact with the source-side contact layer and / or the drain-side contact layer; as well as The source electrode and / or drain electrode are disposed on the source-side contact layer and / or the drain-side contact layer and on the alloy layer.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the n-type semiconductor layer is less than 2 nm.

3. The semiconductor device according to claim 1 or 2, characterized in that, In cross-section, the width of the n-type semiconductor layer is less than 1 μm.

4. The semiconductor device according to claim 1 or 2, characterized in that, In the lower part of the n-type semiconductor layer, the band gap of the portion of the electron supply layer on the n-type semiconductor layer side is smaller than the band gap of the portion of the electron travel layer side in the electron supply layer.

5. The semiconductor device according to claim 1 or 2, characterized in that, The source electrode and the source-side contact layer are made of the same material and do not contain Au. The drain electrode and the drain-side contact layer are made of the same material and do not contain Au.

6. The semiconductor device according to claim 1 or 2, characterized in that, The halogen concentration of the insulating layer is 1×10⁻⁶. 18 atoms / cm 3 the following.

7. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the insulating layer is greater than the thickness of the alloy layer.

8. The semiconductor device according to claim 7, characterized in that, The thickness of the insulating layer is greater than 2nm and less than 30nm.

9. The semiconductor device according to claim 1 or 2, characterized in that, There is no uneven distribution of oxygen between the insulating layer and the electron supply layer.

10. The semiconductor device according to claim 1 or 2, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

11. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: The process of forming an electron supply layer with a larger bandgap than the electron travel layer on the electron travel layer; The process of forming a Si-containing insulating layer on the electron supply layer without exposing it to the atmosphere; The process of thinning a portion of the insulating layer to form a thin section in the insulating layer; A process in which a portion of the thin portion remains as an insulating layer residue, and a through recess is formed that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; The process of embedding and forming a contact layer in the through recess; The process of forming a source electrode and / or a drain electrode across the insulating layer residue and the contact layer; The process of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the residual portion of the insulating layer and the electron supply layer; as well as The process of forming a gate electrode by removing the portion of the insulating layer that is separated from the source electrode and / or the drain electrode. The electron supply auxiliary layer is an n-type semiconductor layer composed of an n-type semiconductor containing Si. The alloy layer is disposed on the n-type semiconductor layer and contains at least one of the elements Ti, Ta, Al, Au, Hf, Ru and Cu, and Si.

12. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: The process of forming an electron supply layer with a larger bandgap than the electron travel layer on the electron travel layer; The process of forming a Si-containing insulating layer on the electron supply layer without exposing it to the atmosphere; The process of thinning a portion of the insulating layer to form a thin section in the insulating layer; A process in which a portion of the thin portion remains as an insulating layer residue, and a through recess is formed that penetrates the thin portion of the insulating layer and the electron supply layer to reach the electron travel layer; The process of forming a source electrode and / or a drain electrode across the insulating layer residue and the through-recess; The process of performing heat treatment to form an alloy layer and an electron supply auxiliary layer in the residual portion of the insulating layer and the electron supply layer; as well as The process of forming a gate electrode by removing the portion of the insulating layer that is separated from the source electrode and / or the drain electrode. The electron supply auxiliary layer is an n-type semiconductor layer composed of an n-type semiconductor containing Si. The alloy layer is disposed on the n-type semiconductor layer and contains at least one of the elements Ti, Ta, Al, Au, Hf, Ru and Cu, and Si.

13. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that, The insulating layer is composed of SiN.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, There is no uneven distribution of oxygen between the insulating layer and the electron supply layer.

15. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that, In the process of forming a thin portion on the insulating layer, the thickness of the thin portion is less than 2 nm.

16. The method of manufacturing a semiconductor device according to claim 11 or 12, characterized in that, The electron travel layer and the electron supply layer are made of group III nitride semiconductors.

Images