A DCR detection unit for peak current mode DCM mode

Abstract

This invention discloses a DCR detection unit for peak current mode DCM, applicable to ultra-low DCR detection. The DCR detection unit includes a reverse current comparator, a peak current comparator, and a current compensation module. Compared to the common peak current mode BUCK structure, it controls L / R... dcr The ratio of R*C improves the signal-to-noise ratio of the input signal, while the added current compensation module ensures the accuracy of the wide load output range and the current reverse shutdown in DCM mode, ultimately achieving a high-efficiency, wide load output range BUCK circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a DCR detection unit for peak current mode DCM. Background Technology

[0002] With the rapid development of automotive electronics and intelligent electronic devices, stringent requirements have been placed on the performance, power consumption, and lifespan of power management chips. Peak current mode, as the most widely used control method in switching power supplies, offers advantages such as fast loop response and ease of control loop design. To improve the signal-to-noise ratio of the current sensing signal and ensure the accuracy of current limiting, the use of HAOO DCR power inductors to maximize conversion efficiency has become a major research direction in current switching power supply design.

[0003] The error of the DC resistance (DCR) of an inductor can be controlled within 5% with current technology, therefore this sampling method is more accurate than MOSFET RDS sampling. Furthermore, this sampling method only adds a resistor and a capacitor, resulting in a simple circuit structure and low cost. Since the added components cause almost no losses, this sampling method is highly efficient. Especially under high load current output conditions, the efficiency of inductor DCR sampling is significantly better than that of external resistor sampling. Summary of the Invention

[0004] The purpose of this invention is to provide a DCR detection unit for peak current mode DCM mode to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a DCR detection unit for peak current mode DCM, comprising:

[0006] A reverse current comparator, used in DCM mode, shuts off the synchronous rectifier when the current reverses to zero.

[0007] The peak current comparator compares the output of the external error amplifier with the weighting coefficient of the sampled inductor current to form a current loop, thereby improving the dynamic response speed.

[0008] The current compensation module achieves accuracy and efficiency for the peak current comparator and reverse current comparator under the premise of high signal-to-noise ratio of the detection input.

[0009] In one embodiment, the reverse current comparator includes: a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a first Schmitt trigger, and a first current detection readout circuit;

[0010] The sources of both the first and second PMOS transistors are connected to VDD. The gates of both the first and second PMOS transistors are connected to the drain of the second PMOS transistor. The drain of the second PMOS transistor is connected to the output of the first current detection readout circuit. The positive input of the first current detection readout circuit is the detection input of the DRC detection unit. senseN The input stage, the negative input terminal of the first current detection readout circuit is the detection I of the DRC detection unit. senseP Input level;

[0011] The drain of the first PMOS transistor and the drain of the third NMOS transistor are both connected to the input of the first Schmitt trigger. The source of the third NMOS transistor is connected to GND. The output of the first Schmitt trigger is the control signal of the first reverse current comparator.

[0012] In one embodiment, the peak current comparator includes: a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, a second Schmitt trigger, a second current detection and readout circuit, and a first resistor;

[0013] The sources of the fifth and sixth PMOS transistors are both connected to VDD. The gates of the fifth and sixth PMOS transistors are both connected to the drain of the sixth PMOS transistor. The drains of the sixth PMOS transistor and the seventh NMOS transistor are connected to the output of the second current detection readout circuit. The positive input of the second current detection readout circuit is the detection input of the DRC detection unit. senseP The input stage, the negative input terminal of the second current detection readout circuit is the detection I of the DRC detection unit. senseN Input level;

[0014] The drains of the fifth PMOS transistor and the fourth NMOS transistor are both connected to the input of the second Schmitt trigger. The source of the fourth NMOS transistor is grounded through the first resistor. The source of the seventh NMOS transistor is connected to GND. The gate of the seventh NMOS transistor is connected to the gate of the third NMOS transistor. The output of the first Schmitt trigger is the control signal of the second reverse current comparator. The gate of the fourth NMOS transistor is connected to the output of the external error amplifier.

[0015] In one embodiment, the current compensation module includes: an eighth NMOS transistor, a first fully differential low-pass filter, and a third current detection and readout circuit;

[0016] The source of the eighth NMOS transistor is connected to GND, and its gate is connected to the gate of the seventh NMOS transistor. Both the drain and gate of the eighth NMOS transistor are connected to the output of the third current detection readout circuit. The positive input of the third current detection readout circuit is connected to the positive output of the first fully differential low-pass filter, and the negative input is connected to the negative output of the first fully differential low-pass filter. The positive input of the first fully differential low-pass filter is the detection input of the DRC detection unit. senseP The input stage, the inverting input of the first fully differential low-pass filter is the detection input of the DRC detection unit. senseN Input level.

[0017] In one embodiment, the detection I of the DRC detection unit senseP The input stage is simultaneously connected to the second terminal of the sampling resistor and the first terminal of the sampling capacitor; the detection I of the DRC detection unit senseN The input stage is connected to both the second terminal of the sampling capacitor and the second terminal of the parasitic resistor; the first terminal of the sampling resistor is connected to the first terminal of the inductor, and the second terminal of the inductor is connected to the first terminal of the parasitic resistor.

[0018] This invention provides a DCR detection unit for peak current mode (DCM). Peak current mode sampling is achieved through DCR detection. Ultra-low DCR sampling requires configuring the inductor L and its parasitic resistance R_dcr with the ratio of R and C at the sampling terminal to increase the AC signal amplitude and improve the signal-to-noise ratio of the detection input signal. To ensure that the output current under large loads is not limited by a large detection peak current and to ensure accurate zero-crossing turn-off at current valleys in DCM mode, a current compensation module is added. This system can achieve wide-load, high-efficiency DCR detection. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a DCR detection unit for peak current mode DCM provided by the present invention.

[0020] Figure 2 This is a schematic diagram of the reverse current comparator provided by the present invention.

[0021] Figure 3 This is a schematic diagram of a reverse current comparator and the current zero-crossing point.

[0022] Figure 4 This is a system block diagram of a peak current comparator.

[0023] Figure 5 It is a peak current comparator and error amplifier I ea A schematic diagram.

[0024] Figure 6 This is a system block diagram of the current compensation module. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the DCR detection unit for peak current mode DCM proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0026] This invention provides a DCR detection unit for peak current mode DCM mode, used for detecting small DC resistance in current mode switching power supplies, and its structure is as follows. Figure 1 As shown, the system includes a reverse current comparator (IRVE), a peak current comparator (ICMP), and a current compensation module (Current_Compensation). The inverting input of the first current detection readout circuit CR1 in the reverse current comparator is connected to the non-inverting input of the second current detection readout circuit CR2 in the peak current comparator. This connection point is also connected to the non-inverting input of the first fully differential low-pass filter LPF1 in the current compensation module; simultaneously, this connection point serves as the DRC detection input. senseP Input terminal. The positive input terminal of the first current detection readout circuit CR1 in the reverse current comparator is connected to the inverting input terminal of the second current detection readout circuit CR2 in the peak current comparator. This connection point is also connected to the inverting input terminal of the first fully differential low-pass filter LPF1 in the current compensation module. Simultaneously, this connection point serves as the DRC detection input. senseN Input terminal. The gate of the third NMOS transistor M3 in the reverse current comparator is connected to the gate of the seventh NMOS transistor M7 in the peak current comparator. This connection point is connected to the gate of the eighth NMOS transistor M8 in the current compensation module.

[0027] In this invention, different L / R ratios are set. _dcr The ratio of L to RC (i.e., L / R) _dcr The (RC) amplifies the peak-to-peak value of the AC signal of the inductor current, improving the input signal-to-noise ratio. Compared with the common peak current mode BUCK with DCM mode, it adds a current compensation module. The compensation current is set according to the ratio of the amplified peak-to-peak value, which can ensure that it is not limited by the large detection peak current when the load output is large and the accuracy of the zero-crossing turn-off of the current valley in DCM mode is guaranteed. The system can realize wide load and high efficiency DCR detection.

[0028] like Figure 2As shown, the reverse current comparator includes: a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a first Schmitt trigger sensor MMT1, and a first current detection and readout circuit CR1. The sources of both the first PMOS transistor M1 and the second PMOS transistor M2 are connected to VDD. The gates of both the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the drain of the second PMOS transistor M2. The drain of the second PMOS transistor M2 is connected to the output of the first current detection and readout circuit CR1. The positive input of the first current detection and readout circuit CR1 is the DRC detection input. senseN The negative input terminal of the first current detection readout circuit CR1 in the input stage is the DRC detection I. senseP Input stage: The drains of the first PMOS transistor M1 and the third NMOS transistor M3 are both connected to the input of the first Schmitt trigger SMT1. The source of the third NMOS transistor M3 is connected to GND. The output of the first Schmitt trigger SMT1 is the reverse current comparator control signal VO1.

[0029] like Figure 4 As shown, the peak current comparator includes: a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh NMOS transistor M7, a second Schmitt trigger SMT2, a second current detection and readout circuit CR2, and a first resistor R1. The sources of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are both connected to VDD. The gates of the fifth PMOS transistor M5 and the sixth PMOS transistor M6 are both connected to the drain of the sixth PMOS transistor M6. The drains of the sixth PMOS transistor M6 and the seventh NMOS transistor M7 are both connected to the output of the second current detection and readout circuit CR1. The positive input of the second current detection and readout circuit CR2 is the DRC detection input. senseP The negative input terminal of the second current detection readout circuit CR2 in the input stage is the DRC detection I. senseN Input stage: The drains of the fifth PMOS transistor M5 and the fourth NMOS transistor M4 are both connected to the input of the second Schmitt trigger SMT2. The source of the fourth NMOS transistor M4 is grounded through the first resistor R1. The source of the seventh NMOS transistor M7 is connected to GND. The output of the first Schmitt trigger SMT1 is the reverse current comparator control signal VO2.

[0030] like Figure 6As shown, the current compensation module includes: an eighth NMOS transistor M8, a first fully differential low-pass filter LPF1, and a third current detection and readout circuit CR3. The source of the eighth NMOS transistor M8 is connected to GND. The gates of the eighth NMOS transistor M8 and the seventh NMOS transistor M7 are both connected to the gate of the third NMOS transistor M3. The drain and gate of the eighth NMOS transistor M8 are both connected to the output of the third current detection and readout circuit CR3. The positive input of the third current detection and readout circuit CR3 is connected to the positive output of the first fully differential low-pass filter LPF1, and the negative input of the third current detection and readout circuit CR3 is connected to the negative output of the first fully differential low-pass filter LPF1. The positive input of the first fully differential low-pass filter LPF1 is connected to the DRC detection circuit I... senseP The inverting input of the first fully differential low-pass filter LPF1 is the DRC detection I. senseN .

[0031] The DCR detection unit provided by this invention is based on a peak current-mode BUCK topology, and by adding a current compensation module, it achieves high signal-to-noise ratio signal detection and large load output, such as... Figure 2 The diagram shows the schematic of a reverse current comparator, which detects the reverse inductor current. Its implementation is as follows: when the load decreases to the critical conduction mode, there will be...

[0032]

[0033] When entering DCM mode, the following requirements must be met:

[0034]

[0035] Among them I O For the average output current, I pp For peak-to-peak current, when When L is inductance, R _dcr Let C be the parasitic DC resistance of the inductor, C be the sampling filter capacitor, and R be the sampling filter resistor; proportional to both sides of equation (2) by K, we can obtain:

[0036]

[0037] The left side of the formula represents the DCR detection valley current read by the first current detection and reading circuit CR1, such as... Figure 3 As shown, when it approaches (1-K)I O When the current comparator flips, it shuts down the low-power transistor to prevent inductor current from flowing back.

[0038] Figure 4 This is the schematic diagram of a peak current comparator. K equals 1, peak current mode I eaThe relationship with the output current is as follows:

[0039]

[0040] like Figure 5 As shown, when K > 1, the following will occur:

[0041]

[0042] Substitute into formula (5):

[0043]

[0044] According to formula (7), the left side of the equation is the peak current of the sample, and the right side of the equation is the output current of the error amplifier and the compensation current. This current can dynamically increase the output swing of the error amplifier and improve the output current capability.

[0045] According to formulas (4) and (7), the compensation current is -(K-1)I. O , where I O The average output current, Figure 6 The medium current compensation module filters the sampled signal through the first fully differential low-pass filter LPF1 to obtain the average sampled inductor current, and controls the output current ratio of the third current detection and readout circuit CR3 to be (K-1) times I. O .

[0046] In summary, the DCR detection unit for peak current mode DCM mode of the present invention, by adding a current compensation module, ensures a wide load output range and the accuracy of current reverse turn-off in DCM mode while achieving high signal-to-noise ratio signal detection.

[0047] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A DCR detection unit for peak current mode DCM mode, characterized in that, include: A reverse current comparator, used in DCM mode, shuts off the synchronous rectifier when the current reverses to zero. The peak current comparator compares the output of the external error amplifier with the weighting coefficient of the sampled inductor current to form a current loop, thereby improving the dynamic response speed. The current compensation module achieves accuracy and efficiency of the peak current comparator and reverse current comparator under the premise of high detection input signal-to-noise ratio; The reverse current comparator includes: a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a first Schmitt trigger, and a first current detection and readout circuit; The sources of both the first and second PMOS transistors are connected to VDD. The gates of both the first and second PMOS transistors are connected to the drain of the second PMOS transistor. The drain of the second PMOS transistor is connected to the output of the first current detection readout circuit. The positive input of the first current detection readout circuit is the detection input of the DRC detection unit. senseN The input stage, the negative input terminal of the first current detection readout circuit is the detection I of the DRC detection unit. senseP Input level; The drain of the first PMOS transistor and the drain of the third NMOS transistor are both connected to the input terminal of the first Schmitt trigger, the source of the third NMOS transistor is connected to GND, and the output of the first Schmitt trigger is the first reverse current comparator control signal. The peak current comparator includes: a fourth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh NMOS transistor, a second Schmitt trigger, a second current detection and readout circuit, and a first resistor; The sources of the fifth and sixth PMOS transistors are both connected to VDD. The gates of the fifth and sixth PMOS transistors are both connected to the drain of the sixth PMOS transistor. The drains of the sixth PMOS transistor and the seventh NMOS transistor are connected to the output of the second current detection readout circuit. The positive input of the second current detection readout circuit is the detection input of the DRC detection unit. senseP The input stage, the negative input terminal of the second current detection readout circuit is the detection I of the DRC detection unit. senseN Input level; The drains of the fifth PMOS transistor and the fourth NMOS transistor are both connected to the input of the second Schmitt trigger. The source of the fourth NMOS transistor is grounded through the first resistor. The source of the seventh NMOS transistor is connected to GND. The gate of the seventh NMOS transistor is connected to the gate of the third NMOS transistor. The output of the second Schmitt trigger is the control signal of the second reverse current comparator. The gate of the fourth NMOS transistor is connected to the output of the external error amplifier. The current compensation module includes: an eighth NMOS transistor, a first fully differential low-pass filter, and a third current detection and readout circuit; The source of the eighth NMOS transistor is connected to GND, and its gate is connected to the gate of the seventh NMOS transistor. Both the drain and gate of the eighth NMOS transistor are connected to the output of the third current detection readout circuit. The positive input of the third current detection readout circuit is connected to the positive output of the first fully differential low-pass filter, and the negative input is connected to the inverted output of the first fully differential low-pass filter. The positive input of the first fully differential low-pass filter is the detection input of the DRC detection unit. senseP The input stage, the inverting input of the first fully differential low-pass filter is the detection input of the DRC detection unit. senseN Input level.

2. The DCR detection unit for peak current mode DCM as described in claim 1, characterized in that, The detection I of the DRC detection unit senseP The input stage is connected to both the second terminal of the sampling resistor and the first terminal of the sampling capacitor. The detection I of the DRC detection unit senseN The input stage is connected to both the second terminal of the sampling capacitor and the second terminal of the parasitic resistor; the first terminal of the sampling resistor is connected to the first terminal of the inductor, and the second terminal of the inductor is connected to the first terminal of the parasitic resistor.

Images