Reset control method and device, electronic equipment, storage medium and computer program product

Abstract

Embodiments of the present disclosure provide a reset control method and device, electronic equipment, storage medium and computer program product. The reset control method is applied to a die included in a chip. The chip includes a master die and at least one slave die. The method includes: receiving a target reset request sent by a target reset source in a plurality of reset sources; determining target reset control logic and a target reset domain corresponding to the target reset request; and sending a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action. The reset object includes at least part of functional modules in the master die and / or at least part of functional modules in the slave die. The present scheme can meet the reset requirements of multiple types, multiple levels and multiple dies in a multi-die system, and ensure correct reset, thereby ensuring the temperature and function of the multi-die system.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a reset control method, apparatus, electronic device, storage medium, and computer program product. Background Technology

[0002] Reset is an essential function of a chip, ensuring that it starts operating from a defined initial state. In packages or systems comprising multiple dies, specific design and control strategies enable these dies to perform reset operations collaboratively. This ensures the entire system functions correctly after reset, while preventing system instability or malfunctions caused by reset signal propagation and timing issues.

[0003] For packages or systems with multiple dies, there are various types of reset objects that cover different levels, and multiple dies need to work together to perform the reset operation. If the reset is not properly controlled, it will lead to system instability or functional abnormalities. Therefore, how to determine the reset object covered by the reset according to the reset type and control the reset object to perform the correct reset operation is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of the above, embodiments of this disclosure provide a reset control method, apparatus, electronic device, storage medium, and computer program product to at least solve or alleviate the above problems.

[0005] According to a first aspect of the present disclosure, a reset control method is provided, applied to a die including a chip, the chip including a master die and at least one slave die, the method comprising: receiving a target reset request sent by a target reset source among a plurality of reset sources; determining a target reset control logic and a target reset domain corresponding to the target reset request; and, according to the target reset control logic, sending a reset signal to a reset object included in the target reset domain, causing the reset object to perform a reset action, the reset object including at least some functional modules in the master die and / or at least some functional modules in the slave die.

[0006] According to a second aspect of the present disclosure, a reset control device is provided, applied to a die including a chip, the chip including a master die and at least one slave die, the device comprising: a receiving unit, configured to receive a target reset request sent by a target reset source among a plurality of reset sources; a processing unit, configured to determine a target reset control logic and a target reset domain corresponding to the target reset request; and a sending unit, configured to send a reset signal to a reset object included in the target reset domain according to the target reset control logic, causing the reset object to perform a reset action, the reset object including at least some functional modules in the master die and / or at least some functional modules in the slave die.

[0007] According to a third aspect of the present disclosure, an electronic device is provided, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform an operation corresponding to the reset control method described in the first aspect above.

[0008] According to a fourth aspect of the present disclosure, a computer storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the reset control method as described in the first aspect above.

[0009] According to a fifth aspect of the present disclosure, a computer program product is provided, including computer instructions that instruct a computing device to perform the reset control method as described in the first aspect above.

[0010] According to the reset control scheme provided in this disclosure, multiple reset sources can send reset requests. After receiving a target reset request from a target reset source among the multiple reset sources, the target reset control logic and target reset domain corresponding to the target reset request are determined. Then, a reset request can be sent to the reset object included in the target reset domain according to the target reset control logic, causing the reset object to perform a reset action. The reset object may include at least some functional modules in the master die and / or slave die. Since reset requests from multiple reset sources can be received, and the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes some or all functional modules in the master die and / or slave die, the reset requirements of multiple types, multiple levels, and multiple die collaboration in a multi-die system can be met, ensuring correct reset and thus ensuring the normal temperature and function of the multi-die system. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 This is a schematic diagram of an exemplary system to which this disclosure is applied, according to one embodiment.

[0013] Figure 2 This is a flowchart of a reset control method according to an embodiment of the present disclosure;

[0014] Figure 3 This is a flowchart of a reset signal transmission method according to an embodiment of the present disclosure;

[0015] Figure 4 This is a timing diagram of an iFLR according to an embodiment of this disclosure;

[0016] Figure 5 This is a timing diagram of another embodiment of the iFLR of this disclosure;

[0017] Figure 6 This is a reset timing diagram of an embodiment of the present disclosure;

[0018] Figure 7 This is a reset timing diagram of another embodiment of this disclosure;

[0019] Figure 8 This is a schematic diagram of a reset control device according to an embodiment of the present disclosure;

[0020] Figure 9 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0021] The present disclosure is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present disclosure below, certain specific details are described in detail. Those skilled in the art will fully understand the present disclosure even without these details. To avoid obscuring the substance of the present disclosure, well-known methods, processes, and procedures are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0022] First, some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0023] Chip: Also known as an integrated circuit (IC), a chip is a miniature electronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) onto a small semiconductor material. Based on their function and application, chips can be classified into various types, such as central processing units (CPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0024] A bare die is an unpackaged single chip obtained after a wafer has been processed, tested, and diced during semiconductor manufacturing. A bare die only has solder pads for packaging and cannot be directly used in actual circuits. Because bare dies are highly susceptible to damage from external environmental factors such as temperature, impurities, and physical forces, they must be encapsulated in a sealed space with corresponding leads to be used as a basic component.

[0025] Reset: Chip reset refers to the process of restoring a chip from its current state to its initial state. The initial state of a chip is usually its default configuration state after power-on, where internal resources such as registers and state machines are set to their initial values, the program counter points to the initial address, and it awaits new instruction input.

[0026] PCIe: Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect computers and peripheral devices. It is widely used in various devices such as desktop computers, servers, and embedded systems, and is one of the important bus technologies in modern computer systems.

[0027] Exemplary System

[0028] Figure 1 An exemplary system for a reset control method applicable to embodiments of this disclosure is shown. For example... Figure 1 As shown, the exemplary system includes a master die 11 and multiple slave dies 12, which are interconnected. For example, the master die 11 can be interconnected with the slave dies 12 via a PCIe bus. This disclosure does not limit the packaging relationship between the master die 11 and the slave dies 12. For example, the master die 11 and slave dies 12 included in the exemplary system can be packaged in the same chip, or the master die 11 and some of the slave dies 12 can be packaged in the same chip, or all the slave dies 12 included in the exemplary system can be packaged in the same chip, or the master die 11 and slave dies 12 can be packaged as separate chips. When the master die 11 and slave dies 12 are packaged in the same chip, they can communicate via an on-chip bus. When the master die 11 and slave dies 12 are packaged in different chips, they can communicate via an inter-chip interconnect bus.

[0029] When the exemplary system includes a master die 11 and a slave die 12 packaged in the same chip, the exemplary system can be a system on a chip (SoC) that includes multiple dies. In addition to the multiple dies, the SoC can also include a scheduling unit (such as a CPU, ASIC, FPGA, etc.). The scheduling unit can schedule the multiple dies to perform computing tasks, such as scheduling the multiple dies to perform computing tasks such as model training and model inference.

[0030] When the master die 11 and slave die 12 included in the exemplary system are packaged onto different chips, the exemplary system may be a SoC or electronic device including multiple chips. If the exemplary system is a SoC including multiple chips, the SoC may include a scheduling unit in addition to the chips corresponding to the master die 11 and slave die 12. If the exemplary system is an electronic device, the electronic device includes a printed circuit board (PCB), the chips corresponding to the master die 11 and slave die 12 are connected to the PCB, the scheduling unit is also connected to the PCB, the master die 11 and slave die 12 are connected through traces in the PCB, and the scheduling unit and the master die 11 are connected through traces in the PCB.

[0031] In one example, the master die11 and slave die12 constitute a graphics processing unit (GPU) comprising multiple basic computing units. The master die11 and slave die12 serve as the basic computing units of the GPU, which can be CUDA (Compute Unified Device Architecture) cores or stream processors (SPs). The CPU can schedule the GPU to perform computational tasks, such as scheduling the GPU to perform model training or model inference tasks.

[0032] It should be noted that, in addition to communicating with the master Die11, different slave Dies12 can also communicate with each other via the intra-chip bus or the inter-chip bus.

[0033] The master die 11 can reset some or all modules in the master die 11 and / or slave die 12 based on a reset request from a reset source. Reset sources can be of various types, such as a scheduling unit, a module in the master die 11 or slave die 12, or a watchdog timer.

[0034] This disclosure focuses on the process of controlling the reset of the master die 11 and the slave die 12. The reset control process will be described in detail later.

[0035] Reset control method

[0036] Based on the exemplary system described above, this disclosure provides a reset control method, which can be executed by the master die 11 or the slave die 12 in the exemplary system embodiment. The reset control method will be described in detail below through several embodiments.

[0037] Figure 2 This is a reset control method according to one embodiment of the present disclosure, which is executed by the master Die 11 or the slave Die 12 in the above system embodiment. For example... Figure 2 As shown, the reset control method includes the following steps:

[0038] Step 201: Receive the target reset request sent by the target reset source among multiple reset sources.

[0039] A reset source is software or hardware that issues a reset request. Multiple reset sources can issue reset requests. The currently received reset request is defined as the target reset request, and the reset source that issues the target reset request among the multiple reset sources is defined as the target reset source. A reset source can issue a reset request to either the master die 11 or the slave die 12. When the master die 11 receives a target reset request, it resets itself, at least one slave die 12, or at least some functional modules included in multiple slave dies 12 based on the target reset request. When a slave die 12 receives a target reset request, it resets at least some functional modules it includes based on the target reset request. In other words, the master die 11 can perform a coordinated reset of multiple dies included in the chip according to the reset request, and the slave die 12 can reset itself according to the reset request.

[0040] Step 202: Determine the target reset control logic and target reset domain corresponding to the target reset request.

[0041] Upon receiving a target reset request, the target reset control logic corresponding to the target reset request is determined from multiple reset control logics, and the target reset domain corresponding to the target reset request is also determined. The reset control logic defines the various operations required to implement the reset and the timing of each operation, such as the types and timing of signals sent and received to implement the reset. The reset domain defines the reset objects involved in the reset operation. The reset objects include at least some functional modules in the main Die 11 and / or at least some functional modules in the slave Die 12; that is, the reset domain defines which functional modules in the main Die 11 and / or slave Die 12 need to be reset.

[0042] Different reset requests correspond to different reset domains, and different reset domains include different functional modules. For example, a global cross-die reset request (por_n) corresponds to all functional modules included in the main Die11 and the subordinate Die12. A multi-subsystem cross-die reset request with optional reset domains (pf_cov_ctrl, pe_as_por) corresponds to multiple subsystems included in the main Die11 and the subordinate Die12. A computation subsystem cross-die reset request (pf reset) corresponds to the computation subsystems included in the main Die11 and the subordinate Die12. An interconnect subsystem reset request (inter conn reset) corresponds to the interconnect subsystems included in the main Die11 and / or the subordinate Die12. Interconnect subsystems are used for inter-chip interconnection.

[0043] In one example, the chip's memory stores multiple reset control logics, which both the master die 11 and the slave die 12 can access. Upon receiving a target reset request, either the master die 11 or the slave die 12 can read the target reset control logic corresponding to that request from memory, allowing them to share the reset control logic. For instance, if the chip's memory stores reset control logic A for resetting the interconnect subsystem, the master die 11 can read reset control logic A from the chip's memory upon receiving a reset request for its interconnect subsystem, and the slave die 12 can also read reset control logic A from the chip's memory upon receiving a reset request for its interconnect subsystem.

[0044] Step 203: According to the target reset control logic, send a reset signal to the reset object included in the target reset domain to cause the reset object to perform a reset action.

[0045] After determining the target reset control logic and the target reset domain, a reset signal is sent to the reset objects included in the target reset domain according to the target reset control logic to control the reset objects to perform reset actions.

[0046] If the target reset domain includes only the functional modules in the main die 11, the main die 11 sends a reset signal to the reset objects within the target reset domain according to the target reset control logic. If the target reset domain includes the main die 11 and at least one functional module in the slave die 12, the main die 11 sends a reset signal to the reset objects within the target reset domain in the main die 11 according to the target reset control logic, and also sends a reset signal to the reset objects within the target reset domain in the slave die 12 via the slave die 12. If the target reset domain includes functional modules in multiple slave dies 12, the main die 11 sends a reset signal to the reset objects within the target reset domain in the slave die 12 via the slave die 12 according to the target reset control logic. If the target reset domain includes only a functional module in a specific slave die 12, that slave die 12 sends a reset signal to the functional module within the target reset domain in that slave die 12 according to the target reset control logic.

[0047] In this embodiment, multiple reset sources can send reset requests. Upon receiving a target reset request from a target reset source among the multiple reset sources, the target reset control logic and target reset domain corresponding to the target reset request are determined. Then, a reset request can be sent to the reset object included in the target reset domain according to the target reset control logic, causing the reset object to perform a reset action. The reset object may include at least some functional modules in the master die 11 and / or slave die 12. Because reset requests from multiple reset sources can be received, and the corresponding reset control logic and reset domain are determined based on the received reset requests, with the reset domain including some or all functional modules in the master die 11 and / or slave die 12, the reset requirements of multiple types, multiple levels, and multiple die collaborations in a multi-die system can be met, ensuring correct reset and thus guaranteeing the normal temperature and function of the multi-die system.

[0048] In one possible implementation, the target reset request can be a soft reset with the protocol's built-in handshake mechanism, a custom soft reset, a linkage reset caused by the reset of some functional modules, a gatekeeper reset under the protection mechanism, or a reset under the debugging mechanism.

[0049] The soft reset with its built-in handshake mechanism is a Function Level Reset (FLR). The FLR mechanism allows software to reset the device at a functional granularity. FLR is primarily for PCIe devices that support multiple functions (Multi-FunPCIe Devices), enabling the reset of specific functions while leaving others unaffected. The reset source for a soft reset with its built-in handshake mechanism can be software running on the CPU.

[0050] A custom soft reset can be a software-implemented reset of a microcontroller unit (MCU) or control subsystem. Therefore, the reset source for a custom soft reset can be an MCU or a control subsystem.

[0051] Resets triggered by certain functional module resets include sideband signal resets (perst_n), linkdown resets, and hot resets. Sideband signal resets are resets based on sideband signals, which trigger the fundamental reset of PCIe devices, including cold and warm resets. Triggering is achieved by powering on / off the mains power supply or by configuring registers within the host computer; the reset source for sideband signal resets is either the mains power supply or registers within the host computer. Linkdown resets are non-fundamental resets related to link disconnection. Hot resets are in-band resets that do not use sideband signals. They are generated by writing 0 followed by 1 to the Secondary BusReset bit in the configuration space of a specific port on the bridge device; the reset source for hot resets is the bridge device.

[0052] The watchdog reset under the protection mechanism is triggered by the internal watchdog timer in the die; that is, the reset source for the watchdog reset under the protection mechanism is the internal watchdog timer in the die.

[0053] MCU debug reset is a reset triggered by the external MCU under the debug mechanism, meaning the reset source under the debug mechanism is the external MCU.

[0054] In this embodiment, the target reset request can be of various types, such as a soft reset with a built-in handshake mechanism, a custom soft reset, a linkage reset caused by the reset of some functional modules, a gatekeeper reset under the protection mechanism, or a reset under the debugging mechanism. Thus, the corresponding reset control logic and reset domain can be determined for different types of resets, ensuring that different types of resets can be executed correctly while ensuring the stability of system operation.

[0055] In one possible implementation, when determining the target reset control logic corresponding to the target reset request, the target reset control logic can be determined from a plurality of alternative reset control logics. At least some of the alternative reset control logics correspond to reset requests from multiple reset sources, and different alternative reset control logics correspond to reset requests from different reset sources.

[0056] Multiple alternative reset control logics are pre-created, and at least some of these alternatives correspond to reset requests from multiple reset sources. This means some alternatives are applicable to reset requests from different sources, or some are reused by multiple reset sources. Upon receiving a target reset request, the target reset control logic corresponding to the target reset request is determined from among the multiple alternatives.

[0057] In one example, sideband signal reset (perst_n), linkdown reset, hot reset, and soft reset with built-in handshake mechanism (FLR) multiplex the reset control logic of the computing subsystem cross-die reset (pf reset). That is, sideband signal reset, linkdown reset, hot reset, soft reset with built-in handshake mechanism, and computing subsystem cross-die reset correspond to the same alternative reset control logic. MCU-related resets such as MCU reset enable (MCU rst_en) and watchdog timer multiplex the reset control logic of MCU reset. That is, MCU reset enable reset and watchdog timer reset correspond to the same alternative reset control logic. Multiple interconnect subsystem reset enable (INTER CONN rst_en) multiplex the reset control logic of interconnect subsystem reset (inter conn reset). pf_cov_ctrl and pe_as_por are two reset configurations for multi-subsystem cross-die resets that can be selected for the reset domain. The same reset source will produce different reset effects under different reset configurations. pf_cov_ctrl reuses the reset control logic of the computation subsystem cross-die reset (pf reset), while pe_as_por reuses the power-on reset (PoR) finite state machine (FSM) reset control logic to complete the global reset of the entire chip and the re-power-on reset initialization.

[0058] In one example, multiple alternative reset control logics are stored in the chip's memory, and different types of reset requests or reset requests from different reset sources share and reuse the alternative reset control logics in memory.

[0059] In the embodiments of this disclosure, reset requests of different types or from different reset sources can reuse reset control logic. At least some alternative reset control logic is reused by multiple reset requests of different types or from different reset sources. The reset operation of each type of reset request can be realized by a small number of alternative reset control logics, so that the alternative reset control logic occupies a small amount of storage space, ensuring the performance of the chip, and making the chip reset system more streamlined.

[0060] In one possible implementation, a global reset request refers to a reset request that affects the entire chip, meaning that a global reset request will reset all functional modules included in the main Die 11 and the slave Die 12. A non-global reset request refers to a reset request that affects a portion of the chip, meaning that a non-global reset request will prevent some functional modules included in the main Die 11 and / or the slave Die 12 from being reset, while all other functional modules in the main Die 11 and the slave Die 12 except for those functional modules that are not reset will be reset.

[0061] When the target reset request is a non-global reset request, before sending a reset signal to the reset objects included in the target reset domain, an isolation signal (Resetiso) may be sent to at least some of the reset objects included in the target reset domain. The isolation signal can return the signals in the master Die11 and slave Die12 located at the boundary of the target reset domain to their initial state.

[0062] In one example, before sending a target reset request, the System Control Unit (SCU) in either the master Die 11 or the slave Die 12 can select and initiate an appropriate isolation mechanism based on the reset mode of the target reset request. After completing the corresponding minimum-granularity isolation task, it begins to reset the reset object within the target reset domain. The reset source can be certain soft resets or certain data sequences specified by the protocol (such as FLR, hot reset, etc.), or certain configurable registers (such as inter_conn_rst_en, mcu_sw_rst_en, ctrl_sw_rst_en, etc.), or certain external control reset signals (such as perst_n), or certain abnormal events that have occurred (such as linkdown, watchdog timeout, etc.).

[0063] In this embodiment, before sending the reset signal, an isolation signal is sent to the reset object located at the boundary of the target reset domain. The isolation signal can be the signal in the main Die 11 and the slave Die 12 located at the boundary of the target reset domain, returning it to its initial state. This ensures that the cross-Die signal is in a known state when the reset is released, avoiding metastability caused by timing deviations. The reset domain boundary signal is forced to return to its initial value, avoiding logical confusion (such as deadlock, data conflict, etc.) caused by some modules not being fully reset. Combined with reset sequence control, this ensures the stability of the data path and reduces logical errors caused by reset timing differences.

[0064] In one possible implementation, before sending a reset signal to the reset objects included in the target reset domain, a reset activation protection signal (Reset AssertionGuard) can be sent to at least some of the reset objects included in the target reset domain. This reset activation protection signal ensures that unreset functional modules are not affected by reset functional modules when the reset objects included in the target reset domain are asynchronously reset and activated. By sending the reset activation protection signal, during asynchronous reset activation, no violation caused by actual activation will occur, thus preventing harm to those unreset logic.

[0065] The reset activation protection signal can activate the isolation and protection mechanism, ensuring the protocol integrity of the interface and returning to the initial state before the reset, so as to ensure that subsequent reset actions will not affect adjacent control modules.

[0066] After sending a reset signal to the reset objects included in the target reset domain, a reset deassertion guard signal can be sent to at least some of the reset objects included in the target reset domain. The reset deassertion guard signal prevents residual reset data from being input into the de-reset reset objects. By sending the reset deassertion guard signal, during reset de-reset, it prevents residual data backflow caused by differences in reset timing (to prevent de-reset from occurring while the other is still reset). The guard blocks this residual data to protect the circuit that de-reset first.

[0067] After sending the reset release protection signal, a de-reset signal is sent to the reset objects included in the target reset domain according to the target reset control logic.

[0068] In one example, during the reset control process, the SCU needs to reuse the reset control logic as much as possible and make reasonable use of the Reset iso or guard logic at each reset domain interface location to minimize the impact. For instance, if the same reset source changes in the current reset configuration (pf_cov_ctrl or pe_as_por), the SCU will choose to expand or shrink the range of Resetiso / FLR in resetting the current reset control logic, and expand or shrink the current reset domain after the Reset iso ends. If the reset configuration is in global reset mode, no Reset iso will be initiated; the logic of the local cross-die reset request (por_n) will be directly reused, and the live electrolytic reset process will restart after all resets are completed.

[0069] All reset sources share and reuse multiple reset isolation mechanisms and logic in the current chip memory, with the SCU responsible for overall coordination, initiation, and handshake. The SCU reuses the reset control logic to simultaneously initiate the corresponding Reset Assertion Guard and Reset Deassertion Guard. The Reset Assertion Guard is used to protect functional modules that are not reset, while the Reset Deassertion Guard (mainly for PCIe interfaces where the core reset is not controlled by the SCU; after a PCIe reset, downstream computing subsystems need to be reset in conjunction, and the downstream computing subsystems' in conjunction resets need to be reset after the reset isolation is completed) is used to protect upstream PCIe from de-reset before downstream computing subsystems' in conjunction resets, preventing residual data from flowing to the de-reset upstream PCIe.

[0070] In this embodiment, before sending a reset signal to the reset objects within the target reset domain, a reset activation protection signal is sent to at least a portion of the reset objects within the target reset domain. This ensures that when a reset object within the target reset domain is reset activated, unreset functional modules are not affected by reset functional modules. After sending the reset signal, a reset deactivation protection signal is sent to at least a portion of the reset objects within the target reset domain to prevent residual reset data from being input to deactivated reset objects. By sending the reset activation protection signal and the reset deactivation protection signal, the reset process is ensured to execute correctly, and the stability and normal function of the chip are guaranteed after reset.

[0071] In one possible implementation, if the reset object includes at least some functional modules in a master die 11 and at least one slave die 12, when the master die 11 sends a reset signal to the reset object included in the target reset domain, the master die 11 first acquires a master die isolation completion signal and a slave die isolation completion signal. The master die isolation completion signal is used to indicate that the signal in the master die 11 located at the boundary of the target reset domain returns to its initial state, and the slave die isolation completion signal is used to indicate that the signal in the slave die 12 located at the boundary of the target reset domain returns to its initial state. After acquiring the master die isolation completion signal and the slave die isolation completion signal, the master die 11 sends a first reset signal to the reset object located within the target reset domain in the master die 11 and sends a second reset signal to the slave die 12, causing the slave die 12 to control the reset object located within the target reset domain to reset according to the second reset signal.

[0072] It should be noted that when the reset target includes multiple functional modules from slave dies 12, after receiving the master die isolation completion signal and slave die isolation completion signals returned by all slave dies 12 containing functional modules within the target reset domain, the master die 11 then sends a first reset signal and a second reset signal. Upon receiving the second reset signal, a slave die 12 can control the functional module within that slave die 12 located within the target reset domain to perform a reset action based on the second reset signal. The master die 11 controls the functional modules within its own slave die 11 located within the target reset domain to perform a reset action via the first reset signal.

[0073] If the reset target includes at least some functional modules from multiple slave dies 12, when the master die 11 sends a reset signal to the reset target included in the target reset domain, the master die 11 first obtains the slave die isolation completion signals returned by all slave dies 12 with functional modules located within the target reset domain. After receiving the slave die isolation completion signals returned by all slave dies 12 with functional modules located within the target reset domain, the master die 11 then sends a second reset signal to each slave die 12 with functional modules located within the target reset domain. After receiving the second reset signal, the slave die 12 controls the functional modules within that slave die 12 located within the target reset domain to perform a reset action based on the second reset signal.

[0074] The master die 11 and slave die 12 have different responsibilities. When the target reset domain includes functional modules in multiple dies (master die 11 + slave die 12 or multiple slave die 12), the target reset source is mainly reflected in the master die, specifically in the SCU of the master die. The slave die 12 is responsible for the reset control of the included functional modules. The master die 11 controls the reset process of multiple dies (master die 11 + slave die 12 or multiple slave die 12). The slave dies collect their respective information and return it to the master die 11. After collecting the isolation completion signals (master die isolation completion signal and / or slave die isolation completion signal) of multiple dies (master die 11 + slave die 12 or multiple slave die 12), the master die 11 initiates the corresponding reset signal (first reset signal and / or second reset signal), and simultaneously resets the master die 11, transmits the reset signal to the slave die 12. While Die12 works in conjunction with the main Die11 to complete the current reset process, it ensures that the reset process of the main Die11 is kept synchronized.

[0075] In this embodiment, when the reset target includes at least some functional modules of at least two dies, the target reset source is mainly reflected in the master die. The master die controls the reset process of multiple dies covered by the target reset domain. After isolation is completed, slave die 12 sends a die isolation completion signal to master die 11. After receiving the master die isolation completion signal and the slave die isolation completion signal, master die 11 issues a first reset signal and a second reset signal. While resetting master die 11, it also transmits the reset signal to slave die 12. Slave die 12 cooperates with master die 11 to complete the reset while ensuring synchronization with the reset process of master die 11. Master die 11 controls the reset process of multiple dies, and slave die 12 cooperates with master die 11 to control the reset of their respective functional modules, so that the reset processes of master die 11 and slave die 12 remain synchronized, ensuring that the reset process can be performed correctly, thereby ensuring system stability and normal function.

[0076] In one possible implementation, the first reset signal is a reset signal sent by the main Die 11 to the functional module to be reset in the main Die 11, and the second reset signal is a reset signal sent by the main Die 11 to the functional module to be reset in the secondary Die 12. The second reset signal contains less information than the first reset signal.

[0077] In this embodiment, the master die 11 controls the reset process of multiple dies. A significant amount of reset information is transmitted between the master die 11 and the slave die 12. To reduce the input / output (I / O) resources occupied by the transmission of reset information between dies, the slave die 12 only receives the necessary multiplexed reset information. The reset information between the master die 11 and the slave die 12 is asymmetrical, meaning that the second reset signal contains less information than the first reset signal. This reduces the amount of data transmitted between dies during the reset process, reduces the I / O resource occupation of the reset information, and ensures the system performance during the reset process.

[0078] In one possible implementation, when the target reset request is a linked reset caused by the reset of a partial functional module (such as perst_n, linkdown reset, hot reset, etc.), it is possible to... Figure 3 The reset signal transmission method shown sends a reset signal to the reset object included in the target reset domain. For example... Figure 3 As shown, the reset signal sending method includes the following steps:

[0079] Step 301: Input the target reset request into the virtual functional level reset state machine included in the main die, so that the virtual functional level reset state machine generates an intermediate reset signal.

[0080] The SCU's control logic mainly includes a Virtual Function Level Reset (VFLR) generator (VFLR_GEN) and a Function Level Reset State Machine (FLR_FSM). In the PCIe protocol, VFLR is an independent reset mechanism for virtual functions (VFs) in the SR-IOV (Single Root I / O Virtualization) architecture. The SCU in Die12 does not include the VFLR_GEN component.

[0081] VFLR_GEN is responsible for receiving interface reset events, such as perst_n, linkdown reset, and hot reset. Upon these events, VFLR generates a handshake mechanism mimicking the FLR portion of the PCIe protocol, using a state machine approach. The virtual function-level reset state machine states IDLE / BME / ACTIVE / RETIRE within VFLR_GEN are configurable timing parameters of virtual FLR generators set according to FLR specifications.

[0082] After receiving the target reset request, the master Die11 inputs the target reset request into the virtual functional level reset state machine, which can generate an intermediate reset signal based on the target reset request.

[0083] Step 302: Input the intermediate reset signal into the functional level reset state machine included in the main die, so that the functional level reset state machine included in the main die generates a first reset signal, and sends the first reset signal to the reset object located in the target reset domain in the main die.

[0084] VFLR_GEN and the FLR mechanism from PCIe share FLR_FSM. FLR_FSM is responsible for receiving handshake signals from VFLR_GEN or the FLR from PCIe, completing the Intelligent Function Level Reset (iFLR) handshake mechanism within this die, and sending the physical function reset signal (pf_rstb) for this die. Die12 only receives pf_rstb from the master die11. In the PCIe protocol, iFLR is an enhanced function level reset mechanism designed to optimize the efficiency and controllability of traditional FLRs. The pf_rstb signal acts on a single physical function (PF) module, resetting its internal logic (such as configuration registers, state machines, data paths, etc.), but does not affect other PFs or virtual functions (VFs) in the same device. The reset domain of pf_rstb normally only contains the computation subunit. When pf_cov_ctrl is enabled, the reset domain of pf_rstb will be expanded to include the control subsystem (including the inter-die transmission module).

[0085] FLR_FSM mainly includes states such as DEASSERT / FLR_REQ / FLR_DONE / ASSERT, which are basically the timing control of the iFLR handshake mechanism and the timing control of pf_rstb activation and deassertion.

[0086] After the main die 11 inputs the intermediate reset signal into the FLR_FSM included in the main die, the FLR_FSM included in the main die 11 will generate a first reset signal based on the intermediate reset signal, and then send the first reset signal to the reset object (functional module) located in the target reset domain in the main die.

[0087] Step 303: Input the intermediate reset signal into the functional level reset state machine included in the die, so that the functional level reset state machine included in the die generates a second reset signal, and sends the second reset signal to the reset object located in the target reset domain in the die.

[0088] After the virtual functional level reset state machine in the master die 11 generates an intermediate reset signal, the master die 11 inputs the intermediate reset signal into the FLR_FSM included in the master die, and simultaneously inputs the intermediate reset signal into the FLR_FSM in the slave die 12. The FLR_FSM in the slave die 12 generates a second reset signal based on the intermediate reset signal, and can then send the second reset signal to the reset object (functional module) located in the target reset domain in the slave die 12.

[0089] In this embodiment, the SCU control logic of the master die 11 includes VFLR_GEN and FLR_FSM, and the SCU control logic of the slave die 12 includes FLR_FSM. When the target reset request is a virtual function level reset (such as perst_n, linkdownreset, hot reset, etc.), VFLR_GEN generates an intermediate reset signal according to the target reset request and inputs the intermediate reset signal into the FLR_FSM included in the master die 11 and the slave die 12 respectively. The FLR_FSM in the master die 11 generates a first reset signal based on the intermediate reset signal, and the FLR_FSM in the slave die 12 generates a second reset signal based on the intermediate reset signal. This ensures that the master die 11 and the slave die 12 can handle virtual function level resets normally, simplifies the reset process, and ensures the efficiency and reliability of the reset process.

[0090] In one possible implementation, when the target reset request is a soft reset (such as FLR) with a built-in handshake mechanism, the master die 11 inputs the target reset request into both the master die 11 and the FLR_FSM included in the slave die 12. This causes the FLR_FSM included in the master die 11 to generate a first reset signal, and the FLR_FSM included in the slave die 12 to generate a second reset signal. The master die 11 sends the first reset signal to the reset object within the target reset domain in the master die 11, and the slave die 12 sends the second reset signal to the reset object within the target reset domain in the slave die 12.

[0091] In the PCIe protocol, FLR_FSM is a hardware state machine used to control and manage the Functional Level Reset (FLR) process.

[0092] In this embodiment, when the target reset request is a soft reset with a built-in handshake mechanism, the target reset request is input into the FLR_FSM included in the main Die 11 to generate a first reset signal, and the target reset request is input into the FLR_FSM included in the secondary Die 12 to generate a second reset signal. When the target reset request is a linkage reset caused by a partial functional module reset, an intermediate reset signal is input into the FLR_FSM included in the main Die 11 to generate a first reset signal, and an intermediate reset signal is input into the FLR_FSM included in the secondary Die 12 to generate a second reset signal. That is, the FLR_FSM can be reused for both the soft reset with a built-in handshake mechanism and the linkage reset caused by a partial functional module reset, eliminating the need to set up separate FSMs for the soft reset with a built-in handshake mechanism and the linkage reset caused by a partial functional module reset. This simplifies the hardware structure of the Die and reduces the manufacturing cost and power consumption of the Die.

[0093] In one possible implementation, the timing diagrams for the iFLR corresponding to the soft reset with the protocol's built-in handshake mechanism and the linkage reset caused by the reset of some functional modules are different. Figure 4 The timing diagram of iFLR is shown when the target reset request is a soft reset with the built-in handshake mechanism of the protocol (taking perst_n as an example). Figure 5 The timing diagram of iFLR is shown when the target reset request is a linkage reset caused by a sub-functional module reset (taking FLR as an example).

[0094] like Figure 4 As shown, `perst_n` triggers the virtual functional level reset state machine to send `FLR_ACTIVE` to the master Die and slave Die's `FLR_FSM`. The `FLR_FSM` then triggers `iFLR_req` to each destination module (the functional module to be reset) based on `FLR_ACTIVE`. After completing the traffic drain task for each destination module and ensuring the reset domain boundary position returns to its initial state, the `FLR_FSM` returns `iFLR_done`. The slave Die's `FLR_FSM` collects the slave Die's `iFLR_done` and returns `FLR_DONE` to the master Die's `FLR_FSM`. The master Die's `FLR_FSM` initiates a `pf reset` assertion to both the master and slave Dies. After waiting for some time, the master Die removes the `iFLR_req`. The slave Die, upon receiving the `pf_rstb` assertion from the master Die, not only performs a direct reset but also sends it to the slave Die's `FLR_FSM` as `iFLR_done`. The slave Die also waits for a period before removing the `iFLR_req`. The destination modules of the master die and slave die can cancel iFLR_done, and then after a certain assertion time, FLR_FSM will return to the initial state, and the master die cancels pf_rstb.

[0095] like Figure 5As shown, after the PCIe host configures the Device Control Register (iFLR) via a configuration write request (CFGWr request), PCIe sends an FLR_ACTIVE message to the FLR_FSM of both the master and slave dies. The FLR_FSM triggers an iFLR_req message to each destination module (module with reset functionality) based on the FLR_ACTIVE message. Each destination module completes its traffic drain task and ensures the reset domain boundary position returns to its initial state before returning an iFLR_done message. The slave dies' FLR_FSM collects the iFLR_done messages from the slave dies and returns an FLR_DONE message to the master dies' FLR_FSM. The master dies' FLR_FSM then initiates a PF reset assertion to both the master and slave dies. After a short wait, the master die will remove the iFLR_req. The slave die, upon receiving the pf_rstb assertion from the master die, will not only reset directly but also send it to the slave die's FLR_FSM as iFLR_done. The slave die will also wait for a period before removing the iFLR_req. The destination modules of both the master and slave dies can then cancel iFLR_done. After a certain activation (assertion) period, the FLR_FSM will return to its initial state, and the master die will cancel pf_rstb. The master die will then return FLR_DONE to the PCIe, and normal operation will resume after a short time.

[0096] In one possible implementation, Figure 6 and Figure 7 The timing diagrams for resets under other soft reset / protection mechanisms and watchdog reset / debugging mechanisms are shown. For resets under other soft reset / protection mechanisms and watchdog reset / debugging mechanisms, before reset activation (assertion), the SCU initiates a reset isolation handshake with the smallest granularity. After the handshake ends, reset activation is completed, and the current reset is revoked after a certain activation (assertion) time. The reset target module can then revoke the iso_done signal based on the req or rstb signal. Figure 6 The timing diagram shown illustrates the cancellation of the iso_done signal based on the rstb signal. Figure 7 The timing diagram shown illustrates the cancellation of the iso_done signal based on the req signal.

[0097] Reset control device

[0098] Figure 8A schematic diagram of a reset control device 800 according to an embodiment of the present disclosure is shown. The reset control device 800 is applied to a die including a chip, the chip including a master die and at least one slave die. Figure 8 As shown, the reset control device 800 includes:

[0099] The receiving unit 801 is used to receive a target reset request sent by the target reset source among multiple reset sources;

[0100] Processing unit 802 is used to determine the target reset control logic and target reset domain corresponding to the target reset request;

[0101] The sending unit 803 is configured to send a reset signal to a reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, wherein the object includes at least some functional modules in the main die and / or at least some functional modules in the slave die.

[0102] In this embodiment, multiple reset sources can send reset requests. After receiving a target reset request from a target reset source among the multiple reset sources, the receiving unit 801 determines the target reset control logic and target reset domain corresponding to the target reset request. Then, the sending unit 803 can send a reset request to the reset object included in the target reset domain according to the target reset control logic, causing the reset object to perform a reset action. The reset object may include at least some functional modules in the master die and / or slave die. Since reset requests from multiple reset sources can be received, and the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes some or all functional modules in the master die and / or slave die, the reset requirements of multiple types, multiple levels, and multiple die collaboration in a multi-die system can be met, ensuring correct reset and thus ensuring the normal temperature and function of the multi-die system.

[0103] In one possible implementation, the processing unit 802 is also responsible for handling the interface isolation reset of this die and coordinating with the main die to control isolation and reset. The processing unit 802 is responsible for processing and controlling reset requests, such as reasonably reusing isolation and reset control logic according to reset requests, as well as controlling isolation and interface protection.

[0104] It should be noted that the reset control device in this embodiment is used to implement the reset control method in the aforementioned method embodiment and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0105] electronic devices

[0106] Figure 9This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Specific embodiments of this disclosure do not limit the specific implementation of the electronic device. Figure 9 As shown, the electronic device may include: a processor 902, a communications interface 904, a memory 906, and a communications bus 908. Wherein:

[0107] The processor 902, communication interface 904, and memory 906 communicate with each other via communication bus 908.

[0108] Communication interface 904 is used to communicate with other electronic devices or servers.

[0109] The processor 902 is used to execute program 910, which can specifically execute the relevant steps in any of the aforementioned reset control method embodiments.

[0110] Specifically, program 910 may include program code that includes computer operation instructions.

[0111] The processor 902 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of this disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0112] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects of microcontrollers and FPGA chips, specifically in areas such as IoT security, industrial control, mobile phones, and personal computers. Because its design considers small size, speed, and low power consumption, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. With the rise of AIoT (Artificial Intelligence of Things), the RISC-V instruction set architecture is receiving increasing attention and support and is expected to become the next generation of widely used CPU architecture.

[0113] The computer operation instructions in this embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 902 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the reset control method in the above embodiments.

[0114] Memory 906 is used to store program 910. Memory 906 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0115] Specifically, program 910 can be used to cause processor 902 to execute the reset control method in any of the foregoing embodiments.

[0116] The specific implementation of each step in program 910 can be found in the corresponding steps and units described in any of the aforementioned reset control method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0117] In the electronic device of this disclosure, multiple reset sources can send reset requests. After receiving a target reset request from a target reset source among the multiple reset sources, the target reset control logic and target reset domain corresponding to the target reset request are determined. Then, a reset request can be sent to the reset object included in the target reset domain according to the target reset control logic, causing the reset object to perform a reset action. The reset object may include at least some functional modules in the master die and / or slave die. Since reset requests from multiple reset sources can be received, and the corresponding reset control logic and reset domain are determined based on the received reset requests, and the reset domain includes some or all functional modules in the master die and / or slave die, the reset requirements of multiple types, multiple levels, and multiple die collaboration in a multi-die system can be met, ensuring correct reset and thus ensuring the normal temperature and function of the multi-die system.

[0118] Computer storage media

[0119] This disclosure also provides a computer-readable storage medium storing instructions for causing a machine to perform the reset control method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0120] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this disclosure.

[0121] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0122] Computer program products

[0123] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0124] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0125] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.

[0126] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0127] It should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0128] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of the embodiments disclosed herein.

[0129] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.

Claims

1. A reset control method applied to a die comprising a chip, the chip comprising a master die and at least one slave die, the method comprising: Receive a target reset request sent by the target reset source among multiple reset sources; Determine the target reset control logic and target reset domain corresponding to the target reset request; According to the target reset control logic, a reset signal is sent to the reset object included in the target reset domain, so that the reset object performs a reset action. The reset object includes at least some functional modules in the master die and / or at least some functional modules in the slave die. When the target reset request is a linkage reset caused by the reset of a partial functional module, sending a reset signal to the reset object included in the target reset domain includes: inputting the target reset request into the virtual functional level reset state machine included in the main die, so that the virtual functional level reset state machine generates an intermediate reset signal; The intermediate reset signal is input to the functional-level reset state machine included in the master die, causing the functional-level reset state machine included in the master die to generate a first reset signal, and the first reset signal is sent to the reset object located in the target reset domain in the master die; the intermediate reset signal is input to the functional-level reset state machine included in the slave die, causing the functional-level reset state machine included in the slave die to generate a second reset signal, and the second reset signal is sent to the reset object located in the target reset domain in the slave die.

2. The method of claim 1, wherein, The target reset request includes a soft reset with the protocol's built-in handshake mechanism, a custom soft reset, a linkage reset caused by the reset of the aforementioned functional modules, a watchdog reset under the protection mechanism, or a reset under the debugging mechanism.

3. The method according to claim 1, wherein, The target reset control logic for determining the target reset request includes: The target reset control logic corresponding to the target reset request is determined from a plurality of alternative reset control logics, wherein at least some of the alternative reset control logics correspond to reset requests from a plurality of reset sources, and different alternative reset control logics correspond to reset requests from different reset sources.

4. The method according to claim 1, wherein when the target reset request is a non-global reset request, before sending a reset signal to the reset object included in the target reset domain, the method further comprises: An isolation signal is sent to at least a portion of the reset objects included in the target reset domain, the isolation signal being used to return the signals of the master die and the slave die located at the boundary of the target reset domain to their initial state.

5. The method according to claim 1, wherein, Before sending a reset signal to the reset objects included in the target reset domain, the method further includes: sending a reset activation protection signal to at least a portion of the reset objects included in the target reset domain, wherein the reset activation protection signal is used to ensure that unreset functional modules are not affected by reset functional modules when the reset objects included in the target reset domain are asynchronously reset activated; After sending a reset signal to the reset objects included in the target reset domain, the method further includes: sending a reset release protection signal to at least a portion of the reset objects included in the target reset domain, the reset release protection signal being used to prevent reset residual data from being input to the de-reset reset objects; and sending a de-reset signal to the reset objects included in the target reset domain according to the target reset control logic.

6. The method according to claim 4, wherein, When the reset object includes at least some functional modules from at least two dies, sending a reset signal to the reset object included in the target reset domain includes: The master die acquires a master die isolation completion signal and a slave die isolation completion signal. The master die isolation completion signal is used to indicate that the signal in the master die located at the boundary of the target reset domain returns to its initial state. The slave die isolation completion signal is used to indicate that the signal in the slave die located at the boundary of the target reset domain returns to its initial state. After acquiring the master die isolation completion signal and the slave die isolation completion signal, the master die sends a first reset signal to the reset object located in the target reset domain in the master die, and sends a second reset signal to the slave die, so that the slave die controls the reset object located in the target reset domain to reset according to the second reset signal.

7. The method according to claim 6, wherein, The second reset signal contains less information than the first reset signal.

8. The method according to claim 2, wherein, When the target reset source is a soft reset with the built-in handshake mechanism of the protocol, sending a reset signal to the reset object included in the target reset domain includes: The target reset request is input into the functional-level reset state machine included in the main die, causing the functional-level reset state machine included in the main die to generate a first reset signal, and the first reset signal is sent to the reset object located in the target reset domain in the main die; The target reset request is input into the functional level reset state machine included in the slave die, causing the functional level reset state machine included in the slave die to generate a second reset signal, and the second reset signal is sent to the reset object located in the target reset domain in the slave die.

9. A reset control device applied to a die comprising a chip, the chip comprising a master die and at least one slave die, the device comprising: The receiving unit is used to receive a target reset request sent by the target reset source among multiple reset sources; The processing unit is used to determine the target reset control logic and target reset domain corresponding to the target reset request; The sending unit is configured to send a reset signal to the reset object included in the target reset domain according to the target reset control logic, so that the reset object performs a reset action, wherein the reset object includes at least some functional modules in the master die and / or at least some functional modules in the slave die; The sending unit is configured to, when the target reset request is a linkage reset caused by a partial functional module reset, input the target reset request into the virtual functional level reset state machine included in the main die, causing the virtual functional level reset state machine to generate an intermediate reset signal; input the intermediate reset signal into the functional level reset state machine included in the main die, causing the functional level reset state machine included in the main die to generate a first reset signal, and send the first reset signal to the reset object located in the target reset domain in the main die; input the intermediate reset signal into the functional level reset state machine included in the slave die, causing the functional level reset state machine included in the slave die to generate a second reset signal, and send the second reset signal to the reset object located in the target reset domain in the slave die.

10. An electronic device, comprising: The processor, memory, communication interface, and communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to any one of the methods in claims 1-8.

11. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method of any one of claims 1-8.

12. A computer program product comprising computer instructions that instruct a computing device to perform the method of any one of claims 1-8.

Images