In-memory multiply-accumulate calculation circuit in hybrid coding format and design method thereof

Abstract

The invention discloses an in-memory multiply-accumulate calculation circuit in a hybrid coding format and a design method thereof. The in-memory multiply-accumulate calculation circuit is used for designing an in-memory calculation circuit with a lower flipping rate. The input data of the circuit are coded by complement codes, and the weight is coded by primitive codes. The circuit comprises an input processing module, a multiplication circuit, a multi-channel adder tree and a result compensation circuit, wherein the input processing module is used for carrying out bitwise negation operation on complement coded input data and original code coded weight sign bits; the input processed by the input processing module and the weight of the original code are used for calculating a product result through a multiplication circuit; the multi-channel adder tree accumulates a plurality of product results; and the result compensation circuit is used for correcting and compensating the product accumulation result and outputting a final result. According to the invention, the sparsity of the bit level of weight storage is improved, a calculation circuit is designed for the hybrid coding format, and the circuit area is saved while the circuit has lower dynamic power consumption.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of application specific integrated circuit design, and particularly relates to a memory-in computing circuit with mixed encoding format and a design method thereof. BACKGROUND

[0002] With the continuous development of artificial intelligence, the problem of "memory wall" in traditional von Neumann architecture is becoming more and more prominent. To alleviate this problem, "memory-in computing" has been proposed and has been widely studied in recent years. The memory-in computing circuit for neural networks mainly focuses on the multiply-accumulate operation in the network. The conventional scheme uses the complement code for multiply-accumulate operation. However, due to the approximate normal distribution of data in the network, the complement code storage scheme reduces the bit-level sparsity of parameter storage due to the existence of many negative small values. In the digital multiply-accumulate circuit, the bit-level sparsity is closely related to the dynamic power consumption of the circuit. Storing the weights in the original code encoding format will greatly improve the bit-level sparsity of storage and reduce the dynamic power consumption of the digital multiply-accumulate computing circuit. At the same time, the complement code input ensures that the product is still in the complement code format, which is suitable for subsequent multi-channel addition without increasing the input flip rate. SUMMARY

[0003] The application aims to provide a memory-in multiply-accumulate computing circuit with mixed encoding format and a design method thereof to overcome the shortcomings of the existing single encoding format multiply-accumulate scheme. For example, the complement code multiply-accumulate scheme usually has the disadvantages of high dynamic power consumption and large circuit area. The original code multiply-accumulate scheme has a large overhead in multi-channel accumulation after obtaining the original code product.

[0004] To solve the above technical problems, the specific technical solutions of the application are as follows:

[0005] A memory-in multiply-accumulate computing circuit with mixed encoding format, the input data of the circuit adopts complement code encoding, and the weights adopt original code encoding to improve the bit-level sparsity.

[0006] The circuit includes an input processing module, a multiplication circuit, a multi-channel adder tree and a result compensation circuit. The input processing module is used to perform bitwise inversion operation on the input data encoded in the complement code and the sign bit of the weights encoded in the original code. The input processed by the input processing module and the weights encoded in the original code are calculated by the multiplication circuit to obtain the product result. The multi-channel adder tree accumulates multiple product results. The result compensation circuit is used to modify and compensate the product accumulation result and output the final result.

[0007] Further, the weights are stored in a 6T SRAM array.

[0008] Further, the input processing module is composed of a number of XOR gate circuits corresponding to each input data bit width, the XOR gate circuit shares the sign bit of the original code encoded weight as the control input, and each bit of the input data encoded by the complement code is input as the operand, so as to realize the bit-by-bit conditional negation processing.

[0009] Further, the result compensation circuit includes a shift accumulator, a product compensation calculation unit and a preloading module.

[0010] The product compensation calculation unit is used for calculating an online compensation value, the online compensation value is obtained by converting the multiplication accumulation result of the all-1 input in a period and the weight by the product compensation calculation unit; the preloading module is used for selecting the online compensation value or the offline compensation value before each multiplication accumulation operation starts, and loading the compensation value to the shift accumulator; the shift accumulator takes the compensation value as the initial accumulation value, accumulates the calculation results of multiple periods, and finally obtains the correct multiplication accumulation result.

[0011] The application further discloses a design method of the in-memory multiplication accumulation calculation circuit with a mixed encoding format, and the method comprises the following steps:

[0012] Step 1, the input in the complement code format is input in a m-bit serial manner in each period, and the n-bit weight is stored in the original code in the 6T SRAM array; each array calculates the multiplication accumulation result of a n-bit input and a m-bit weight in each period;

[0013] Step 2, the n-bit input input in a serial manner is first processed by the input processing module; in the input processing module, the XOR gate is used to determine whether to perform the negation operation on the input according to the sign bit of the weight in the original code; if the weight is negative, the sign is '1', and the XOR gate will negate the input; otherwise, the sign of the weight is '0', and the XOR gate does not change the input.

[0014] Step 3, the input processed by the input processing module is subjected to the multiplication operation with the weight in the original code without the sign bit; the operation is equivalent to the multiplication of a complement code input and a complement code always positive number; through the multiplication circuit, the product in the complement code format is obtained, and the product is subjected to the accumulation of a channels through the multi-channel adder tree.

[0015] Step 4, in the result compensation circuit, the product compensation calculation unit is responsible for calculating the 'add 1' online compensation result; the preloading module selects the online compensation result or the compensation result calculated offline, and loads the compensation result into the shift accumulator, so as to obtain the final result.

[0016] The application discloses a mixed coding format in-memory multiply-accumulate calculation circuit and a design method thereof, and has the following advantages: based on the parameter distribution characteristics of a neural network, a mixed coding mode is adopted for input and weight, and the sparsity of data is improved. Meanwhile, a corresponding multiply-accumulate calculation circuit is adapted for the calculation method. Compared with a conventional multiply-accumulate calculation circuit, the dynamic power consumption and area overhead of the mixed coding format in-memory multiply-accumulate calculation circuit are significantly reduced, and the efficiency of in-memory calculation and the hardware resource utilization rate are improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A mixed coding format in-memory multiply-accumulate calculation method circuit principle diagram of the application;

[0018] Figure 2 A mixed coding format in-memory multiply-accumulate calculation method flowchart of the application. DETAILED DESCRIPTION

[0019] In order to better understand the purpose, structure and function of the application, the application of a mixed coding format in-memory multiply-accumulate calculation circuit and a design method thereof will be further described in detail below in combination with the drawings.

[0020] As shown in the formula (1), the m-bit complement code input IN is divided into two groups according to the sign of the n-bit weight W, and the input IN corresponding to the negative weight is subjected to the inversion operation. Figure 1 The application discloses a mixed coding format in-memory multiply-accumulate calculation circuit and a design method thereof, and has the following advantages: based on the parameter distribution characteristics of a neural network, a mixed coding mode is adopted for input and weight, and the sparsity of data is improved. Meanwhile, a corresponding multiply-accumulate calculation circuit is adapted for the calculation method. Compared with a conventional multiply-accumulate calculation circuit, the dynamic power consumption and area overhead of the mixed coding format in-memory multiply-accumulate calculation circuit are significantly reduced, and the efficiency of in-memory calculation and the hardware resource utilization rate are improved.

[0021] The input processing module is composed of a number of exclusive OR gate circuits corresponding to the bit width of the input data each time. The exclusive OR gate circuit shares the sign bit of the weight encoded in the original code as the control input, and each bit of the input data encoded in the complement code as the operand input. Through the exclusive OR operation, the input processing module realizes the conditional bit inversion processing based on the sign bit of the weight, as shown in the formula (1)①, the m-bit complement code input IN is divided into two groups according to the sign of the n-bit weight W, and the input IN corresponding to the negative weight is subjected to the inversion operation.

[0022] The result compensation circuit includes an extended shift accumulator, a product compensation calculation unit and a preloading module. The product compensation calculation unit is responsible for calculating the online product compensation value according to the encoding characteristics of the input data and the weights, and is mainly used to compensate the error caused by the incomplete complement "add 1" operation in the input module. The preloading module selects the online compensation value or the offline compensation value to be loaded into the shift accumulator register as the initial accumulation value before each multiply-accumulate operation starts, to ensure the numerical correctness of the final accumulation result. The compensation value is shown as formula (1) ②:

[0023]

[0024] The compensation value ② can be obtained in two ways: (1) Since the weights of the neural network are usually known values, the offline compensation value can be directly calculated from the network weight parameters; (2) An additional cycle of all-1 input can be used to obtain an integer multiple of the online compensation value, which is processed by the product compensation calculation unit to obtain the correct online compensation value. Where {m ' b1} represents m bits of "1", where {m ' b0} represents m bits of "0".

[0025]

[0026] The input processing module works with the result compensation circuit, the former completes the sign adjustment of the input data, and the latter compensates the multiply-accumulate result, which together realizes the in-memory multiply-accumulate calculation of the hybrid encoding format with low dynamic power consumption and accumulation friendly.

[0027] In this embodiment, as shown in Figure 2 , the specific calculation steps of the hybrid encoding in-memory multiply-accumulate calculation are as follows:

[0028] 1. The complement format input is input in 2-bit serial form per cycle, and the 8-bit weight is stored in the original code form in the 6T SRAM array. Each array calculates the multiply-accumulate result of 16 2-bit inputs and 8-bit weights at a time.

[0029] 2. The 2-bit serial input is first processed by the input module. In the input module, an XOR gate is used to determine whether to perform an inversion operation on the input according to the sign bit of the original code weight. If the weight is negative, the sign is "1", and the XOR gate will invert the input. Otherwise, the weight sign is "0", and the XOR gate does not change the input.

[0030] 3. The input processed by the input module is multiplied by the original code weight without the sign bit. This operation is equivalent to a complement input multiplied by a complement which is always positive. The product in the complement format is obtained by the multiplier, and the product is accumulated by the adder in 16 channels.

[0031] 4. In the compensation circuit, the product compensation calculation circuit is used to calculate the online compensation value, and the preload module selects the online compensation value or the offline compensation value to store the "add 1" result calculated in advance into the register of the accumulator, which is used as the initial value to accumulate the result of the serial calculation in each cycle, and finally the correct product-sum result in the complement form is obtained.

[0032] In this embodiment, the input module is composed of 32 (16x2) XOR gates. Each two XOR gates perform corresponding operations on 2-bit input according to the sign bit of the weight. The result compensation circuit is composed of a shift accumulator, a product compensation calculation unit and a preload module. The product compensation calculation unit is used to calculate the online compensation value, and the preload module selects the online compensation value or the offline compensation value to load the compensation value to the shift accumulator, which takes the compensation value as the initial accumulation value to accumulate the calculation result of multiple cycles, and finally the correct product-sum result is obtained.

[0033] It can be understood that the present application is described by some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to these features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, these features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

Claims

1. An in-memory multiply-accumulate computing circuit of hybrid encoding format, characterized by, The input data of the circuit is encoded in the complement code, and the weight is encoded in the original code; The circuit comprises an input processing module, a multiplication circuit, a multi-channel adder tree and a result compensation circuit, the input processing module is configured to perform a bitwise inversion operation on the input data encoded in the complement code and the sign bit of the weight encoded in the original code; the input processed by the input processing module and the weight encoded in the original code are input into the multiplication circuit to obtain a multiplication result; the multi-channel adder tree is configured to accumulate a plurality of multiplication results; The result compensation circuit is configured to modify and compensate the multiplication accumulation result and output a final result.

2. The hybrid encoded format in-memory multiply-accumulate calculation circuit of claim 1, wherein, The weight is stored in a 6T SRAM array.

3. The hybrid encoded format in-memory multiply-accumulate calculation circuit of claim 1, wherein, The input processing module comprises a plurality of XOR gate circuits corresponding to the bit width of the input data, the XOR gate circuits share the sign bit of the weight encoded in the original code as a control input, and each bit of the input data encoded in the complement code is input as an operand to realize the bitwise conditional inversion processing.

4. The hybrid encoded format in-memory multiply-accumulate calculation circuit of claim 1, wherein, The result compensation circuit comprises a shift accumulator, a product compensation calculation unit and a preloading module. The product compensation calculation unit is configured to calculate an online compensation value, and the online compensation value is obtained by converting the multiplication accumulation result of the all-1 input in a period and the weight by the product compensation calculation unit; the preloading module is configured to select the online compensation value or an offline compensation value before each multiplication accumulation operation starts, and load the compensation value into the shift accumulator, and the shift accumulator takes the compensation value as an initial accumulation value to accumulate the calculation results of multiple periods, and finally obtain the correct multiplication accumulation result.

5. A design method of a hybrid encoding format in-memory MAC computation circuit, used for the hybrid encoding format in-memory MAC computation circuit of any one of claims 1-4, characterized in that, The method comprises the following steps: Step 1: the input in the complement code format is input in the form of m-bit serial input per period, and the n-bit weight is stored in the original code in the 6T SRAM array, and each array calculates a multiplication accumulation result of a n-bit input and a m-bit weight per time; Step 2: the n-bit input input in series is first processed by the input processing module, and in the input processing module, an XOR gate is used to determine whether to perform an inversion operation on the input according to the sign bit of the weight in the original code, if the weight is negative and the sign bit is "1", the XOR gate will invert the input, otherwise, the weight sign is "0", and the XOR gate does not change the input; Step 3: the input processed by the input processing module is multiplied by the weight in the original code without the sign bit, which is equivalent to multiplying a complement code input by a complement code that is always positive, and the multiplication result in the complement code format is obtained through the multiplication circuit, and the multiplication result is accumulated through the multi-channel adder tree in a channel; Step 4: in the result compensation circuit, the product compensation calculation unit is responsible for calculating the "add 1" online compensation result, the preloading module selects the online compensation result or the offline compensation result, and loads the compensation result into the shift accumulator to obtain the final result.

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