Data transmission method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses a data transmission method and device, equipment and a storage medium, the method is applied to a first system-on-chip, the first system-on-chip is in communication connection with a second system-on-chip through a high-speed serial computer expansion bus standard PCIe bus, and the method comprises the steps that a target channel corresponding to data to be transmitted is obtained, the target channel is one PCIe channel between the first system-on-chip and the second system-on-chip, the target channel is configured with corresponding channel resources, and the channel resources comprise shared memory resources and direct memory access (DMA) resources; the to-be-transmitted data is sent to the second system on chip through target channel resources of the target channel, the target channel resources are one of shared memory resources and DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information comprises the service type or the data length. The efficiency of cross-chip system data transmission based on the PCIe bus can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of communication, and relate to but are not limited to a data transmission method and device, equipment and storage medium. BACKGROUND

[0002] In the field of communication, a Peripheral Component Interconnect Express (PCIe) bus can be used to connect various components inside a computer, such as a processor, a network device, a memory, and a graphics card. The PCIe bus has the characteristics of serial transmission, full-duplex transmission, and high bandwidth, and can support interaction and data transmission between components.

[0003] In related technologies, when systems interact based on a PCIe bus, data transmission is usually implemented by direct memory access (DMA) transmission or base address register (BAR) resource mapping. However, the two have different indicators in terms of rate and latency, and users need to measure the appropriate way according to actual needs, increasing the cost and complexity of manual work, and there is a problem of low data transmission efficiency. SUMMARY

[0004] Therefore, the data transmission method and device, equipment and storage medium provided by the embodiments of the present application can improve the efficiency of cross-system data transmission based on a PCIe bus. The data transmission method and device, equipment and storage medium provided by the embodiments of the present application are implemented as follows:

[0005] The first aspect of the present application provides a data transmission method, which is applied to a first system on a chip, and the first system on a chip is in communication connection with a second system on a chip through a Peripheral Component Interconnect Express (PCIe) bus, and the method comprises the following steps:

[0006] obtaining target channel corresponding to to-be-transmitted data, wherein the target channel is one of PCIe channels between the first system on a chip and the second system on a chip, the target channel is configured with corresponding channel resources, and the channel resources include shared memory resources and direct memory access (DMA) resources;

[0007] sending the to-be-transmitted data to the second system on a chip through target channel resources of the target channel, wherein the target channel resources are one of the shared memory resources and the DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length.

[0008] According to the data transmission method provided in the embodiment of the present application, the target channel is one of the PCIe channels between the first system on chip and the second system on chip. The target channel is configured with corresponding channel resources. According to the target information such as the service type or the data length of the to-be-transmitted data, the target channel resources matched with the target information are selected to transmit the to-be-transmitted data to the second system on chip, without the need of user selection or resource configuration, thereby simplifying the operation process and improving the efficiency of cross-system data transmission.

[0009] As an optional implementation, in the first aspect of the embodiment of the present application, the target information includes a service type, the service type includes a control type and a data type, and the transmitting the to-be-transmitted data to the second system on chip through the target channel resources of the target channel includes:

[0010] In a case where the service type of the to-be-transmitted data is the control type, the to-be-transmitted data is transmitted to the second system on chip through the shared memory resources of the target channel.

[0011] In a case where the service type of the to-be-transmitted data is the data type, the to-be-transmitted data is transmitted to the second system on chip through the DMA resources of the target channel.

[0012] According to the above technical solution, in a case where the service type is the control type, the data transmission can be realized through the shared memory resources of the target channel, and in a case where the service type is the data type, the data transmission can be realized through the DMA resources of the target channel. In this way, the target channel resources are flexibly selected according to the service type, so that the data transmission requirements in different service scenarios can be met, and the efficiency and adaptability of data transmission are improved.

[0013] As an optional implementation, in the first aspect of the embodiment of the present application, the target information includes a data length, and the transmitting the to-be-transmitted data to the second system on chip through the target channel resources of the target channel includes:

[0014] In a case where the data length of the to-be-transmitted data is less than or equal to a target threshold, the to-be-transmitted data is transmitted to the second system on chip through the shared memory resources of the target channel.

[0015] In a case where the data length of the to-be-transmitted data is greater than the target threshold, the to-be-transmitted data is transmitted to the second system on chip through the DMA resources of the target channel.

[0016] According to the technical solution, according to the data length of the to-be-transmitted data, when the data length is less than or equal to a target threshold, the shared memory resource is used for transmission; and when the data length is greater than the target threshold, the DMA resource is used for transmission. In this way, the transmission mode can be flexibly selected according to the data amount, and the transmission efficiency and the reasonable use of channel resources are considered.

[0017] As an optional implementation, in the first aspect of the embodiment of the application, the shared memory resource includes a target memory block corresponding to the target channel in the shared memory, and the sending of the to-be-transmitted data to the second system-on-chip through the shared memory resource of the target channel includes:

[0018] sending the to-be-transmitted data to the target memory block through the target channel;

[0019] sending a first doorbell signal to the second system-on-chip, so that the second system-on-chip receives the to-be-transmitted data in the target memory block.

[0020] According to the technical solution, the to-be-transmitted data is sent through a specific target memory block in the shared memory corresponding to the target channel, and a first doorbell signal is sent to the second system-on-chip to notify the second system-on-chip to receive data, so as to meet the scenario requirements that the service type of the to-be-transmitted data is a control type, or the data length is less than or equal to a target threshold.

[0021] As an optional implementation, in the first aspect of the embodiment of the application, the DMA resource includes a DMA memory block, and the sending of the to-be-transmitted data to the second system-on-chip through the DMA resource of the target channel includes:

[0022] sending the to-be-transmitted data to the DMA memory block through the target channel;

[0023] sending transmission information to a target memory block corresponding to the target channel in the shared memory, wherein the transmission information includes a destination address and a data length of the to-be-transmitted data, and the destination address is an address of the DMA memory block;

[0024] sending a second doorbell signal to the second system-on-chip, so that the second system-on-chip receives the to-be-transmitted data in the DMA memory block according to the transmission information in the target memory block.

[0025] By implementing the above technical solution, the first system on chip sends the to-be-transmitted data to the DMA memory block through the target channel, and then sends the transmission information containing the DMA memory block address and the data length to the target memory block in the shared memory, and then sends the second doorbell signal to the second system on chip, so as to inform the second system on chip to receive the to-be-transmitted data in the DMA memory block according to the transmission information. The method is suitable for scenarios with large data volume, such as when the service type of the to-be-transmitted data is a data type, or when the data length of the to-be-transmitted data is greater than a target threshold.

[0026] As an optional implementation, in the first aspect of the embodiment of the present application, before the to-be-transmitted data is sent to the DMA memory block through the target channel, the method includes:

[0027] obtaining the destination address stored in the target memory block.

[0028] By implementing the above technical solution, the destination address of the DMA memory block can be sent to the target memory block by the second system on chip in advance, and obtained by the first system on chip. In this way, the first system on chip can accurately send the to-be-transmitted data to the DMA memory block specified by the second system on chip, ensuring the accuracy and reliability of data transmission, and ensuring efficient coordination between the sender and the receiver.

[0029] As an optional implementation, in the first aspect of the embodiment of the present application, the target channel includes a shared channel or a dedicated channel, the shared channel is used to transmit data of multiple processes, and the dedicated channel is used to transmit data of one process. The method of obtaining the target channel corresponding to the to-be-transmitted data includes:

[0030] determining the target channel as the shared channel or the dedicated channel according to the process priority of the target process corresponding to the to-be-transmitted data.

[0031] By implementing the above technical solution, the target channel is determined as the shared channel or the dedicated channel according to the process priority of the target process corresponding to the to-be-transmitted data. In this way, the high-priority process can use the dedicated channel to ensure the efficiency of data transmission, and the low-priority process can transmit data through the shared channel to improve the utilization rate of memory resources.

[0032] The second aspect of the present application provides a data transmission method, which is applied to a second system on chip, the second system on chip is connected with a first system on chip through a high-speed serial computer expansion bus standard (PCIe) bus, and the method includes:

[0033] receive the to-be-transmitted data sent by a target channel resource of a target channel of the first system on chip, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources include shared memory resources and direct memory access (DMA) resources, the target channel resource is one of the shared memory resources and the DMA resources, the target channel resource matches target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length.

[0034] By implementing the above technical solutions, the second system on chip can receive the to-be-transmitted data from the first system on chip, the complexity of establishing a connection between system on chips and resource overhead are reduced, and data transmission efficiency is improved.

[0035] The third aspect of the present application provides a data transmission device, the device is applied to a first system on chip, the first system on chip is connected with a second system on chip through a peripheral component interconnect express (PCIe) bus, and the device comprises:

[0036] a channel obtaining module, configured to obtain a target channel corresponding to to-be-transmitted data, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, and the channel resources include shared memory resources and direct memory access (DMA) resources;

[0037] a data sending module, configured to send the to-be-transmitted data to the second system on chip through a target channel resource of the target channel, wherein the target channel resource is one of the shared memory resources and the DMA resources, the target channel resource matches target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length.

[0038] The fourth aspect of the present application provides a data transmission device, the device is applied to a second system on chip, the second system on chip is connected with a first system on chip through a peripheral component interconnect express (PCIe) bus, and the device comprises:

[0039] The data receiving module is configured to receive to-be-transmitted data sent by a target channel resource of a target channel of the first SoC, wherein the target channel is one of the PCIe channels between the first SoC and the second SoC, the target channel is configured with a corresponding channel resource, the channel resource includes a shared memory resource and a direct memory access (DMA) resource, the target channel resource is one of the shared memory resource and the DMA resource, the target channel resource is matched with target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length.

[0040] The fifth aspect of the present application provides a computer device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements the method of the first aspect or the second aspect of the present application when executing the program.

[0041] The sixth aspect of the present application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method of the first aspect or the second aspect of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0042] The drawings incorporated into the specification and forming a part of the specification, the drawings show the embodiments consistent with the present application, and together with the specification, are used to illustrate the technical solutions of the present application.

[0043] Figure 1 An application scenario diagram of the data transmission method provided by the embodiments of the present application is shown.

[0044] Figure 2 An architecture schematic diagram of the SoC provided by the embodiments of the present application is shown.

[0045] Figure 3 A flowchart of the data transmission method provided by the embodiments of the present application is shown.

[0046] Figure 4 A flowchart of transmitting data through a shared memory resource in the data transmission method provided by the embodiments of the present application is shown.

[0047] Figure 5 A flowchart of transmitting data through a DMA resource in the data transmission method provided by the embodiments of the present application is shown.

[0048] Figure 6 Another flowchart of the data transmission method provided by the embodiments of the present application is shown.

[0049] Figure 7 An illustrative diagram of data transmission between the first SoC and the second SoC is shown.

[0050] Figure 8 Another flow diagram of transmitting data through shared memory resources in the data transmission method provided by the embodiments of the present application is shown in FIG. 6;

[0051] Figure 9 Another flow diagram of transmitting data through DMA resources in the data transmission method provided by the embodiments of the present application is shown in FIG. 7;

[0052] Figure 10 A diagram of implementing DMA transmission in the data transmission method provided by the embodiments of the present application is shown in FIG. 8;

[0053] Figure 11 A diagram of the structure of the data transmission device provided by the embodiments of the present application is shown in FIG. 9;

[0054] Figure 12 Another diagram of the structure of the data transmission device provided by the embodiments of the present application is shown in FIG. 10;

[0055] Figure 13 A diagram of the structure of the computer device provided by the embodiments of the present application is shown in FIG. 11. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the following will further describe the specific technical solutions of the present application with reference to the drawings in the embodiments of the present application. The following embodiments are used to explain the present application, but are not used to limit the scope of the present application.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0058] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0059] It should be noted that the terms "first\second\third" used in the embodiments of the present application are used to distinguish similar or different objects, and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0060] In the field of communication technology, PCIe is a high-speed serial computer expansion bus standard, and the PCIe bus is a bus applying the standard and capable of realizing interaction and data transmission between computer components. Compared with Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP) and Industry Standard Architecture (ISA) type buses, the PCIe bus is favored by users due to its characteristics of serial transmission, full-duplex transmission and high bandwidth.

[0061] In the related art, when computer components and systems interact through the PCIe bus, the transmission of data is usually realized by using the DMA transmission or BAR resource mapping mode. The DMA transmission mode allows part of the hardware or system to read and write memory independently of the Central Processing Unit (CPU), and data transmission can be directly performed between memory and devices without frequent intervention of the CPU, thereby improving data transmission efficiency and reducing CPU load. The BAR resource mapping mode defines the memory address space of the device through the base register to ensure that data can be accurately read and written at the specified location. The two modes differ in rate and latency, and when processing different types of services, the appropriate mode needs to be selected according to actual needs, which increases the problem of lack of unified standard and increases the cost and complexity of manual work, thereby affecting the data transmission efficiency.

[0062] Therefore, the embodiments of the present application provide a data transmission method and device, equipment and storage medium, which can improve the efficiency of data transmission between systems or components based on the PCIe bus.

[0063] The following explains the scene to which the data transmission method provided in the embodiments of the present application is applied and the first system on chip, the second system on chip and the PCIe bus contained in the scene, so as to understand the data transmission method provided in the present application.

[0064] Please refer to Figure 1 , Figure 1 A scene diagram of one application of the data transmission method provided in the embodiments of the present application is shown in FIG. 1. Figure 1 The application scene includes a first system on chip 10, a second system on chip 20 and a PCIe bus 30, and the first system on chip 10 is in communication connection with the second system on chip 20 through the PCIe bus 30.

[0065] A System on Chip (SoC) is an integrated circuit that integrates multiple functional modules into a single chip, which can include one or more processing cores such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a Digital Signal Processor (DSP), a storage unit such as a Random Access Memory (RAM) or a Read-Only Memory (ROM), a communication interface such as WiFi, Bluetooth, or Ethernet, and a peripheral interface, without limitation.

[0066] In the embodiments of the present application, the first SoC 10 is communicatively connected to the second SoC 20 through the PCIe bus 30 to realize data communication between the two SoCs. The first SoC 10 can be a sender or a receiver of data, and correspondingly, the second SoC can be a receiver or a sender of data. In this way, the two SoCs can perform data transmission through the PCIe bus 30 to realize data interaction between systems and meet functional requirements such as data processing and real-time communication.

[0067] It should be noted that the application scenario diagram as shown in Figure 1 is only an example. In actual applications, the PCIe bus 30 can also be connected to more SoCs, such as a third SoC, a fourth SoC, and the like. Each pair of SoCs can realize data transmission through the data communication method provided in the embodiments of the present application to complete real-time communication, data processing, or other tasks, without limitation.

[0068] The following describes a possible system architecture of the SoC in the embodiments of the present application to better understand the data transmission method provided in the present application.

[0069] Please refer to Figure 2 , Figure 2 for a schematic diagram of an architecture of the SoC provided in the embodiments of the present application.

[0070] As Figure 2As shown, the user state layer in the architecture can include a plurality of applications (APPs) and a plurality of SDK toolkits, such as a network SDK, an inter-process communication (IPC) SDK, and the like. The kernel driver layer can include a plurality of clients, each of which can correspond to a different SDK or APP of the user state layer, or can dispatch different controller devices through a virtual bus driver. Each controller device can be a root complex (RC) or an endpoint (EP) corresponding device, for example, an RC corresponding controller device 0, a controller device 1, and an EP corresponding controller device 0, a controller device 1, and the like, which are not limited herein.

[0071] Each controller device can be connected to the physical communication link layer through a channel, and the physical communication link layer interacts with the PCle adapter driver through the PCle adaptation layer API. The PCle adaptation layer API provides an interface for configuring and managing PCle devices, enabling upper layer software to conveniently access and control underlying PCle hardware resources. The PCle adapter driver includes a PCle RC adapter driver and a PCle EP adapter driver, and the PCle controller driver includes a PCle RC controller driver and a PCle EP controller driver, to drive RC and EP devices and realize data transmission on the PCle bus and the plug-and-play function of the devices.

[0072] It should be noted that the RC is the core control hub in PCIe and can be used to manage the enumeration and configuration of other devices on the PCIe bus, control channel configuration, send instructions, and the like. The EP refers to a terminal device on the PCIe bus, which can receive and respond to requests from the RC or other devices, and perform data transmission or task processing according to the requests.

[0073] In some possible embodiments, when the first system on chip and the second system on chip perform data transmission based on the PCIe bus, the first system on chip can be a data sender, and the corresponding second system on chip can be a data receiver; or the first system on chip can also be a data receiver, and the corresponding second system on chip can be a data sender, which are not limited herein.

[0074] For example, when the first system on chip is a data sender and the second system on chip is a data receiver. The first system on chip sends the to-be-transmitted data to the second system on chip, which can be that the RC of the first system on chip sends the to-be-transmitted data to the EP of the second system on chip, or that the EP of the first system on chip sends the to-be-transmitted data to the RC of the second system on chip.

[0075] In the case that the first system on chip is a data receiver and the second system on chip is a data transmitter, the second system on chip transmits the data to be transmitted to the first system on chip. The data to be transmitted can be transmitted from an RC of the second system on chip to an EP of the first system on chip, or from an EP of the second system on chip to an RC of the first system on chip, which is not limited herein.

[0076] In some possible embodiments, the data transmission method can also be applied to an RC or an EP of the target system on chip, so as to transmit the data to be transmitted to the EP or the RC of the target system on chip. That is, the data transmission method can be flexibly applied to data interaction between different components of the system on chip, whether the data is transmitted from the RC to the EP or from the EP to the RC, the data transmission task can be efficiently completed, and the efficiency and reliability of data transmission are improved.

[0077] The data transmission method provided in the present application will be described below with reference to the accompanying drawings, so as to better understand the implementation process of the data transmission method.

[0078] Please refer to Figure 3 , Figure 3 A flowchart of the data transmission method provided in the embodiments of the present application is shown in FIG. 1. The data transmission method can be applied to a first system on chip, as shown in FIG. 1, the method can include the following steps: Figure 3

[0079] S301, obtaining a target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first system on chip and a second system on chip, the target channel is configured with corresponding channel resources, and the channel resources include shared memory resources and direct memory access (DMA) resources.

[0080] In the embodiments of the present application, the first system on chip and the second system on chip are connected in communication through a PCIe bus. For example, in the case that the first system on chip is a data transmitter, the data can be transmitted from an RC of the first system on chip to an EP of the second system on chip, or from an EP of the first system on chip to an RC of the second system on chip, or in other possible ways, which is not limited herein.

[0081] ​The target channel is one of the PCIe channels between the first system on chip and the second system on chip, and is configured with corresponding channel resources. The channel is a logical path for data transmission, which defines the specific way and resources for data to flow between two systems. Each channel is associated with specific resources, which can include but are not limited to shared memory resources and direct DMA resources, to support efficient data transmission. Shared memory resources allow two systems to share specific memory areas to exchange data, while DMA resources allow data to be transmitted directly between memory and devices without the direct involvement of the CPU, improving the efficiency of data transmission. In this way, the channel not only ensures the efficiency of data transmission, but also provides flexibility to adapt to different types or lengths of data transmission requirements.

[0082] In some possible embodiments, multiple PCIe channels can be configured between the first system on chip and the second system on chip, and the target channel can be determined according to the target process corresponding to the data to be transmitted. The target process can be the process corresponding to the sender, or the process corresponding to the receiver, or the processes corresponding to the sender and the receiver respectively. That is, when the first system on chip sends data to be transmitted to the second system on chip, the target channel for transmitting the data to be transmitted can be determined from the multiple PCIe channels according to the target process corresponding to the data to be transmitted, such as the process generating or processing the data to be transmitted in the first system on chip or the process receiving the data to be transmitted in the second system on chip, or according to the above two processes and a preset mapping relationship. The preset mapping relationship includes the mapping relationship between the preset process and the preset channel.

[0083] For example, when process a of the first system on chip transmits data to process b of the second system on chip, the target channel can be determined according to parameters such as the source address and / or destination address of the data to be transmitted. In this way, according to the communication requirements between processes, the appropriate PCIe channel can be dynamically selected for data transmission to ensure the priority transmission of critical processes and improve the overall response speed and reliability of system data transmission.

[0084] In some possible embodiments, in addition to determining the target channel according to the target process corresponding to the data to be transmitted, the target channel can also be determined according to one or more of the data length, data category, and transmission priority of the data to be transmitted, to meet the data transmission requirements in different scenarios. By determining the target channel, the reuse and management of channel resources can be achieved, avoiding resource waste while ensuring the stability and reliability of data transmission.

[0085] Exemplarily, different lengths of data pairs have significant differences in transmission efficiency and resource occupation. For short data packets, channels with lower delay characteristics can be preferentially selected to achieve fast transmission; while for large capacity data, channels with higher bandwidth will be preferred. Data categories are also one of the important factors that may affect the transmission strategy in the data transmission process. For example, real-time data (such as video stream, audio stream) has higher requirements for real-time performance and bandwidth of transmission, and usually needs to allocate dedicated high-speed channels to ensure smooth transmission; while non-real-time data (such as file transmission, batch data processing) can select other relatively lower priority channels according to actual conditions, thereby improving the overall utilization rate of channel resources. In addition, transmission priority can also be one of the bases for determining the target channel. Critical business data or data with extremely high time efficiency requirements will be assigned higher priority to guarantee the use right of the transmission channel of these data. By determining the target channel by one or more of the above factors, different scenarios of data transmission requirements can be more flexibly coped with, and the performance and reliability of data transmission can be improved.

[0086] In some possible embodiments, the shared memory resource allows different processes or systems to share the same memory region, thereby realizing fast data exchange. Between the first system on chip and the second system on chip, the shared memory resource can include a memory block of the first system on chip or the second system on chip, and the processes can access the memory block through mapping, so as to be suitable for a multi-process cooperation scenario in which data needs to be frequently exchanged between processes, for example, in real-time data processing or distributed computing. The access of the shared memory resource is usually managed by an operating system to ensure the consistency of data and the security of access.

[0087] In some possible embodiments, the DMA resource allows data to be directly transmitted between the memory and the device without the CPU directly participating in the data transfer, which is suitable for large data volume transmission, such as image processing, large-scale data acquisition and the like. The DMA transmission can significantly reduce the load of the CPU and improve the overall performance of the system. Between the first system on chip and the second system on chip, the DMA resource can include a DMA memory block and be managed by a DMA controller to realize efficient data transmission.

[0088] In some possible embodiments, an interrupt refers to a mechanism in a computer system that suspends a currently executing program when a specific event occurs (such as completion of data transmission, occurrence of an error, or a request for service from an external device), and executes a corresponding interrupt processing program instead. The interrupt resource can include various interrupt functions related to data transmission and channel management. The interrupt processing code can be stored in a memory block corresponding to the target channel, and a corresponding interrupt triggering condition can be set, so that the system can respond and process in a timely manner when data transmission is completed or an abnormal situation occurs. This approach can improve the reliability and real-time performance of data transmission, and ensure effective monitoring and management of data during transmission.

[0089] S302, sending, to the second system on chip, the to-be-transmitted data through a target channel resource of the target channel, wherein the target channel resource is one of a shared memory resource and a DMA resource, and the target channel resource matches target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length.

[0090] In the embodiments of the present application, the target channel resource matches the target information corresponding to the to-be-transmitted data, so as to select the target channel resource and ensure the efficiency and applicability of data transmission.

[0091] In some possible embodiments, the target information includes the service type, and the service type includes a control type and a data type. The sending, to the second system on chip, of the to-be-transmitted data through the target channel resource of the target channel includes the following steps.

[0092] In a case where the service type of the to-be-transmitted data is the control type, the to-be-transmitted data is sent to the second system on chip through the shared memory resource of the target channel.

[0093] In a case where the service type of the to-be-transmitted data is the data type, the to-be-transmitted data is sent to the second system on chip through the DMA resource of the target channel.

[0094] It should be noted that the target information includes the service type, and the service type is divided into the control type and the data type. The service type is classified according to the purpose and transmission requirement of the to-be-transmitted data. The control type usually involves coordination, synchronization, or management instructions between devices, and is used to implement system control logic, for example, operations such as starting or stopping a function, adjusting a parameter, and the like. The data type refers to a data set for transmitting service load information, and is used to carry specific data content, for example, data collected by a sensor, information input by a user, and the like. Different data types can correspond to different channel resources of the target channel.

[0095] Exemplarily, in the case that the service type is a control type, the data transmission can be implemented through the shared memory resource of the target channel, allowing fast exchange of control instructions and ensuring real-time response capability of the system. In the case that the service type is a data type, the data transmission can be implemented through the DMA resource of the target channel, so as to reduce the intervention of the CPU and improve the transmission efficiency of large data. In this way, the target channel resource is flexibly selected according to the service type, so as to meet the data transmission requirements in different service scenarios and improve the efficiency and adaptability of data transmission.

[0096] In some possible embodiments, the target information includes a data length, and the to-be-transmitted data is sent to the second system on chip through the target channel resource of the target channel, including:

[0097] In the case that the data length of the to-be-transmitted data is less than or equal to a target threshold, the to-be-transmitted data is sent to the second system on chip through the shared memory resource of the target channel;

[0098] In the case that the data length of the to-be-transmitted data is greater than the target threshold, the to-be-transmitted data is sent to the second system on chip through the DMA resource of the target channel.

[0099] It can be understood that different data lengths of data have different requirements for transmission resources. In the case that the data length is less than or equal to the target threshold, the shared memory resource is used for transmission; and in the case that the data length is greater than the target threshold, the DMA resource is used for transmission. In this way, the transmission mode can be flexibly selected according to the size of the data amount, and the transmission efficiency and reasonable use of channel resources are taken into account. The target threshold can be determined according to the bandwidth of the target channel and the system performance, can be dynamically adjusted according to historical data transmission statistics, or can be pre-set by the user according to the requirements, which is not limited herein.

[0100] In some possible embodiments, the first system on chip sends the to-be-transmitted data to the second system on chip through the shared memory resource of the target channel, which can be understood as that the first system on chip sends the to-be-transmitted data to be transmitted to a memory block region shared by the first system on chip and the second system on chip, so that the second system on chip receives the data.

[0101] In some possible embodiments, the to-be-transmitted data is sent to the second system on chip through the DMA resource of the target channel, which can be understood as that the first system on chip transmits the to-be-transmitted data to a DMA memory block through the DMA resource such as a DMA controller, and the DMA memory block is different from the memory block shared by the two systems and can be a memory region dedicated to the second system on chip, so that the second system on chip receives the data from the DMA memory block.

[0102] The data transmission method provided in the embodiments of the present application is that the target channel is one of the PCIe channels between the first system on chip and the second system on chip. The target channel is configured with corresponding channel resources. According to target information such as a service type or a data length of the to-be-transmitted data, the target channel resources matched with the target information are selected to send the to-be-transmitted data to the second system on chip, without the need of user selection or configuration of resources, thereby simplifying the operation process and improving the efficiency of cross-system data transmission. In addition, the PCIe bus only needs to provide the most basic shared memory and DMA resources to the outside, and the physical communication link layer is independent of the underlying controller driver, and only exposes the controller device object and the communication channel to the outside, which can adapt to different chip platforms and meet different service requirements.

[0103] The way in which the first system on chip sends the to-be-transmitted data to the second system on chip through the shared memory resources of the target channel in the data transmission method will be introduced below with reference to the accompanying drawings, so as to better understand the implementation process of the data transmission method.

[0104] Please refer to Figure 4 , Figure 4 A flowchart of transmitting data through shared memory resources in the data transmission method provided in the embodiments of the present application is shown in the figure. The data transmission method can be applied to the first system on chip, as shown in the figure, and the method can include the following steps: Figure 4

[0105] S401, obtaining a target channel corresponding to to-be-transmitted data.

[0106] It should be noted that the implementation of step S401 is described with reference to the content described in the foregoing step S301, which will not be described here again.

[0107] S402, sending the to-be-transmitted data to a target memory block through the target channel.

[0108] In some possible embodiments, the target communication resources matched with the target information corresponding to the to-be-transmitted data include shared memory resources. The shared memory resources include a target memory block in the shared memory corresponding to the target channel.

[0109] It should be noted that the shared memory is a memory that can be accessed by the first system on chip and the second system on chip, and the physical address thereof can point to the memory in the first system on chip or the second system on chip, for example, the shared memory can be the memory of the EP in the first system on chip or the second system on chip. For example, when the two systems on chip perform data transmission, the shared memory of the EP of the first system on chip and the RC of the second system on chip can be located in the EP of the first system on chip, or the shared memory of the RC of the first system on chip and the EP of the second system on chip can be located in the EP of the second system on chip, so that the first system on chip and the second system on chip can access the shared memory, and data transmission is realized.​

[0110] In some possible embodiments, the shared memory can be divided according to the number of PCIe channels, the bandwidth requirements of each PCIe channel, or the channel priority, and the like, to allocate the memory blocks corresponding to each channel as the data transmission area of the channel. Such a division helps to improve the organization and efficiency of data transmission, ensures that each channel has independent memory space for data operation, and avoids data confusion and conflict.

[0111] It should be noted that the target channel corresponds to the target memory block, and the target memory block is part of the shared memory. The first system on chip can send the data to be transmitted to the target memory block through the target channel. In this way, the second system on chip can also access the target memory block to receive and read the transmitted data, so that the two systems can efficiently and orderly transmit data, fully guaranteeing the stability and reliability of data transmission.

[0112] S403, sending a first doorbell signal to the second system on chip to make the second system on chip receive the data to be transmitted in the target memory block.

[0113] It should be noted that the doorbell signal refers to a signal sent by the first system on chip to the second system on chip through the doorbell mechanism in PCIe. The doorbell is a way to inform a device that there is a new command or data to be processed. The sender sends a doorbell signal to the receiver to inform the receiver that there is a new task or event to be processed. For example, the first doorbell signal sent by the first system on chip can instruct the second system on chip to receive the data to be transmitted from the target memory block.

[0114] In the above technical solution, the data to be transmitted is sent through a specific target memory block in the shared memory corresponding to the target channel, and a first doorbell signal is sent to the second system on chip to inform the second system on chip to receive the data, so as to meet the scenario requirements that the business type of the data to be transmitted is a control type, or the data length is less than or equal to a target threshold.

[0115] The way in which the first system on chip sends the data to be transmitted to the second system on chip through the DMA resource of the target channel in the data transmission method will be introduced below with reference to the accompanying drawings, so as to better understand the implementation process of the data transmission method.

[0116] Please refer to Figure 5 , Figure 5 A flowchart of transmitting data through a DMA resource in the data transmission method provided by the embodiments of the present application is shown in the figure. The data transmission method can be applied to a first system on chip, as shown in Figure 5 The method can include the following steps:

[0117] S501, obtaining a target channel corresponding to the to-be-transmitted data.

[0118] It should be noted that the implementation of step S501 is described with reference to the content described in the foregoing step S301, which will not be described here.

[0119] S502, sending the to-be-transmitted data to a DMA memory block through the target channel.

[0120] In some possible embodiments, the target communication resource matched with the target information corresponding to the to-be-transmitted data includes a DMA resource. The DNA resource includes a DMA memory block.

[0121] It should be noted that the DMA memory block can be a memory block inside the data receiving party. For example, when a first system on chip transmits data to a second system on chip, the DMA memory block can be a memory block of the second system on chip, used to receive the to-be-transmitted data sent by the first system on chip. The DMA memory block can also be a memory block outside the first system on chip and the second system on chip, such as other memory devices connected by a PCIe bus, so that the DMA transmission can adapt to different system architectures and application scenarios, and improve the flexibility and efficiency of data transmission.

[0122] In some possible embodiments, the DMA resource can also include a DMA controller, where the DMA controller is a hardware component used to manage direct memory access operations. It can control the direct transmission of data between memory and peripherals without the direct participation of the CPU. The DMA controller plays a key role in the data transmission process, and it is responsible for initializing, executing and terminating data transmission operations, while monitoring the transmission process to ensure the integrity and accuracy of the data. In this way, the DMA controller significantly improves the efficiency of data transmission, reduces the burden of the CPU, and thus improves the efficiency of data transmission.

[0123] In some possible embodiments, sending the to-be-transmitted data to the DMA memory block through the target channel can be understood as that the first system on chip uses the DMA memory block, the DMA controller and other DMA resources corresponding to the target channel to send the to-be-processed data to the DMA memory block for storage through the DMA transmission.

[0124] S503, sending transmission information to a target memory block corresponding to the target channel in the shared memory, where the transmission information includes a destination address and a data length of the to-be-transmitted data, and the destination address is an address of the DMA memory block.

[0125] In some possible embodiments, after the first SoC sends the to-be-transmitted data to the DMA memory block through the target channel, the first SoC also needs to send transmission information to the target memory block in the shared memory corresponding to the target channel, the transmission information including a destination address of the DMA memory block and a data length of the to-be-transmitted data, so that the second SoC can locate the data position in the DMA memory block according to the transmission information, and implement the receiving process of the to-be-transmitted data based on the data length.

[0126] In some possible embodiments, before the second SoC sends the to-be-transmitted data to the DMA memory block through the target channel, the data transmission method includes the following steps.

[0127] obtaining the destination address stored in the target memory block.

[0128] It should be noted that the DMA memory block can be determined by the second SoC according to a preset rule or requirement, and the destination address of the DMA memory block is sent to the target memory block by the second SoC. In this way, the first SoC can obtain the destination address of the DMA memory block through the target memory block in the shared memory, and send the to-be-transmitted data to the DMA memory block.

[0129] For example, the DMA memory block can be a memory block on the second SoC that is used to receive data by default, and before the first SoC and the second SoC perform data transmission, the second SoC can store the destination address to the target memory block in the shared memory, so as to ensure the accuracy of data transmission.

[0130] S504, sending a second doorbell signal to the second SoC, so that the second SoC receives the to-be-transmitted data in the DMA memory block according to the transmission information in the target memory block.

[0131] In some possible embodiments, the first SoC sends a second doorbell signal to the second SoC, so that the second SoC obtains the transmission information from the target memory block through the second doorbell signal, and receives the to-be-transmitted data from the DMA memory block based on the transmission information.

[0132] In the above technical solution, the to-be-transmitted data is sent through the DMA memory block corresponding to the target channel, and the second doorbell signal is sent to the second SoC to inform the second SoC to receive the to-be-transmitted data in the DMA memory block according to the transmission information, which is suitable for scenarios with large data volume, such as the service type of the to-be-transmitted data is data type, or the data length of the to-be-transmitted data is greater than a target threshold.

[0133] For example, Figure 6 , Figure 6Another flowchart of the data transmission method provided by the embodiments of the present application is shown in FIG. 6, which can be applied to a second system on chip, such as Figure 6 The method can include the following steps:

[0134] S601, receiving data to be transmitted sent by a target channel resource of a target channel of a first system on chip.

[0135] In the embodiments of the present application, the second system on chip is in communication connection with the first system on chip through a high-speed serial computer expansion bus standard (PCIe) bus, the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources include shared memory resources and direct memory access (DMA) resources, the target channel resource is one of the shared memory resources and the DMA resources, the target channel resource is matched with target information corresponding to the data to be transmitted, and the target information includes a service type or a data length.

[0136] It should be noted that the data transmission method can be applied to receiving and sending, the second system on chip can receive the data to be transmitted from the first system on chip, the complexity and resource overhead of establishing a connection between the system on chips are reduced, and the data transmission efficiency is improved.

[0137] In some possible embodiments, the receiving of the data to be transmitted sent by the target channel resource of the target channel of the first system on chip includes:

[0138] receiving a first doorbell signal sent by the first system on chip, wherein the first doorbell signal is used to instruct the second system on chip to receive the data to be transmitted in the target memory block;

[0139] According to the first doorbell signal, the data to be transmitted in the target memory block is received.

[0140] It should be noted that if the second system on chip receives the first doorbell signal, the second system on chip can receive the data to be transmitted in the target memory block, which will not be described here.

[0141] In some possible embodiments, the receiving of the data to be transmitted sent by the target channel resource of the target channel of the first system on chip includes:

[0142] receiving a second doorbell signal sent by the first system on chip, wherein the second doorbell signal is used to instruct the second system on chip to receive the data to be transmitted in the DMA memory block according to transmission information in the target memory block;

[0143] obtaining the transmission information in the target memory block, wherein the transmission information includes a destination address and a data length of the data to be transmitted, and the destination address is an address of the DMA memory block;

[0144] According to the destination address and the data length of the data to be transmitted, the data to be transmitted in the DMA memory block is received.

[0145] It should be noted that if the second system on chip receives the second doorbell signal, the second system on chip can receive the data to be transmitted in the DMA memory block according to the transmission information in the target memory block, which will not be described here.

[0146] In some possible embodiments, before receiving the second doorbell signal sent by the first system on chip, the data transmission method applied to the second system on chip further includes:

[0147] The destination address is sent to the target memory block, wherein the destination address is the address of the DMA memory block, and the target memory block is the memory block corresponding to the target channel in the shared memory.

[0148] It should be noted that the second system on chip sends the destination address to the target memory block, so that the first system on chip can obtain the memory position to which the data should be transmitted, thereby realizing efficient and accurate data transmission.

[0149] Please refer to Figure 7 , Figure 7 is a schematic diagram of data transmission between the first system on chip and the second system on chip. In a possible embodiment, the sender can be a root complex RC (such as the RC in the first system on chip), and the receiver can be an endpoint EP (such as the EP in the second system on chip). The sender can send the data to be transmitted through a shared memory resource or a DMA resource.

[0150] When the sender transmits data using the DMA resource, the receiver can send the destination address of the DMA memory block through the channel, and the sender can send the data to be transmitted into the DMA memory block. For example, the EP of the receiver sends the destination address of the DMA memory block to the target memory block in the shared memory through the corresponding channel, so that the RC of the first system on chip can obtain the target position of data transmission. The RC of the sender sends the data to be transmitted into the DMA memory block through the corresponding channel using the DMA resource, so that the data is directly transmitted from the memory of the sender to the DMA memory block of the receiver, thereby improving the transmission efficiency. After the sender sends data to the DMA memory block, the transmission information such as the data length and the destination address can be sent to the target memory block in the shared memory, so that the receiver can accurately receive and process the data.

[0151] The sender sends the destination address to the target memory block and the sender sends the transmission information to the target memory block can be implemented through different channels or different queues such as sending queues or receiving queues of the same channel, which is not limited here.

[0152] In the technical solution, the second system on chip can receive the data to be transmitted from the first system on chip, complexity and resource consumption of connection establishment between the system on chips are reduced, and data transmission efficiency is improved.

[0153] Please refer to Figure 8 , Figure 8 Another flowchart for transmitting data through a shared memory resource in the data transmission method provided by the embodiments of the present application is shown in FIG. 8. The data transmission method can be applied to a first system on chip, and the method can include the following steps. Figure 8

[0154] S801, obtaining a target channel corresponding to the data to be transmitted.

[0155] In some possible embodiments, before obtaining the target channel corresponding to the data to be transmitted, the data transmission method applied to the first system on chip further includes:

[0156] registering the first system on chip as a sender to the PCIe bus.

[0157] It should be noted that registering the first system on chip as a sender to the PCIe bus can be understood as that the first system on chip sends a registration request to a controller of the PCIe bus through its RC or EP, and indicates that the first system on chip will act as a sender of data to participate in a subsequent data transmission process. The registration process involves a series of configuration operations, which can include but are not limited to allocating system resources (such as memory address space, interrupt request line, etc.), and setting communication parameters, to ensure that the first system on chip can establish an effective communication link with a second system on chip on the PCIe bus. Details are not described herein again. After completing the registration, the first system on chip has the permission and ability to send data through the PCIe bus, and can start data transmission related operations.

[0158] In some possible embodiments, the target channel includes a shared channel or an exclusive channel, the shared channel is used for transmitting data of multiple processes, and the exclusive channel is used for transmitting data of one process. Obtaining the target channel corresponding to the data to be transmitted includes:

[0159] According to a process priority of a target process corresponding to the data to be transmitted, determining whether the target channel is a shared channel or an exclusive channel.

[0160] ​It should be noted that for a shared channel, it allows multiple processes to share the same channel for data transmission, which helps to improve the utilization of the channel and reduce the waste of system resources. Shared channels are suitable for processes that do not have high real-time requirements or have small data volumes. Through shared channels, multiple processes can reuse the same channel resources, thereby reducing the overall resource consumption of the system. Exclusive channels are channels reserved for a single process to ensure that the data transmission of the process will not be disturbed by other processes, and are suitable for processes that have high real-time requirements or large data volumes. Exclusive channels can provide more stable and predictable transmission performance, ensuring that the data of critical processes can be transmitted in a timely and accurate manner.

[0161] In some possible embodiments, the process priority of each process can be pre-set by the system according to factors such as the type of the process, data transmission requirements, and real-time requirements. For example, real-time data processing processes can be assigned a higher priority to ensure that data can be quickly transmitted and processed; while non-real-time batch data processing processes can have a lower priority and can share channel resources. In addition, users can also manually adjust the process priority according to actual needs, which is not limited herein.

[0162] In some possible embodiments, the data transmission method applied to the first system on chip further includes:

[0163] Registering a related callback of the target channel.

[0164] It should be noted that the related callback can include but is not limited to a data transmission completion callback, an error handling callback, a data arrival callback, etc. By registering these callback functions, the first system on chip can automatically execute the corresponding processing logic when the data transmission is completed, an error occurs, or other critical events occur. For example, when the data transmission is successfully completed, the data transmission completion callback can notify the application program that the data has been successfully sent or received; if an error occurs during transmission, the error handling callback can capture and handle the error in a timely manner to ensure the stability of data transmission.

[0165] S802, whether the sending queue of the destination channel is empty.

[0166] In some possible embodiments, the data transmission through the target channel can be implemented through a virtio mechanism (protocol). The virtio provides a virtual queue management mechanism, allowing the first system-on-chip to efficiently monitor and manage the state of the transmission queue (Virtqueue Ring). Through the virtio virtual queue, the first system-on-chip can monitor the number of data packets or the occupied space in the transmission queue in real time. When there is data to be sent in the transmission queue, the virtual queue will be in a non-empty state, triggering the corresponding data transmission operation. This mechanism ensures that the data to be transmitted can be sent through the PCIe bus in time, while avoiding unnecessary resource consumption and delay.

[0167] In some possible embodiments, S803 is implemented when the transmission queue of the target channel is non-empty; and when the transmission queue of the target channel is not non-empty, the first system-on-chip can continue to monitor the state of the transmission queue until the queue is non-empty. For example, the system can detect the change of the queue state through polling or event notification mechanism. Once it is detected that a data packet is added to the transmission queue, the queue becomes non-empty, the system triggers the corresponding operation, such as data transmission or state update. This mechanism ensures the timeliness of data transmission and the efficient operation of the system, while avoiding waste of resources.

[0168] S803, sending the data to be transmitted to the target memory block through the target channel.

[0169] In some possible embodiments, sending the data to be transmitted to the target memory block through the target channel comprises:

[0170] obtaining a first resource descriptor, wherein the first resource descriptor comprises an address of the target memory block;

[0171] copying the data to be transmitted to a continuous memory space corresponding to the target memory block indicated by the first resource descriptor;

[0172] submitting the first resource descriptor to a used descriptor queue corresponding to the target channel.

[0173] It should be noted that through the resource descriptor and queue mechanism, the system can orderly process multiple data transmission requests, ensuring the accuracy and timeliness of data transmission. At the same time, it also helps to optimize the use of system resources, reduce delay and errors in the data transmission process.

[0174] S804, sending a first doorbell signal to the second system-on-chip, so that the second system-on-chip receives the data to be transmitted in the target memory block.

[0175] It should be noted that after receiving the first doorbell signal, the second system on chip can obtain the to-be-transmitted data from the target memory block, return the queue resource to the receiving queue, that is, release the channel resource corresponding to the first resource descriptor, so that subsequent other data transmission tasks can reuse the resource. This ensures the effective recycling of resources and improves the overall efficiency of data transmission.

[0176] S805, whether there is new to-be-transmitted data.

[0177] In some possible embodiments, in the case that there is new to-be-transmitted data in the first system on chip, S802 is implemented to continue transmitting data with the second system on chip, otherwise, the data transmission process is ended.

[0178] In the above technical solution, the virtio mechanism can be used to realize data transmission between system on chips through the shared memory resource of the target channel.

[0179] Please refer to Figure 9 , Figure 9 Another flowchart of a data transmission method provided by the embodiments of the present application for transmitting data through DMA resources, which can be applied to a first system on chip, as shown in Figure 9 , the method can include the following steps:

[0180] S901, obtaining a target channel corresponding to to-be-transmitted data.

[0181] S902, whether the sending queue of the target channel is non-empty.

[0182] In some possible embodiments, in the case that the sending queue of the target channel is non-empty, S903 is implemented, and in the case that the sending queue of the target channel is not non-empty, the first system on chip can continue to monitor the state of the sending queue until the queue is non-empty.

[0183] S903, sending the to-be-transmitted data to a DMA memory block through the target channel.

[0184] In some possible embodiments, sending the to-be-transmitted data to the DMA memory block through the target channel includes:

[0185] obtaining a second resource descriptor, wherein the second resource descriptor includes an address of the target memory block, and the target memory block is a memory block corresponding to the target channel in the shared memory;

[0186] obtaining a destination address stored in the target memory block according to the second resource descriptor, wherein the destination address is an address of the DMA memory block;

[0187] sending the to-be-transmitted data to the DMA memory block.

[0188] Referring to Figure 10 , Figure 10 A schematic diagram of implementing DMA transmission in the data transmission method provided by the embodiments of the present application is shown in FIG. 4. As shown in FIG. 4, in some possible embodiments, the virtqueue component of the virtio mechanism can be used to send the to-be-transmitted data to the DMA memory block through the target channel. Figure 8

[0189] It should be noted that the virtqueue component is a component in the virtio mechanism (protocol), which is a channel for data exchange between the front-end driver and the back-end virtual device, and allows efficient transmission of bulk data in a virtual environment without simulating a traditional physical device interface.

[0190] In some possible embodiments, the target channel can include a sender queue and a receiver queue, and the virtqueue component and the target channel resource of the target channel can be used to send the to-be-transmitted data to the DMA memory block. For example, first, the receiver (e.g., the second system on chip) can prefill the second resource descriptor corresponding to the DMA memory block into the descriptor table; second, the first system on chip can obtain the last index in the used queue (Used ring) through the target channel and the corresponding mapping relationship, obtain the second resource descriptor in the descriptor table, and thus obtain the target address of the DMA memory block; third, the sender, i.e., the first system on chip, can write the index of the second resource descriptor after DMA transmission to the available queue (avail ring) after sending the to-be-transmitted data to the DMA memory block through the DMA resource (which can include the DMA memory block and the DMA controller, etc.) of the target channel, and send the second doorbell signal to the second system on chip to notify the second system on chip to receive the data; fourth, the second system on chip can obtain the address of the DMA memory block and the data length according to the second resource descriptor after DMA transmission obtained through the available queue after receiving the second doorbell signal, and thus receive the to-be-transmitted data; and finally, the second system on chip can write the index of the second resource descriptor back to the used queue to return the idle resource, thereby implementing the DMA transmission of the to-be-transmitted data.

[0191] S904, whether the sending of the to-be-transmitted data to the DMA memory block is successful.

[0192] ​In some possible embodiments, it can be detected whether the first SoC succeeds in sending the to-be-transmitted data to the DMA memory block through the DMA resource of the target channel. In the case where the first SoC succeeds in sending the to-be-transmitted data to the DMA memory block, S905 is implemented; and in the case where the first SoC fails to send the to-be-transmitted data to the DMA memory block, the DMA memory block may be out of space or other faults may occur, and the data transmission process can be ended. For example, after detecting that the first SoC fails to send the to-be-transmitted data to the DMA memory block, the memory block can be recycled, the resource can be reallocated, or other necessary maintenance operations can be performed, which are not limited herein.

[0193] S905, sending the transmission information to the target memory block corresponding to the target channel in the shared memory.

[0194] S906, sending a second doorbell signal to the second SoC, so that the second SoC receives the to-be-transmitted data in the DMA memory block according to the transmission information in the target memory.

[0195] S907, whether there is new to-be-transmitted data.

[0196] In some possible embodiments, in the case where there is new to-be-transmitted data in the first SoC, S902 is implemented, so as to continue the data transmission between the first SoC and the second SoC, otherwise, the data transmission process is ended.

[0197] It should be noted that, in addition to the virtqueue component, a QP queue or other ring buffer queue can also be used to implement the data transmission method based on the target channel, so as to meet the data transmission requirements in different scenarios, which are not limited herein.

[0198] In the above technical solution, the virtio mechanism can be used to implement the data transmission between the SoCs through the DMA resource of the target channel.

[0199] It should be understood that, although each step in the above flowcharts is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps has no strict sequence limitation, and these steps can be executed in other sequences. Moreover, at least part of the steps in the above flowcharts can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or sub-steps or stages of other steps.

[0200] Based on the foregoing embodiments, this application provides a data transmission device, which includes the included modules and the units included in each module, which can be implemented by a processor; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA), etc.

[0201] Please refer to Figure 11 , Figure 11 A schematic diagram of a data transmission device provided in an embodiment of this application is shown below. Figure 11 As shown, the data transmission device is applied to the first system-on-a-chip (SoC), which is connected to the second SoC via a high-speed serial computer expansion bus standard PCIe bus. It includes a channel acquisition module 1101 and a data transmission module 1102, wherein:

[0202] The channel acquisition module 1101 is used to acquire the target channel corresponding to the data to be transmitted. The target channel is one of the PCIe channels between the first on-chip system and the second on-chip system. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources.

[0203] The data transmission module 1102 is used to send data to be transmitted to the second on-chip system through the target channel resource of the target channel. The target channel resource is one of the shared memory resource and DMA resource. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0204] In some possible embodiments, the target information includes a service type, which includes a control type and a data type. The data sending module 1102 is further configured to send the data to be transmitted to the second system on the chip via the shared memory resources of the target channel when the service type of the data to be transmitted is a control type; and to send the data to be transmitted to the second system on the chip via the DMA resources of the target channel when the service type of the data to be transmitted is a data type.

[0205] In some possible embodiments, the target information includes the data length. The data sending module 1102 is also used to send the data to be transmitted to the second system on the chip through the shared memory resources of the target channel when the data length of the data to be transmitted is less than or equal to the target threshold; and to send the data to be transmitted to the second system on the chip through the DMA resources of the target channel when the data length of the data to be transmitted is greater than the target threshold.

[0206] In some possible embodiments, the shared memory resource includes a target memory block in the shared memory corresponding to the target channel. The data transmission module 1102 is also used to send data to be transmitted to the target memory block through the target channel; and to send a first doorbell signal to the second system on the chip so that the second system on the chip can receive the data to be transmitted in the target memory block.

[0207] In some possible embodiments, the DMA resource includes a DMA memory block. The data transmission module 1102 is further configured to send data to be transmitted to the DMA memory block via a target channel; send transmission information to the target memory block in shared memory corresponding to the target channel, wherein the transmission information includes a destination address and the data length of the data to be transmitted, and the destination address is the address of the DMA memory block; and send a second doorbell signal to the second system on-chip so that the second system on-chip receives the data to be transmitted in the DMA memory block according to the transmission information in the target memory block.

[0208] In some possible embodiments, where the destination address is sent to the target memory block by the second on-chip system, the data sending module 1102 is further configured to: obtain the destination address stored in the target memory block.

[0209] In some possible embodiments, the target channel includes a shared channel or a dedicated channel. The shared channel is used to transmit data from multiple processes, and the dedicated channel is used to transmit data from one process. The channel acquisition module 1101 is also used to determine whether the target channel is a shared channel or a dedicated channel based on the process priority of the target process corresponding to the data to be transmitted.

[0210] Please refer to Figure 12 , Figure 12 Another schematic diagram of the data transmission device provided in the embodiments of this application is shown below. Figure 12 As shown, the data transmission device is applied to the second system-on-a-chip (SoC), which is connected to the first SoC via a high-speed serial computer expansion bus standard PCIe bus. It includes a data receiving module 1201, wherein:

[0211] The data receiving module 1201 is used to receive the data to be transmitted sent by the first system on-chip through the target channel resources of the target channel. The target channel is one of the PCIe channels between the first system on-chip and the second system on-chip. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources. The target channel resources are one of the shared memory resources and DMA resources. The target channel resources are matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0212] The description of the above device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0213] It should be noted that the division of the data transmission device into modules shown in the embodiments of the present application is illustrative, and is only a logical functional division. In actual implementation, there can be another division manner. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or can be physically separated, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of a software functional unit. It can also be realized in the form of a combination of software and hardware. Figure 11 Figure 12 It should be noted that if the above method is realized in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing an electronic device to execute all or part of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read only memory (ROM), a magnetic disk or an optical disk, and various storage program codes. Thus, the embodiments of the present application are not limited to any specific hardware and software combination.

[0214] The embodiments of the present application provide a computer device, which can be a server, and the internal structure diagram thereof can be as shown in FIG. 1. The computer device includes a processor, a memory and a network interface connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program is executed by the processor to implement the above method.

[0215] The embodiments of the present application provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in the method provided in the above embodiments. Figure 13 The embodiments of the present application provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in the method provided in the above embodiments.

[0216] The embodiments of the present application provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in the method provided in the above embodiments.​

[0217] The embodiment of the present application provides a computer program product containing instructions, which, when running on a computer, causes the computer to execute the steps in the method provided by the above method embodiment.

[0218] Those skilled in the art can understand that, Figure 13 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0219] In one embodiment, the data transmission apparatus provided by the present application can be implemented in the form of a computer program, which can run on the computer device as shown in the figure. Figure 13 The memory of the computer device can store various program modules constituting the above apparatus. The computer program constituted by the various program modules causes the processor to execute the steps in the method of various embodiments of the present application described in the specification.

[0220] It should be noted that: the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects to the method embodiments. For technical details of the present application that are not disclosed in the storage medium, storage medium and device embodiments, please refer to the description of the method embodiments of the present application.

[0221] It should be understood that the "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" or "in some embodiments" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of the above processes does not mean the execution order, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The serial number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments. The above description of each embodiment tends to emphasize the differences between each embodiment, and the same or similar parts can be referred to each other. For the sake of brevity, this paper will not repeat here.

[0222] The term "and / or" in this paper is only to describe the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, object A and / or object B, which can represent three cases of existence of object A, existence of object A and object B, and existence of object B.

[0223] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a", "comprising", or "includes a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0224] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described embodiments are merely illustrative, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, such as: multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0225] The modules described above as separate components may, or can not, be physically separate, and the components shown as modules may, or can not, be physical modules; they can be located in one place, or distributed on multiple network units; and some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0226] In addition, all the functional modules in the embodiments of the present application can be integrated in one processing unit, or each module can be a separate unit, or two or more modules can be integrated in one unit; the integrated modules can be realized in the form of hardware or in the form of hardware plus software functional units.

[0227] Those of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the above method embodiments when executed; and the foregoing storage medium includes mobile storage devices, read only memory (ROM), magnetic discs or optical discs, and various storage medium that can store program codes.

[0228] Alternatively, the above-mentioned integrated units of the present application, if realized in the form of software function modules and sold or used as independent products, can also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. The aforementioned storage medium includes: mobile storage devices, ROM, magnetic disks or optical disks and various media capable of storing program codes.

[0229] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments.

[0230] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new product embodiments.

[0231] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method or device embodiments.

[0232] The above is only an implementation of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data transmission method, characterized by, The method is applied to a first system on chip, the first system on chip is connected with a second system on chip through a high-speed serial computer expansion bus standard PCIe bus, and the method comprises the following steps: obtaining a target channel corresponding to the to-be-transmitted data, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, and the channel resources comprise shared memory resources and direct memory access (DMA) resources; sending the to-be-transmitted data to the second system on chip through the target channel resources of the target channel, wherein the target channel resources are one of the shared memory resources and the DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information comprises a service type or a data length.

2. The method of claim 1, wherein, The target information comprises a service type, the service type comprises a control type and a data type, and the step of sending the to-be-transmitted data to the second system on chip through the target channel resources of the target channel comprises the following steps: in the case that the service type of the to-be-transmitted data is the control type, sending the to-be-transmitted data to the second system on chip through the shared memory resources of the target channel; in the case that the service type of the to-be-transmitted data is the data type, sending the to-be-transmitted data to the second system on chip through the DMA resources of the target channel.

3. The method of claim 1, wherein, The target information comprises a data length, and the step of sending the to-be-transmitted data to the second system on chip through the target channel resources of the target channel comprises the following steps: in the case that the data length of the to-be-transmitted data is less than or equal to a target threshold value, sending the to-be-transmitted data to the second system on chip through the shared memory resources of the target channel; in the case that the data length of the to-be-transmitted data is greater than the target threshold value, sending the to-be-transmitted data to the second system on chip through the DMA resources of the target channel.

4. The method according to claim 2 or 3, characterized in that, The shared memory resources comprise a target memory block corresponding to the target channel in the shared memory, and the step of sending the to-be-transmitted data to the second system on chip through the shared memory resources of the target channel comprises the following steps: sending the to-be-transmitted data to the target memory block through the target channel; sending a first doorbell signal to the second system on chip, so that the second system on chip receives the to-be-transmitted data in the target memory block.

5. The method according to claim 2 or 3, characterized in that, The DMA resources comprise a DMA memory block, and the step of sending the to-be-transmitted data to the second system on chip through the DMA resources of the target channel comprises the following steps: sending the to-be-transmitted data to the DMA memory block through the target channel; sending transmission information to the target memory block corresponding to the target channel in the shared memory, wherein the transmission information comprises a destination address and a data length of the to-be-transmitted data, and the destination address is the address of the DMA memory block; sending a second doorbell signal to the second system on chip, so that the second system on chip receives the to-be-transmitted data in the DMA memory block according to the transmission information in the target memory block.

6. The method of claim 5, wherein, The destination address is sent by the second system on chip to the target memory block, and before the to-be-transmitted data is sent to the DMA memory block through the target channel, the method comprises: obtaining the destination address stored in the target memory block.

7. The method of any one of claims 1-3, wherein, The target channel comprises a shared channel or a dedicated channel, the shared channel is used for transmitting data of multiple processes, and the dedicated channel is used for transmitting data of one process, and the target channel corresponding to the to-be-transmitted data comprises: According to the process priority of the target process corresponding to the to-be-transmitted data, it is determined that the target channel is the shared channel or the dedicated channel.

8. A data transmission method, characterized by, The method is applied to a second system on chip, and the second system on chip is connected with a first system on chip through a high-speed serial computer expansion bus standard (PCIe) bus, and the method comprises: receiving to-be-transmitted data sent by a target channel resource of a target channel of the first system on chip, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources comprise shared memory resources and direct memory access (DMA) resources, the target channel resource is one of the shared memory resources and the DMA resources, and the target channel resource is matched with target information corresponding to the to-be-transmitted data, the target information comprises a service type or a data length.

9. A data transmission apparatus, characterized by comprising: The device is applied to a first system on chip, and the first system on chip is connected with a second system on chip through a high-speed serial computer expansion bus standard (PCIe) bus, and the device comprises: a channel obtaining module, configured to obtain a target channel corresponding to to-be-transmitted data, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, and the channel resources comprise shared memory resources and direct memory access (DMA) resources; a data sending module, configured to send the to-be-transmitted data to the second system on chip through a target channel resource of the target channel, wherein the target channel resource is one of the shared memory resources and the DMA resources, and the target channel resource is matched with target information corresponding to the to-be-transmitted data, and the target information comprises a service type or a data length.

10. A data transmission apparatus, characterized by comprising: The device is applied to a second system on chip, and the second system on chip is connected with a first system on chip through a high-speed serial computer expansion bus standard (PCIe) bus, and the device comprises: A data receiving module is configured to receive to-be-transmitted data sent by a target channel resource of a target channel of the first SoC, wherein the target channel is one of the PCIe channels between the first SoC and the second SoC, the target channel is configured with a corresponding channel resource, the channel resource includes a shared memory resource and a direct memory access (DMA) resource, the target channel resource is one of the shared memory resource and the DMA resource, the target channel resource matches target information corresponding to the to-be-transmitted data, and the target information includes a service type or a data length. 11.A computer device, comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the computer device is characterized in that, The processor implements the steps of the method of any one of claims 1-7 or 8 when executing the program.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the method of any one of claims 1-7 or 8.

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