Chip system simulation method, device, equipment, medium and program product

Abstract

The application relates to a chip system simulation method, device, equipment, medium and program product. The chip system comprises a first chip layer and a second chip layer from bottom to top according to a stacking level, and the design completion degree of the first chip layer is greater than or equal to a target value, and the design completion degree of the second chip layer is less than the target value. The method comprises the following steps: acquiring at least one abstract model corresponding to the second chip layer; superimposing the abstract model into design data of the first chip layer, and performing pressure drop electric migration simulation to obtain a simulation result of the first chip layer. The method can be used for simulation without being limited by the completion degree of physical implementation data.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a simulation method, apparatus, device, medium, and program product for a chip system. Background Technology

[0002] The use of 3D-IC (3D integration, which involves vertically stacking multiple layers of chips and using through-silicon vias (TSVs) for interlayer interconnection) packaging technology has revitalized the microchip industry, especially in high-end fields such as central processing units (CPUs), graphics processing units (GPUs), and systems-on-chips (SoCs), avoiding the diminishing returns associated with advancements in ultra-deep submicron process nodes. However, 3D-IC packaging technology is highly complex. Physical implementation teams need to model and simulate voltage drop, timing, power consumption, and thermal effects, as well as capture the interactions between these phenomena. Voltage drop electromigration is a crucial aspect of chip approval, making solutions for joint simulation of voltage drop electromigration across multiple dies (a die is a unit in a silicon wafer that includes the fully designed individual chip as well as the adjacent horizontal and vertical dicing areas, referred to as chips in this application) particularly important.

[0003] However, current voltage drop electromigration analysis techniques require complete physical design data for each chip as input, as well as process files for each chip, to perform overall power-ground network voltage drop electromigration simulation analysis. Without either input file, multi-chip voltage drop electromigration joint simulation is impossible. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for simulating chip systems that are not limited by the physical implementation data completeness, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application includes a simulation method for a chip system, wherein the chip system comprises a first chip layer and a second chip layer from bottom to top according to a stacking hierarchy, and the design completion degree of the first chip layer is greater than or equal to a target value, while the design completion degree of the second chip layer is less than the target value; the method includes:

[0006] Obtain at least one abstract model corresponding to the second chip layer;

[0007] The abstract model is superimposed onto the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer.

[0008] In one embodiment, the abstract model of the second chip layer includes a first electrical model and a physical model; obtaining at least one abstract model corresponding to the second chip layer includes:

[0009] A power consumption analysis of the second chip layer yields the first electrical model corresponding to the second chip layer.

[0010] Based on the layout information and power supply point location information of the second chip layer, the physical model corresponding to the second chip layer is obtained.

[0011] In one embodiment, the lumped first electrical model corresponding to the second chip layer includes the time-to-current profile of the lumped power via pins in each power domain and the time-to-current profile of the lumped via pins to ground.

[0012] In one embodiment, the first electrical model corresponding to the second chip layer further includes at least one of the following: the equivalent resistance of the power supply pin, the equivalent capacitance of the power supply pin, the equivalent resistance of the ground pin, the equivalent capacitance of the ground pin, the power supply voltage, and the operating temperature of the semiconductor device in the second chip layer.

[0013] In one embodiment, obtaining at least one abstract model corresponding to the second chip layer includes:

[0014] In the case where the chip system includes at least two second chip layers, the power consumption information of each second chip layer is superimposed according to the ground terminal and different power domains to obtain a lumped first electrical model, wherein the different layers of the second chip layers are stacked in the chip system.

[0015] In one embodiment, the step of overlaying the abstract model onto the design data of the first chip layer and performing voltage drop electromigration simulation to obtain the simulation results of the first chip layer includes:

[0016] The physical model corresponding to the second chip layer is instantiated into the first physical design information of the first chip layer to obtain the second physical design information.

[0017] Based on the first electrical model and the second physical design information corresponding to the second chip layer, voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer.

[0018] In one embodiment, after overlaying the abstract model onto the design data of the first chip layer and performing voltage drop electromigration simulation to obtain the simulation results of the first chip layer, the process includes:

[0019] If the simulation results of the first chip layer do not meet the design goals, the number and distribution of power vias and ground vias on the first chip layer are adjusted, and the step of obtaining at least one abstract model corresponding to the second chip layer continues until the simulation results of the first chip layer meet the design goals.

[0020] In one embodiment, the method further includes:

[0021] When the design completion of the second chip layer changes and the changed design completion is greater than or equal to the target value, voltage drop electromigration simulation is performed on the target chip layer separately to obtain the simulation results of the target chip layer, wherein the target chip layer is the second chip layer whose changed design completion is greater than or equal to the target value.

[0022] Determine the abstract model of the target chip layer;

[0023] Based on the abstract model of the target chip layer, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation results of the first chip layer.

[0024] The target simulation result of the target chip layer is obtained by superimposing and statistically analyzing the target simulation results of the first chip layer and the target chip layer.

[0025] In one embodiment, the abstract model of the target chip layer includes a second electrical model and a physical model; determining the abstract model of the target chip layer includes:

[0026] Based on the simulation results of the target chip layer, the time-to-current curve of each power supply point in the target chip layer is determined, and the second electrical model corresponding to the target chip layer is determined based on the ground terminal and different power domains.

[0027] Based on the layout information and power supply point location information of the target chip layer, the physical model corresponding to the target chip layer is obtained.

[0028] In one embodiment, the step of performing voltage drop electromigration simulation on the first chip layer based on the abstract model of the target chip layer to obtain the target simulation result of the first chip layer includes:

[0029] The physical model corresponding to the target chip layer is instantiated into the first physical design information of the first chip layer to obtain the third physical design information;

[0030] Based on the second electrical model of the target chip layer and the third physical design information, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation results of the first chip layer.

[0031] In one embodiment, the simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of the first chip layer include the target effective voltage of the first chip layer, the power region voltage drop and ground terminal voltage drop of the through-silicon via contact metal layer region on the first chip layer, and the power electromigration results of the first chip layer.

[0032] The target simulation results of the target chip layer are obtained by superimposing and statistically analyzing the target simulation results based on the first chip layer and the simulation results of the target chip layer, including:

[0033] Based on the target effective voltage on the target chip layer, the target effective voltage on the first chip layer, the power region voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on the first chip layer, and the starting voltage on the first chip layer, the total voltage drop of the target chip layer is obtained.

[0034] The total voltage drop of the target chip layer and the power electromigration results of the target chip layer are used as the target simulation results of the target chip layer.

[0035] In one embodiment, the method further includes:

[0036] If the target simulation results of the first chip layer or the target chip layer do not meet the design target, the number and distribution of power vias and ground vias on the first chip layer and / or the target chip layer are adjusted, and the step of performing voltage drop electromigration simulation on the target chip layer separately to obtain the simulation results of the target chip layer continues until the target simulation results of the first chip layer and the target chip layer meet the design target.

[0037] In one embodiment, the step of performing voltage drop electromigration simulation on the first chip layer based on the abstract model of the target chip layer to obtain the target simulation result of the first chip layer includes:

[0038] In the case where the chip system includes at least two first chip layers, based on the abstract model of the target chip layer, voltage drop electromigration simulation is performed on the first chip layer in the order of the stacking hierarchy from top to bottom to obtain the target simulation results and the abstract model corresponding to each first chip layer.

[0039] In one embodiment, the simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of each first chip layer include the total voltage drop of the first chip layer and the power electromigration results of the first chip layer.

[0040] The generation of the total voltage drop of the target chip layer includes:

[0041] The voltage drop of the target chip layer is obtained based on the target effective voltage of the target chip layer, the starting voltage of the bottom first chip layer, the power area voltage drop and the ground terminal voltage drop of the silicon via contact metal layer region on each first chip layer.

[0042] The generation of the total voltage drop across each of the first chip layers includes:

[0043] When the third chip is not the bottommost first chip layer, the voltage drop of the third chip is obtained based on the starting voltage on the bottommost first chip layer, the target equivalent voltage of the third chip, the power supply voltage drop and the ground voltage drop in the silicon via contact metal layer region on the first chip layer below the third chip.

[0044] When the first chip layer is the bottommost first chip layer, the target voltage drop of the bottommost first chip layer is obtained based on the starting voltage on the bottommost first chip layer and the target effective voltage of the bottommost first chip layer.

[0045] Secondly, this application also includes a chip system simulation device, wherein the chip system comprises a first chip layer and a second chip layer from bottom to top according to the stacking hierarchy, and the design completion degree of the first chip layer is greater than or equal to a target value, and the design completion degree of the second chip layer is less than the target value; the device includes:

[0046] Abstract model determination module, used to obtain at least one abstract model corresponding to the second chip layer;

[0047] The simulation module is used to overlay the abstract model onto the design data of the first chip layer and perform voltage drop electromigration simulation to obtain the simulation results of the first chip layer.

[0048] Thirdly, this application also includes a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0049] Fourthly, this application also includes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method in any of the above embodiments.

[0050] Fifthly, this application also includes a computer program product comprising a computer program that, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0051] The above-mentioned simulation method, apparatus, equipment, medium, and program product for chip systems include a first chip layer and a second chip layer from bottom to top according to the stacking hierarchy. The design completion degree of the first chip layer is greater than or equal to the target value, while the design completion degree of the second chip layer is less than the target value. During simulation, at least one abstract model corresponding to the second chip layer is obtained; the abstract model is superimposed on the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation result of the first chip layer. In this way, simulation can be achieved even when the design completion degree of the second chip layer is less than the target value, without being limited by the completion degree of the physical implementation data. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a traditional 2.5D-IC multi-chip stacking design.

[0054] Figure 2 for Figure 1 Simulation flowchart involving multi-chip stacking;

[0055] Figure 3 This is a schematic diagram of a hybrid bonded 3D-IC stacked structure design in one embodiment;

[0056] Figure 4 This is a schematic diagram of other stacking structures in another embodiment;

[0057] Figure 5 This is a flowchart illustrating a simulation method for a chip system in one embodiment;

[0058] Figure 6 This is a schematic diagram of the first lumped electrical model in one embodiment;

[0059] Figure 7This is a flowchart of the process for confirming the layout scheme of the first chip layer power supply point TSV in the first design phase of one embodiment;

[0060] Figure 8 This is a flowchart illustrating the multi-chip voltage drop electromigration simulation process in the second design phase of one embodiment.

[0061] Figure 9 This is a flowchart of a multi-chip voltage drop electromigration simulation of a two-layer stacked chip system in a second design phase, as shown in one embodiment.

[0062] Figure 10 This is a structural block diagram of a simulation device for a chip system in one embodiment.

[0063] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] Combination Figure 1 As shown, Figure 1 This diagram illustrates a traditional 2.5D-IC multi-chip stacked design, where a chip (die) is a unit on a silicon wafer, comprising the complete individual chip and adjacent horizontal and vertical scribe lines. The multi-chip stacked structure includes a silicon interposer, a memory system-on-a-chip (SoC) layer, and a unified integrated circuit layer. Both the memory system-on-a-chip (MSB) layer and the unified integrated circuit (UIC) layer sequentially connect to the chip pads via the AP layer (adapter pad layer), mBump (a metal bump used for electrical interconnection and stress buffering between different chip layers), AP layer, RDL (Redistribution Layer) for XY plane electrical extension and interconnection, TSV (Through Silicon Via) for vertical (Z-axis) electrical extension and interconnection; 3D TSV refers to a TSV that runs through the entire chip system, connecting upper and lower chip layers), and the bump connection layer BMET (Bump Metallization Layer, a key metallization structure located between the solder bump and the chip / interposer surface in semiconductor packaging), the bump structure, and the silicon interposer to achieve 2.5D interconnection. The MSB layer, UIC layer, and silicon interposer can all be manufactured using different processes.

[0066] Among them, for Figure 1 The simulation flow of the multi-chip stacked design shown can be found in [reference]. Figure 2 As shown, the first step is to obtain the Def file generated after the physical implementation design of each chip. This Def file includes the location of TSV (Through Silicon Via) patterns and the location information of mbump and bump patterns, and then obtains the power ground or signal bump coordinate information. The second step is to obtain the origin coordinate information and orientation setting information for each chip. The third step is to obtain the mBump RLC parameter information of the package and the interconnection components between chips. The fourth step is to create virtual position alignment for multiple chips and their relative coverage areas using the relative coordinates between chips. The fifth step is to extract the nodes of the PG structure for each chip to form the power network node connection circuit for each chip. The sixth step is to connect the nodes and the RLC model circuits of the interconnection components between chips to form the entire power network node connection structure of the 2.5D IC design. Finally, a voltage drop and electromigration co-simulation is performed on the entire network circuit structure.

[0067] Therefore, current multi-chip voltage drop electromigration analysis methods require complete physical design data for each chip as input, as well as process files for each chip, to perform overall power-ground network voltage drop electromigration simulation analysis. Without either input file, multi-chip voltage drop electromigration joint simulation cannot be performed.

[0068] To address the aforementioned technical issues, this application proposes a method that can quickly perform voltage drop and electromigration analysis considering the combined current of multiple chips, even when some design data is incomplete or a chip process document is missing. This method simplifies the design scale and makes simulation memory consumption controllable.

[0069] Specifically, the chip system simulation method provided in this application embodiment can be applied to, for example, Figure 3 The chip stacking design shown. Figure 3 This design presents a hybrid bonding 3D-IC stacked structure. 3D-IC, or 3D integration, involves vertically stacking multiple layers of chips and using through-silicon vias (TSVs) for interlayer interconnection. All chips and passive devices are located above the chip's XY plane. The chips are stacked together, with TSVs passing through the chips above the XY plane and substrate wiring and vias below the XY plane. Hybrid bonding is an integrated circuit packaging technology primarily used to achieve high-density, high-performance interconnects between different chips.

[0070] Figure 3The 3D-IC stacked structure includes two chip layers: a first chip layer 100, a second chip layer 200, and a connection portion connecting the two chip layers. This connection portion can be implemented using a hybrid bonding method or a metal bump method; no specific limitation is made here. Figure 3 This is achieved through a hybrid bonding method. (Combination) Figure 3 The connection portion includes a TSV500, a metal transition layer 300 (HBM layer, Hybrid Bonding Metal), and a hybrid bonding via 400 (HBV). The TSV500 contacts one side of the metal layer 600 of the first chip layer 100, for example, with the TSV landing layer of the first chip layer 100. The TSV500 is connected to the hybrid bonding via 400 through the metal transition layer 300, which connects the metal transition layer 300 to the metal layer of the second chip layer 200. Each chip layer has an independent power domain, which needs to be powered across layers via the TSV500. The power domain is typically distributed within the metal layers of each chip layer. The power supply point 700 can be a metal bump. The power via pins, i.e., the TSVs connecting the external power supply and the internal power domain, provide a ground loop to the ground terminal and appear in pairs with the power via pins.

[0071] It should be noted that this application may only include, as Figure 3 The 3DIC shown includes two-layer chips, but it can also support multi-layer (three or more layers) 3DIC stacking structures. The connection between different chip layers can be achieved through hybrid bonding or mBump bonding. For ease of understanding, combined with... Figure 4 As shown, Figure 4 Several stacking methods are given, where S1 represents the first chip layer directly connected to the package substrate, S2 represents the second chip layer connected to the first chip layer via a connection structure such as a TSV, S3 represents the third chip layer vertically connected to the second chip layer via a connection structure such as a TSV, and so on up to the top Nth chip layer. The number of stacked chip layers N is determined by the height that the package can accommodate. Furthermore, the second chip layer can also consist of multiple chips of different shapes and sizes, and the third chip layer can consist of the same chip connected to the same second chip layer or different chips within the second chip layer.

[0072] One point that needs to be explained is Figure 3 and Figure 4The stacking design shown is for illustrative purposes only and does not limit this application in any way. However, it should be noted that the chip system simulation method of this application corresponds to a chip system that includes a first chip layer and a second chip layer from bottom to top according to the stacking hierarchy. The design completion degree of the first chip layer is greater than or equal to the target value, and the design completion degree of the second chip layer is less than the target value. The number and number of the second chip layer may also include at least one layer. As the design of the chip system is gradually improved, the number and number of the first chip layer may include at least one layer until all chips in the chip system have been designed. In addition, it should be noted that the number of chips in each chip layer includes at least one, which is not specifically limited here.

[0073] In one exemplary embodiment, such as Figure 5 As shown, a simulation method for a chip system is provided, including the following steps S502 to S504. Wherein:

[0074] S502: Obtain at least one abstract model corresponding to the second chip layer.

[0075] The design completion rate refers to the completeness of the design data for each chip in the chip layer. This design data includes necessary simulation conditions, such as the physical design and logic connection information of the chips in the chip layer, the process parameters of each chip, the first electrical and physical models of the logic units and simulation modules, the timing information of the logic circuits, and the necessary simulation time. In this application, if the design data for each chip in the chip layer includes these necessary simulation conditions, the design completion rate of the chip layer is greater than or equal to the target value; otherwise, the design completion rate of the chip layer is lower than the target value. For example, in the early stages of design, some chip layers in the chip system may have low design completion rates, such as the second chip layer, which may have a completion rate lower than the target value. Figure 4 As shown, the second chip layer may include S2 and S3. In other embodiments, the second chip layer may include other numbers or layers, which are not specifically limited here.

[0076] The abstract model of the second chip layer is obtained by transforming and abstracting each second chip layer. This abstract model includes a first electrical model and a physical model. Specifically, obtaining at least one abstract model corresponding to the second chip layer includes: performing power consumption analysis on the second chip layer to obtain the first electrical model corresponding to the second chip layer; and obtaining the physical model corresponding to the second chip layer based on the layout information and power supply point location information of the second chip layer.

[0077] In some optional embodiments, the first electrical model is obtained by power consumption analysis of the second chip layer. The first electrical model corresponding to the second chip layer includes the time-to-current curve of the power via pins in each power domain and the time-to-current curve of the power via pins to ground. In other embodiments, the first electrical model may further include at least one of the following: the equivalent resistance of the power pins, the equivalent capacitance of the power pins, the equivalent resistance of the ground pins, the equivalent capacitance of the ground pins, the power supply voltage, and the operating temperature of the semiconductor devices in the second chip layer, wherein the operating temperature of the semiconductor devices is specifically the operating temperature of the transistors. Figure 6 As shown, Figure 6 The chip system shown includes a first chip layer S1 and a second chip layer comprising three second chips, namely S2-1, S2-2, and S2-3. The power consumption analysis of the three second chips yields time-to-current curves.

[0078] The time-to-current curve for all TSV pins in each power domain can be a triangular or trapezoidal model, or an average current value. The time-to-current curve for all TSV pins to ground can also be a triangular or trapezoidal model, or an average current value; no specific limitations are imposed here.

[0079] The layout information of the second chip layer can include the shape and size information of each second chip in the second chip layer and its relative coordinate relationship with the first chip layer S1. The shape and size information can be represented by the magnitude in the x and y directions. The power supply point location information can be obtained based on the TSV position of the first chip layer. The contact metal layer of the TSV is the metal layer of the power supply point, thereby obtaining the definition, shape and size, and position coordinate information of the metal layer of the power supply point. Finally, based on the layout information of the second chip layer and the power supply point location information, the physical model corresponding to the second chip layer is obtained. First electrical model S504: The abstract model is superimposed on the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer.

[0080] The limitations of the design data for the first chip layer can be found above. In this embodiment, the design data for the first chip layer includes at least physical design and logic connection information. In this application, the abstract models of each second chip layer with a design completion rate lower than the target value are superimposed on the physical design and logic connection information of the first chip layer for voltage drop and electromigration analysis. Through voltage drop and electromigration analysis, engineers can obtain the simulation results of the first chip layer. The simulation results of the first chip layer include the planning scheme of the number and distribution of the power supply point TSVs of the second chip layer from the first chip layer.

[0081] The above-mentioned simulation method for the chip system obtains at least one abstract model corresponding to the second chip layer during simulation; the abstract model is superimposed on the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer. In this way, simulation can be achieved even when the design completion of the second chip layer is less than the target value, without being limited by the completion of the physical implementation data. This allows for power supply network planning and preliminary voltage drop electromigration analysis of multiple chip layers in the early stages of design.

[0082] In one optional embodiment, obtaining at least one abstract model corresponding to the second chip layer includes: when the chip system includes at least two second chip layers, superimposing the power consumption information of each second chip layer according to the ground terminal and different power domains to obtain a lumped first electrical model, wherein the different second chip layers are stacked in the chip system.

[0083] In this embodiment, the chip system includes at least three stacked chip layers. The design completion degree of the first chip layer is greater than or equal to the target value, while the design completion degree of the second and above chip layers is less than the target value. In this case, when determining the lumped first electrical model, the second chip layers with design completion degrees less than the target value need to be stacked according to the ground terminal and different power domains to obtain the lumped first electrical model.

[0084] For example, if a chip system includes a third layer and higher, and the design completion rate of the second layer and higher is less than the target value, then determining the first electrical model includes: superimposing the power consumption information of the third layer and other layers with the power consumption information of the second layer according to the ground terminal and different power domains to form a lumped abstract first electrical model. The VDD1 of the second layer (which can be considered as the first power domain) is superimposed with the VDD1 current curves of the third layer and higher layers; the VDD2 of the second layer (which can be considered as the second power domain, a different power domain from the first power domain) is superimposed with the VDD2 current curves of the third layer and higher layers; and the VSS of the second layer is superimposed with the VSS current curves of the third layer and higher layers.

[0085] The physical model is derived from the analysis of the layout information and power supply point location information of the second chip layer. The limitations of the second chip layer layout information can be found above. This is combined with... Figure 6The diagram illustrates the TSV (Transmission Switch) locations of VDD1, VDD2, and VSS on the first chip layer S1 of the chip system. The physical model includes the shape and size information of each second chip (S2-1, S2-2, S2-3) in the second chip layer, as well as the relative coordinates of each second chip with respect to the first chip layer S1. The power supply point locations for each second chip in the second chip layer can be obtained from the TSV locations on the first chip layer. The contact metal layer of the TSV is the metal layer of the power supply point, thus providing the definition, shape, size, and coordinate information of the power supply point's metal layer. The power supply points are categorized according to different power domains (VDD1 and VDD2) and ground (VSS).

[0086] In the above embodiments, when the design completion of the second chip layer is less than the target value, its corresponding abstract model can be determined, thereby enabling power supply network planning and preliminary voltage drop and electromigration analysis for multiple chips. It is not limited by the physical implementation data completion, nor by process documents, and supports joint simulation between multiple dies and processes in dual-layer stacking. The abstract model iterates quickly and can generate different abstract models based on different power supply design schemes. It supports analysis and TSV number and layout evaluation and optimization when the design completion is less than the target value, simplifies the design scale, and greatly reduces simulation memory requirements.

[0087] In one optional embodiment, an abstract model is superimposed onto the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer. This includes: instantiating the physical model corresponding to the second chip layer into the first physical design information of the first chip layer to obtain the second physical design information; and performing voltage drop electromigration simulation based on the first electrical model and the second physical design information corresponding to the second chip layer to obtain the simulation results of the first chip layer.

[0088] The second physical design data refers to instantiating the physical model corresponding to the second chip layer with a design completion level less than the target value into the first physical design information of the first chip layer, thus creating new physical design data for the first chip layer. Subsequently, voltage drop electromigration simulations are performed based on the first electrical model corresponding to the second chip layer with a design completion level less than the target value and this second physical design data to obtain the simulation results for the first chip layer.

[0089] In one optional embodiment, after overlaying the abstract model onto the design data of the first chip layer and performing voltage drop electromigration simulation to obtain the simulation results of the first chip layer, the process includes: if the simulation results of the first chip layer do not meet the design target, adjusting the number and distribution of power supply vias and ground vias on the first chip layer, and continuing to execute the step of obtaining at least one abstract model corresponding to the second chip layer until the simulation results of the first chip layer meet the design target.

[0090] The design objectives include voltage drop targets and power electromigration result standards. The loop stops only when both voltage drop targets and power electromigration result standards are met; otherwise, the number and distribution of power vias and ground vias on the first chip layer are adjusted, and a new abstract model is regenerated, such as a new physical model. The simulation is then repeated until the design objectives are met. It should be noted that the first electrical model does not need to be re-obtained in this application because the simplified model extracted from the coarse design does not change much.

[0091] For ease of understanding, combined with Figure 7 As shown, Figure 7 This is a flowchart illustrating the process for confirming the TSV (Transmission Siemens VHS) layout scheme for the first chip layer during the first design phase in one embodiment. In this embodiment, the process includes creating a lumped first electrical model for the second chip layer, creating a physical model for the second chip layer, instantiating the physical model of the second chip layer into the first physical design information of the first chip layer to obtain the second physical design information, performing voltage drop electromigration simulation on the first chip layer using the second physical design information and the first electrical model, obtaining simulation results, and then determining whether the devices on the first chip layer meet the voltage drop electromigration criteria, i.e., whether they meet the design objectives. If they do, the simulation ends; otherwise, the number and distribution of power vias and ground vias on the first chip layer are adjusted, i.e., the TSV layout scheme for the first chip layer is adjusted, and the process returns to the step of creating the physical model of the second chip layer until the simulation results meet the design objectives. The initial steps of creating the lumped first electrical model and creating the physical model of the second chip layer can be processed in parallel to improve efficiency. In subsequent iterations, it is not necessary to regenerate the first electrical model; only the physical model needs to be regenerated because the simplified model extraction in a coarse design does not involve significant changes.

[0092] Subsequently, in the second design phase (which follows the first design phase), for example, when the design completion of at least one second chip layer changes, and the changed design completion is greater than or equal to the target value, the second design phase begins. After the TSV layout scheme for powering the first chip layer to the second chip layer stabilizes, multi-chip voltage drop electromigration simulation checks can be performed in the second design phase. Specifically, this is combined with... Figure 8 The above methods also include:

[0093] S902: When the design completion of at least one second chip layer is changed, and the changed design completion is greater than or equal to the target value, voltage drop electromigration simulation is performed on the target chip layer separately to obtain the simulation results of the target chip layer, wherein the target chip layer is the second chip layer whose changed design completion is greater than or equal to the target value.

[0094] In the case where the design completion level of the second chip layer changes and the design completion level of the changed second chip layer is greater than or equal to the target value, that is, at least one second chip layer becomes the first chip layer, for the sake of convenience, the second chip layer whose design completion level is greater than or equal to the target value is called the target chip layer. However, the target chip layer refers to at least one second chip layer whose design completion level has changed. The change in name is only to indicate that its design completion level has changed.

[0095] First, a separate voltage drop and electromigration simulation is performed on the target chip layer to obtain the simulation results. Specifically, the location of the TSV on the first chip layer is taken as the power supply point, and the starting voltage is Vvddideal. Considering the RC circuit model from TSV to mbump, dynamic voltage drop and electromigration simulations are performed on the target chip layer with high design maturity to obtain the simulation results. The simulation results of the target chip layer include the target effective voltage Veffdie2 of the devices on the target chip layer and the power supply electromigration results on the target chip layer. The target effective voltage Veffdie2 of the devices on the target chip layer is the minimum effective voltage on the devices in the dynamic voltage drop simulation, where Veffdie2 = MIN(Vvdd2 - Vvss2).

[0096] S904: Define the abstract model of the target chip layer.

[0097] In one optional embodiment, the abstract model of the target chip layer includes a second electrical model and a physical model; determining the abstract model of the target chip layer includes: determining the time-to-current curve of each power supply point in the target chip layer based on the simulation results of the target chip layer, and determining the second electrical model corresponding to the target chip layer based on the ground terminal and different power domains; obtaining the physical model corresponding to the target chip layer based on the layout information of the target chip layer and the power supply point location information.

[0098] The abstract model of the target chip layer is obtained based on the voltage drop electromigration simulation results of the target chip layer. For the time-to-current curve of each power supply point in the target chip layer, a second electrical model can be generated according to different power domains and ground.

[0099] It should be noted that the accuracy of the current curve in the second electrical model is greater than that in the first electrical model. For example, the first electrical model includes a rough triangular or trapezoidal waveform, while the second electrical model is based on the time current curve at the sampling point. In addition, the first electrical model includes a lumped current curve of a single power source, while the second electrical model includes a set of current curve models for each power source TSV supply point.

[0100] The physical model of the target chip layer is generated based on the layout information and power supply point information of the target chip layer. For the specific generation method, please refer to the generation method of the physical model of the second chip layer above, which will not be repeated here.

[0101] S906: Based on the abstract model of the target chip layer, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation results of the first chip layer.

[0102] S908: Based on the target simulation results of the first chip layer and the simulation results of the target chip layer, the target simulation results of the target chip layer are obtained by superimposing and statistically analyzing them.

[0103] In this embodiment, after obtaining the abstract model of the target chip layer, voltage drop electromigration simulation can be performed on the first chip layer to obtain the target simulation results of the first chip layer, thereby improving the accuracy of the multi-chip voltage drop electromigration simulation results in the second design period.

[0104] In one optional embodiment, voltage drop electromigration simulation is performed on the first chip layer based on the abstract model of the target chip layer to obtain the target simulation result of the first chip layer, including: instantiating the physical model corresponding to the target chip layer into the first physical design information of the first chip layer to obtain the third physical design information; and performing voltage drop electromigration simulation on the first chip layer based on the second electrical model and the third physical design information of the target chip layer to obtain the target simulation result of the first chip layer.

[0105] Specifically, the physical model corresponding to the target chip layer is instantiated into the first physical design information of the first chip layer to obtain the third physical design information. Based on the second electrical model of the target chip layer and the third physical design information, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation result of the first chip layer. The target simulation result of the first chip layer includes the target effective voltage of the first chip layer, the power region voltage drop Vvddtsv1 and the ground terminal voltage drop Vvsstsv1 in the silicon via contact metal layer region on the first chip layer, and the power electromigration result of the first chip layer. The target effective voltage of the first chip layer is the equivalent voltage Veffdie1 of the device on the first die. Veffdie1 is the minimum effective voltage on the device in the dynamic voltage drop simulation, Veffdie1 = MIN(Vvdd1 - Vvss1).

[0106] In some optional embodiments, the target simulation results of the target chip layer are obtained by superimposing and statistically analyzing the target simulation results of the first chip layer, including: obtaining the total voltage drop of the target chip layer based on the target effective voltage on the target chip layer, the target effective voltage on the first chip layer, the power region voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on the first chip layer, and the starting voltage on the first chip layer; and using the total voltage drop of the target chip layer and the power electromigration results of the target chip layer as the target simulation results of the target chip layer.

[0107] The purpose of superposition statistics is to determine the total voltage drop on the target chip layer, thereby determining whether the total voltage drop of the second chip layer meets the voltage drop standard.

[0108] The formula for calculating the total voltage drop of the target chip layer is:

[0109] Vdrop2=Vvddideal-Vvddtsv1+Vvddideal-Veffdie2+Vvsstsv1

[0110] Where Vdrop2 is the total voltage drop of the target chip layer, Vvddideal is the starting voltage on the first chip layer, Vvddtsv1 is the power supply voltage drop in the region where the through-silicon via contacts the metal layer on the first chip layer, Vvsstsv1 is the ground voltage drop in the region where the through-silicon via contacts the metal layer on the first chip layer, and Veffdie2 is the target effective voltage of the device on the target chip layer.

[0111] In one optional embodiment, the method further includes: if the target simulation results of the first chip layer or the target simulation results of the target chip layer do not meet the design target, adjusting the number and distribution of power supply vias and ground vias on the first chip layer and / or the target chip layer, and continuing to perform voltage drop electromigration simulation on the target chip layer separately to obtain the simulation results of the target chip layer, until the target simulation results of the first chip layer and the target simulation results of the target chip layer meet the design target.

[0112] The specific limitations of the design objectives can be found above, and will not be repeated here.

[0113] In this application, the determination of whether to perform cyclic simulation can be based on the target simulation results of the first chip layer or the target chip layer. For example, if at least one of the target simulation results of the first chip layer and the target chip layer does not meet the design target, it is necessary to adjust the number and distribution of power vias and ground vias on the first chip layer and / or the target chip layer. The adjustment method can be based on experience and is not specifically limited here. Then, the step of performing voltage drop electromigration simulation on the target chip layer separately to obtain the simulation results of the target chip layer continues until the target simulation results of the first chip layer and the target chip layer meet the design target.

[0114] The target simulation results of the first chip layer and the target simulation results of the target chip layer meet the design objectives. This includes the voltage drop results of all devices on the first chip layer and the voltage drop results of all devices on the target chip layer meeting the voltage drop criteria, as well as the electromigration results meeting the electromigration criteria.

[0115] For ease of understanding, combined with Figure 9 As shown, Figure 9 This is a flowchart illustrating a multi-chip voltage drop electromigration simulation of a two-layer stacked chip system in the second design phase, as shown in one embodiment. In this embodiment, a voltage drop electromigration simulation is first performed on the target chip layer to obtain the simulation results. Then, based on the simulation results, a second electrical model of the target chip layer is obtained, and a refined physical model of the target chip layer is also obtained. This physical model is instantiated into the first physical design information of the first chip layer to obtain third physical design information. Finally, a voltage drop electromigration simulation is performed on the first chip layer using the refined second electrical model and the third physical design information to obtain the first chip layer's voltage drop electromigration simulation. The target simulation results are used to obtain the voltage drop of the target chip layer based on the target simulation results of the first chip layer and the target chip layer. Then, it is determined whether the devices on the first chip layer and the target chip layer meet the voltage drop electromigration simulation standard. If they do, the simulation ends. Otherwise, the devices and designs that do not meet the standard are adjusted, that is, the number and distribution of power supply vias and ground vias on the first chip layer and / or the target chip layer are adjusted. Then, the step of performing voltage drop electromigration simulation on the target chip layer separately is re-executed to obtain the simulation results of the target chip layer until the devices on the first chip layer and the target chip layer meet the voltage drop electromigration simulation standard.

[0116] In the above embodiments, power supply network planning and preliminary voltage drop and electromigration analysis of multiple chips can be performed in the first design period, and multi-chip voltage drop and electromigration simulation checks can be performed in the second design period.

[0117] In one optional embodiment, voltage drop electromigration simulation is performed on the first chip layer based on the abstract model of the target chip layer to obtain the target simulation result of the first chip layer. This includes: when the chip system includes at least two first chip layers, voltage drop electromigration simulation is performed on the first chip layers sequentially according to the stacking hierarchy from top to bottom based on the abstract model of the target chip layer to obtain the target simulation result and the abstract model corresponding to each first chip layer.

[0118] In this embodiment, the chip system includes at least three stacked chip layers, with at least two layers having a design completion rate greater than or equal to the target value. That is, the chip system includes at least two first chip layers. When the design completion rate of a current chip layer changes, and the changed design completion rate is greater than or equal to the target value, a separate voltage drop electromigration simulation needs to be performed on the current chip layer. Based on the results of the voltage drop electromigration simulation of the current chip layer, a multi-layer chip joint voltage drop electromigration simulation is performed in conjunction with other layers. For consistency, the chip corresponding to the layer where the design completion rate changes and the changed design completion rate is greater than or equal to the target value is referred to as the target chip layer.

[0119] At least two first chip layers are divided into a bottom first chip layer and other first chip layers. The bottom first chip layer is the chip layer whose design completion level is first greater than or equal to the target value. The other first chip layers are chips that are stacked sequentially on the bottom first chip layer. Above each of the other first chip layers is the target chip layer. Above the target chip layer may be other chip layers, which are the second chip layers, i.e., the chip layers whose design completion level is less than the target value.

[0120] When the design completion rate of the target chip layer is greater than or equal to the target value, a separate voltage drop electromigration simulation is performed on the target chip layer to obtain the simulation results. Then, the accurate second electrical model and physical model corresponding to the target chip layer are obtained. Following the top-down stacking order of the chip system, voltage drop electromigration simulations are performed on each first chip layer sequentially to obtain the target simulation results and corresponding abstract models for each first chip layer. Specifically, firstly, voltage drop electromigration simulation is performed based on the accurate second electrical model and physical model corresponding to the target chip layer and the topmost first chip layer to obtain the target simulation results for the topmost first chip layer. Then, based on the target simulation results, the second electrical model and physical model corresponding to the topmost first chip layer are obtained. Next, voltage drop electromigration simulation is performed based on the second electrical model and physical model corresponding to the topmost first chip layer and the second-to-topmost first chip layer to obtain the target simulation results for the second-to-topmost first chip layer. This sequential calculation yields the target simulation results and corresponding abstract models for each first chip layer.

[0121] In one optional embodiment, the simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of each first chip layer include the total voltage drop of the first chip layer and the power electromigration results of the first chip layer.

[0122] The generation of the total voltage drop of the target chip layer includes: the target effective voltage of the target chip layer, the starting voltage of the bottom first chip layer, the power supply voltage drop and the ground voltage drop of the silicon via contact metal layer region on each first chip layer.

[0123] The generation of the total voltage drop of each first chip layer includes: when the third chip is not the bottom first chip layer, the voltage drop of the third chip is obtained based on the starting voltage on the bottom first chip layer, the target equivalent voltage of the third chip, the power supply voltage drop and the ground voltage drop of the silicon via contact metal layer region on the first chip layer below the third chip; when the first chip layer is the bottom first chip layer, the target voltage drop of the bottom first chip layer is obtained based on the starting voltage on the bottom first chip layer and the target effective voltage of the bottom first chip layer.

[0124] The target chip layer is the topmost chip of the chip whose design completion level is greater than or equal to the target value. Therefore, the total voltage drop of the target chip layer is generated based on the power area voltage drop and ground terminal voltage drop of the silicon via contact metal layer region of each chip layer below it, the starting voltage on the bottom first chip layer, and the target equivalent voltage of the target chip layer. For example, the total voltage drop of the target chip layer is obtained based on the target effective voltage of the target chip layer, the starting voltage of the bottom first chip layer, and the power area voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on each first chip layer. For example, assuming the target chip layer is the third layer, the corresponding total voltage drop of the target chip layer is Vdrop3 = Vvddideal - Vvddtsv1 + Vvddideal - Vvddtsv2 + Vvddideal - Veffdie3 + Vvsstsv2 + Vvsstsv1, where Vvddideal is the starting voltage on the bottom first chip layer, Vvddtsv1 is the power supply voltage drop of the first chip layer, Vvsstsv2 is the power supply voltage drop of the second chip layer, Vvsstsv2 is the ground voltage drop of the first chip layer (i.e., ground bounce), Vvsstsv1 is the ground voltage drop of the second chip layer, and Veffdie3 is the target effective voltage of the third chip layer.

[0125] The total voltage drop across each first chip layer is also determined based on the position of the first chip layer. It is based on the target equivalent voltage of the first chip layer, the starting voltage on the bottom first chip layer, and the power supply voltage drop and ground voltage drop in the silicon via contact metal layer region of each first chip layer below the first chip layer. If there are no other chips below the first chip layer, i.e., the bottom first chip layer, then the total voltage drop is the difference between the starting voltage on the bottom first chip layer and the target effective voltage of the bottom first chip layer.

[0126] For ease of understanding, this example uses a three-layer chip system, stacked from top to bottom as the third die, second die, and first die. Assuming the design completion of the third die is greater than or equal to the target value, a voltage drop electromigration simulation is first performed on the third die to obtain its simulation results. These results include the equivalent voltage drop (target effective voltage) of the devices on the third die, Veffdie3. Subsequently, based on the simulation results of the third die, a second electrical model and a physical model of the third die are obtained. These models are then superimposed onto the physical design data of the second die to perform a voltage drop electromigration simulation on the second die, yielding the target simulation results. These results include the voltage on the TSV contact metal layer on the second die, which is the power region voltage drop Vvddtsv2 and the ground terminal voltage drop Vvsstsv2. The equivalent voltage (target effective voltage) of the devices on the second die is Veffdie2. Finally, based on the target simulation results of the second die, the second electrical model and physical model of the second die are obtained. The voltage drop electromigration simulation of the first die is performed to obtain the target simulation results of the first die, including the voltage on the TSV contact metal layer on the first die as the power region voltage drop Vvddtsv1 and the ground terminal voltage drop Vvsstsv1, and the device equivalent voltage (target effective voltage) on the first die as Vdffdie1.

[0127] Therefore, the target voltage drop on each die can be calculated subsequently:

[0128] The target pressure drop on the third die is:

[0129] Vdrop3=Vvddideal-Vvddtsv1+Vvddideal-Vvddtsv2+Vvddideal-Veffdie3+Vvsstsv2+Vvsstsv1.

[0130] The equivalent voltage of the device on the second die is Veffdie2, and the target voltage drop of the second die is:

[0131] Vdrop2=Vvddideal-Vvddtsv1+Vvddideal-Veffdie2+Vvsstsv1.

[0132] The equivalent voltage of the device on the first die is Veffdie1, and the target voltage drop of the first die is:

[0133] Vdrop1 = Vvddideal-Veffdie1.

[0134] Then, based on the target voltage drop and electromigration simulation results on each die, it is determined whether the devices on each die meet the design target. If they do, the simulation ends and continues to wait for the design completion of the next die layer to be greater than or equal to the target value before performing a joint simulation. If they do not meet the target, at least one device on each die needs to be adjusted, and the above simulation process is repeated until it is determined whether the devices on each die meet the design target.

[0135] In the above embodiments, it is not limited by the completeness of physical implementation data, nor by process documents, supports joint simulation between multiple dies and processes in double-layer stacking, has fast abstract model iteration, can generate different abstract models based on different power supply design schemes, supports analysis in the first design phase and evaluation and optimization of the number and layout of TSVs, simplifies the design scale and greatly reduces simulation memory requirements.

[0136] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0137] Based on the same inventive concept, this application also provides a chip system simulation apparatus for implementing the above-described chip system simulation method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip system simulation apparatus embodiments provided below can be found in the limitations of the chip system simulation method described above, and will not be repeated here.

[0138] In one exemplary embodiment, such as Figure 10As shown, a simulation device for a chip system is provided. The chip system includes a first chip layer and a second chip layer from bottom to top according to the stacking hierarchy. The design completion degree of the first chip layer is greater than or equal to the target value, and the design completion degree of the second chip layer is less than the target value. The device includes: an abstract model determination module 1301 and a simulation module 1302, wherein:

[0139] Abstract model determination module 1301 is used to obtain at least one abstract model corresponding to the second chip layer;

[0140] The simulation module 1302 is used to overlay the abstract model onto the design data of the first chip layer and perform voltage drop electromigration simulation to obtain the simulation results of the first chip layer.

[0141] In one optional embodiment, the abstract model of the second chip layer includes a first electrical model and a physical model; the abstract model determination module 1301 is specifically used to perform power consumption analysis on the second chip layer to obtain the lumped first electrical model corresponding to the second chip layer; and to obtain the physical model corresponding to the second chip layer based on the layout information and power supply point location information of the second chip layer.

[0142] In one optional embodiment, the first electrical model corresponding to the second chip layer includes the time-to-current profile of the power via pins in each power domain and the time-to-current profile of the via pins to ground.

[0143] In one optional embodiment, the first electrical model corresponding to the second chip layer further includes at least one of the following: the equivalent resistance of the power supply pin, the equivalent capacitance of the power supply pin, the equivalent resistance of the ground pin, the equivalent capacitance of the ground pin, the power supply voltage, and the operating temperature of the semiconductor device in the second chip layer.

[0144] In one optional embodiment, the abstract model determination module 1301 is specifically used to superimpose the power consumption information of each second chip layer according to the ground terminal and different power domains when the chip system includes at least two second chip layers to obtain a lumped first electrical model, wherein the different second chip layers are stacked in the chip system.

[0145] In one optional embodiment, the simulation module 1302 is specifically used to instantiate the physical model corresponding to the second chip layer into the first physical design information of the first chip layer to obtain the second physical design information; and to perform voltage drop electromigration simulation based on the first electrical model and the second physical design information corresponding to the second chip layer to obtain the simulation results of the first chip layer.

[0146] In one optional embodiment, the simulation module 1302 is specifically used to adjust the number and distribution of power vias and ground vias on the first chip layer when the simulation results of the first chip layer do not meet the design target, and to continue to execute the step of obtaining at least one abstract model corresponding to the second chip layer until the simulation results of the first chip layer meet the design target.

[0147] In one optional embodiment, the simulation module 1302 is specifically used to perform voltage drop electromigration simulation on the target chip layer separately when the design completion of the second chip layer changes and the changed design completion is greater than or equal to the target value, to obtain the simulation result of the target chip layer, wherein the target chip layer is the second chip layer whose changed design completion is greater than or equal to the target value; determine the abstract model of the target chip layer; perform voltage drop electromigration simulation on the first chip layer based on the abstract model of the target chip layer, to obtain the target simulation result of the first chip layer; and perform superposition and statistics based on the target simulation result of the first chip layer and the simulation result of the target chip layer to obtain the target simulation result of the target chip layer.

[0148] In one optional embodiment, the abstract model of the target chip layer includes a second electrical model and a physical model; the simulation module 1302 is specifically used to determine the time-to-current curve of each power supply point in the target chip layer based on the simulation results of the target chip layer, and to determine the second electrical model corresponding to the target chip layer based on the ground terminal and different power domains; and to obtain the physical model corresponding to the target chip layer based on the layout information of the target chip layer and the power supply point location information.

[0149] In one optional embodiment, the simulation module 1302 is specifically used to instantiate the physical model corresponding to the target chip layer into the first physical design information of the first chip layer to obtain the third physical design information; based on the second electrical model of the target chip layer and the third physical design information, to perform voltage drop electromigration simulation on the first chip layer to obtain the target simulation result of the first chip layer.

[0150] In one optional embodiment, the simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of the first chip layer include the target effective voltage of the first chip layer, the power region voltage drop and ground terminal voltage drop of the through-silicon via contact metal layer region on the first chip layer, and the power electromigration results of the first chip layer.

[0151] The simulation module 1302 is specifically used to obtain the total voltage drop of the target chip layer based on the target effective voltage on the target chip layer, the target effective voltage on the first chip layer, the power region voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on the first chip layer, and the starting voltage on the first chip layer; and to use the total voltage drop of the target chip layer and the power electromigration result of the target chip layer as the target simulation result of the target chip layer.

[0152] In one optional embodiment, the simulation module 1302 is specifically used to adjust the number and distribution of power vias and ground vias on the first chip layer and / or the target chip layer when the target simulation result of the first chip layer or the target chip layer does not meet the design target, and to continue to perform voltage drop electromigration simulation on the target chip layer separately to obtain the simulation result of the target chip layer, until the target simulation result of the first chip layer and the target simulation result of the target chip layer meet the design target.

[0153] In one optional embodiment, the simulation module 1302 is specifically used to perform voltage drop electromigration simulation on the first chip layers in the order of stacking hierarchy from top to bottom, based on the abstract model of the target chip layer when the chip system includes at least two first chip layers, so as to obtain the target simulation results and the abstract model corresponding to each first chip layer.

[0154] In one optional embodiment, the simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of each first chip layer include the total voltage drop of the first chip layer and the power electromigration results of the first chip layer; the simulation module 1302 is specifically used to obtain the voltage drop of the target chip layer based on the target effective voltage of the target chip layer, the starting voltage of the bottom first chip layer, the power region voltage drop and ground terminal voltage drop of the through-silicon via contact metal layer region on each first chip layer; when the third chip is not the bottom first chip layer, the voltage drop of the third chip is obtained based on the starting voltage of the bottom first chip layer, the target equivalent voltage of the third chip, the power region voltage drop and ground terminal voltage drop of the through-silicon via contact metal layer region on the first chip layer below the third chip; when the first chip layer is the bottom first chip layer, the target voltage drop of the bottom first chip layer is obtained based on the starting voltage of the bottom first chip layer and the target effective voltage of the bottom first chip layer.

[0155] Each module in the simulation device of the aforementioned chip system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0156] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 11 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a chip system simulation method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0157] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0158] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0159] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0160] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0161] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0163] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A simulation method for a chip system, characterized in that, The chip system comprises a first chip layer and a second chip layer from bottom to top according to the stacking hierarchy, wherein the design completion degree of the first chip layer is greater than or equal to the target value, and the design completion degree of the second chip layer is less than the target value; the method includes: Obtain at least one abstract model corresponding to the second chip layer; The abstract model is superimposed onto the design data of the first chip layer, and voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer. The abstract model of the second chip layer includes a first electrical model and a physical model; obtaining at least one abstract model corresponding to the second chip layer includes: A power consumption analysis of the second chip layer yields the first electrical model corresponding to the second chip layer. Based on the layout information and power supply point location information of the second chip layer, the physical model corresponding to the second chip layer is obtained; The step of overlaying the abstract model onto the design data of the first chip layer and performing voltage drop electromigration simulation to obtain the simulation results of the first chip layer includes: The physical model corresponding to the second chip layer is instantiated into the first physical design information of the first chip layer to obtain the second physical design information. Based on the first electrical model and the second physical design information corresponding to the second chip layer, voltage drop electromigration simulation is performed to obtain the simulation results of the first chip layer.

2. The method according to claim 1, characterized in that, The first electrical model corresponding to the second chip layer includes the time-to-current curve of the power through-silicon via pins in each power domain and the time-to-current curve of the power through-silicon via pins to ground.

3. The method according to claim 2, characterized in that, The first electrical model corresponding to the second chip layer also includes at least one of the following: the equivalent resistance of the power supply pin, the equivalent capacitance of the power supply pin, the equivalent resistance of the ground pin, the equivalent capacitance of the ground pin, the power supply voltage, and the operating temperature of the semiconductor device in the second chip layer.

4. The method according to claim 2, characterized in that, The step of obtaining at least one abstract model corresponding to the second chip layer includes: In the case where the chip system includes at least two second chip layers, the power consumption information of each second chip layer is superimposed according to the ground terminal and different power domains to obtain a lumped first electrical model, wherein the different layers of the second chip layers are stacked in the chip system.

5. The method according to claim 1, characterized in that, After superimposing the abstract model onto the design data of the first chip layer and performing voltage drop electromigration simulation to obtain the simulation results of the first chip layer, the process includes: If the simulation results of the first chip layer do not meet the design goals, the number and distribution of power vias and ground vias on the first chip layer are adjusted, and the step of obtaining at least one abstract model corresponding to the second chip layer continues until the simulation results of the first chip layer meet the design goals.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: When the design completion of the second chip layer changes and the changed design completion is greater than or equal to the target value, voltage drop electromigration simulation is performed on the target chip layer separately to obtain the simulation results of the target chip layer, wherein the target chip layer is the second chip layer whose changed design completion is greater than or equal to the target value. Determine the abstract model of the target chip layer; Based on the abstract model of the target chip layer, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation results of the first chip layer. The target simulation result of the target chip layer is obtained by superimposing and statistically analyzing the target simulation results of the first chip layer and the target chip layer.

7. The method according to claim 6, characterized in that, The abstract model of the target chip layer includes a second electrical model and a physical model; determining the abstract model of the target chip layer includes: Based on the simulation results of the target chip layer, the time-to-current curve of each power supply point in the target chip layer is determined, and the second electrical model corresponding to the target chip layer is determined based on the ground terminal and different power domains. Based on the layout information and power supply point location information of the target chip layer, the physical model corresponding to the target chip layer is obtained.

8. The method according to claim 7, characterized in that, The abstract model based on the target chip layer is used to perform voltage drop electromigration simulation on the first chip layer to obtain the target simulation results of the first chip layer, including: The physical model corresponding to the target chip layer is instantiated into the first physical design information of the first chip layer to obtain the third physical design information; Based on the second electrical model of the target chip layer and the third physical design information, voltage drop electromigration simulation is performed on the first chip layer to obtain the target simulation results of the first chip layer.

9. The method according to claim 8, characterized in that, The simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of the first chip layer include the target effective voltage of the first chip layer, the power region voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on the first chip layer, and the power electromigration results of the first chip layer. The target simulation results of the target chip layer are obtained by superimposing and statistically analyzing the target simulation results based on the first chip layer and the simulation results of the target chip layer, including: Based on the target effective voltage on the target chip layer, the target effective voltage on the first chip layer, the power region voltage drop and ground terminal voltage drop of the silicon via contact metal layer region on the first chip layer, and the starting voltage on the first chip layer, the total voltage drop of the target chip layer is obtained. The total voltage drop of the target chip layer and the power electromigration results of the target chip layer are used as the target simulation results of the target chip layer.

10. The method according to claim 6, characterized in that, The method further includes: If the target simulation results of the first chip layer or the target chip layer do not meet the design target, the number and distribution of power vias and ground vias on the first chip layer and / or the target chip layer are adjusted, and the step of performing voltage drop electromigration simulation on the target chip layer separately to obtain the simulation results of the target chip layer continues until the target simulation results of the first chip layer and the target chip layer meet the design target.

11. The method according to claim 6, characterized in that, The abstract model based on the target chip layer is used to perform voltage drop electromigration simulation on the first chip layer to obtain the target simulation results of the first chip layer, including: In the case where the chip system includes at least two first chip layers, based on the abstract model of the target chip layer, voltage drop electromigration simulation is performed on the first chip layers in the order of the stacking hierarchy from top to bottom to obtain the target simulation results and the abstract model corresponding to each first chip layer.

12. The method according to claim 11, characterized in that, The simulation results of the target chip layer include the target effective voltage of the target chip layer and the power electromigration results of the target chip layer; the target simulation results of each first chip layer include the total voltage drop of the first chip layer and the power electromigration results of the first chip layer. The generation of the total voltage drop of the target chip layer includes: The voltage drop of the target chip layer is obtained based on the target effective voltage of the target chip layer, the starting voltage of the bottom first chip layer, the power area voltage drop and the ground terminal voltage drop of the silicon via contact metal layer region on each first chip layer. The generation of the total voltage drop across each of the first chip layers includes: When the third chip is not the bottommost first chip layer, the voltage drop of the third chip is obtained based on the starting voltage on the bottommost first chip layer, the target equivalent voltage of the third chip, the power supply voltage drop and the ground voltage drop in the silicon via contact metal layer region on the first chip layer below the third chip. When the first chip layer is the bottommost first chip layer, the target voltage drop of the bottommost first chip layer is obtained based on the starting voltage on the bottommost first chip layer and the target effective voltage of the bottommost first chip layer.

13. A simulation device for a chip system, characterized in that, The chip system comprises, from bottom to top, a first chip layer and a second chip layer according to the stacking hierarchy, wherein the design completion degree of the first chip layer is greater than or equal to the target value, and the design completion degree of the second chip layer is less than the target value; the device includes: Abstract model determination module, used to obtain at least one abstract model corresponding to the second chip layer; The simulation module is used to overlay the abstract model onto the design data of the first chip layer and perform voltage drop electromigration simulation to obtain the simulation results of the first chip layer. The abstract model of the second chip layer includes a first electrical model and a physical model; the abstract model determination module is specifically used to perform power consumption analysis on the second chip layer to obtain the first electrical model corresponding to the second chip layer; and to obtain the physical model corresponding to the second chip layer based on the layout information and power supply point location information of the second chip layer. The simulation module is specifically used to instantiate the physical model corresponding to the second chip layer into the first physical design information of the first chip layer to obtain the second physical design information; and to perform voltage drop electromigration simulation based on the first electrical model corresponding to the second chip layer and the second physical design information to obtain the simulation results of the first chip layer.

14. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 12.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

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