Converter acceleration device

Abstract

The transducer acceleration device may include a memory device including a first memory block and a second memory block storing a first plurality of cache vectors and a second plurality of cache vectors for a first plurality of tokens and a second plurality of tokens, respectively, and a memory stride circuit accessing the first memory block and the second memory block. The memory stride circuit may include: a memory block address management circuit storing first and second memory block base addresses of first and second memory blocks; a target address generation circuit that calculates a first target address of the first memory block based on the first memory block base address and the first sub-block offset, and calculates a second target address of the second memory block based on the second memory block base address and the first sub-block offset; and a command issuing circuit that issues the first plurality of memory access commands and the second plurality of memory access commands for the first and second target sub-blocks of the first and second target addresses, respectively.

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