1T2FC ferroelectric storage unit and preparation method thereof

Abstract

The invention provides a 1T2FC ferroelectric storage unit and a preparation method thereof, and the 1T2FC ferroelectric storage unit is configured in an in-memory calculation ferroelectric memory and comprises a selection transistor, a first transistor, a second transistor, a third transistor and a fourth transistor, the first ferroelectric capacitor is electrically connected between a first plate line and the grid electrode of the selection transistor; the second ferroelectric capacitor is electrically connected between a second plate line and the grid electrode of the selection transistor; a word line electrically connected to the select transistor gate; a bit line electrically connected to the drain of the select transistor; a source line electrically connected to the source of the selection transistor; a binary logic state is represented by modulating a polarization state of a ferroelectric capacitor. According to the 1T2FC ferroelectric storage unit and the preparation method thereof, independent ferroelectric polarization of each ferroelectric capacitor is allowed, and a differential sensing technology is utilized, so that the data carrying energy consumption can be reduced, and the reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of in-memory computing memory, in particular to a 1T2FC ferroelectric memory cell and a preparation method thereof. BACKGROUND

[0002] Ferroelectric memory (FRAM) as a new type of non-volatile memory (NVM) can capture and save critical data immediately when the power is interrupted, which is very suitable for mission-critical data recording applications. Ferroelectric memory adopts a low-power and miniaturized design, which can provide instant non-volatility and almost unlimited durability without affecting speed or energy efficiency.

[0003] Compute-in-Memory (CiM) is an architecture that integrates computing functions directly into a memory array, which can reduce data transfer energy consumption.

[0004] The structure of Compute-in-Memory design needs to have multi-bit storage, high durability and simplified array operation. Figure 1 The existing ferroelectric field effect transistor (FeFET) and its multi-bit capability in AI are shown in the prior art, and in Figure 1 (a) is a FeFET device, and (b) is the transmission characteristics of a FeFET device programmed with different voltage pulses, as shown in Figure 1 By controlling the gate voltage (usually referred to as the WL voltage, i.e. the Word Line voltage), the FeFET can have stable multi-level states, and appropriate sensing circuits can be designed to sense current or threshold voltage to distinguish various states of AI applications (memory computing). Since the existing ferroelectric memory mainly relies on the ferroelectric field effect transistor (FeFET) architecture, there is a great limitation in area efficiency. SUMMARY

[0005] In order to solve the defects of the prior art, the purpose of the present application is to provide a 1T2FC ferroelectric memory cell and a preparation method thereof, which adopts two reverse-polarized ferroelectric capacitors (FeCAPs) and a selection transistor, while improving the area efficiency and signal margin, and maintaining the compatibility with the CMOS process.

[0006] To achieve the above purpose, the present application provides a ferroelectric-1T2FC gate device, comprising: a selection transistor; a first ferroelectric capacitor electrically connected between a first plate line and the gate of the selection transistor; a second ferroelectric capacitor electrically connected between a second plate line and the gate of the selection transistor; a word line electrically connected to the gate of the select transistor; a bit line electrically connected to the drain of the select transistor; a source line electrically connected to the source of the select transistor; by modulating the polarization state of the ferroelectric capacitor to represent binary logic states.

[0007] Further, by applying opposite polarity voltages to the first and second ferroelectric capacitors, the polarization state of the ferroelectric capacitor is modulated.

[0008] Further, when the 1T2FC ferroelectric memory cell is written with logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction along a first direction, while a negative polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction opposite to the first direction.

[0009] Further, when the 1T2FC ferroelectric memory cell is written with logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction opposite to the first direction, while a positive polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction along the first direction.

[0010] Further, when the 1T2FC ferroelectric memory cell reads data: a read voltage is applied to the second plate line, and the first plate line is kept at ground; the word line is floated to enable gate-controlled channel conduction; a read voltage is applied to the bit line; the logic state is determined according to the detected drain current of the select transistor.

[0011] Further, the logic state is determined according to the following: high drain current represents logic "1", and low drain current represents logic "0"; the high drain current is the current from the drain to the source of the select transistor when the gate voltage exceeds the threshold voltage, and the channel forms a conductive path; the low drain current is the current from the drain to the source of the select transistor when the gate voltage is below the threshold voltage, and the channel does not form a conductive path.

[0012] Further, after reading data, the memory cell drives the word line, the bit line, the source line, the first plate line and the second plate line to 0V for discharging, to eliminate residual gate charge and prevent data read interference.

[0013] To achieve the above-mentioned purpose, the application also provides a preparation method of a 1T2FC ferroelectric memory cell, comprising the following steps: Depositing a gate oxide layer, a high dielectric constant dielectric layer and a TiN gate electrode on a silicon substrate in sequence to form a gate stack of a selection transistor; Forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation, respectively; Depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region, respectively; Forming two ferroelectric capacitors symmetrically on both sides of the gate stack; connecting the two ferroelectric capacitors to a plate line.

[0014] Further, after the step of forming the gate stack of the selection transistor, the method further comprises a step of forming a word line.

[0015] Further, after the step of depositing the interlayer dielectric layer, the method further comprises a step of forming a bit line and a source line.

[0016] Further, the step of forming two ferroelectric capacitors symmetrically on both sides of the gate stack further comprises: Depositing a bottom electrode, a ferroelectric dielectric layer and a top electrode on both sides of the gate electrode in sequence to form a symmetric first ferroelectric capacitor and a second ferroelectric capacitor; wherein, The ferroelectric dielectric layer is formed by atomic layer deposition, and the bottom electrode and the top electrode are formed by plasma enhanced atomic layer deposition.

[0017] To achieve the above object, the present application also provides a memory array comprising a plurality of 1T2FC ferroelectric memory cells as described above, and the plurality of 1T2FC ferroelectric memory cells operate in-memory computing operations in a parallel manner.

[0018] Further, the memory array accesses a selected row by means of a plurality of voltages.

[0019] Further, when the memory array performs a write operation, a step voltage is applied to reduce the stress on the half-selected and unselected cells; a complementary step voltage or a full voltage is applied to switch the polarization state of the target cell.

[0020] Further, the logic value is stored by differential polarization between the two ferroelectric capacitors in each memory cell To achieve the above object, the present application also provides an AI chip comprising a memory array as described above.

[0021] The 1T2FC ferroelectric memory cell and the preparation method thereof provided by the present application allow independent ferroelectric polarization of each ferroelectric capacitor, and improve reliability by using differential sensing technology. By using two oppositely polarized ferroelectric capacitors and a core sensing selection transistor, the area efficiency and signal margin are improved while maintaining compatibility with the CMOS process.

[0022] Additional features and advantages of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the present application. The features and advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings: Figure 1 Schematic diagram of ferroelectric field effect transistor and its multi-bit capability in AI in the prior art; Figure 2 Schematic diagram of 1T2FC ferroelectric memory cell structure according to embodiments of the present application; Figure 3 Schematic diagram of differential write logic value according to embodiments of the present application; Figure 4 Schematic diagram of read logic value according to embodiments of the present application; Figure 5 Flow chart of 1T2FC ferroelectric memory cell preparation method according to embodiments of the present application; Figure 6 Schematic diagram of active region pattern according to embodiments of the present application; Figure 7 Schematic diagram of gate stack according to embodiments of the present application; Figure 8 Schematic diagram of interlayer dielectric layer and contact hole formation according to embodiments of the present application; Figure 9 Schematic diagram of bit line, source line contact formation according to embodiments of the present application; Figure 10 Schematic diagram of patterning ferroelectric capacitor contact hole on gate according to embodiments of the present application; Figure 11 Schematic diagram of generating bottom electrode of ferroelectric capacitor according to embodiments of the present application; Figure 12 Schematic diagram of stack structure of ferroelectric capacitor according to embodiments of the present application; Figure 13 Schematic diagram of generating plate line, word line according to embodiments of the present application; Figure 14 Schematic diagram of cell integration result according to embodiments of the present application; Figure 15 Schematic diagram of first step operation of writing "0" to memory array according to some embodiments of the present application; Figure 16 Schematic diagram of second step operation of writing "0" to memory array according to some embodiments of the present application; Figure 17 First step of operation for writing a "1" to a memory array according to some embodiments of the application; Figure 18 Second step of operation for writing a "1" to a memory array according to some embodiments of the application; Figure 19 First step of operation for writing a "0" to a memory array according to some other embodiments of the application; Figure 20 Second step of operation for writing a "0" to a memory array according to some other embodiments of the application; Figure 21 First step of operation for writing a "1" to a memory array according to some other embodiments of the application; Figure 22 Second step of operation for writing a "1" to a memory array according to some other embodiments of the application; Figure 23 Read operation for a memory array according to some other embodiments of the application.

[0024] Reference numerals: 101 - select transistor; 102, 103 - ferroelectric capacitor; 401 - active device region; 402 - oxide; 403 - gate oxide layer; 404 - high-K dielectric layer; 405 - TiN gate electrode; 406 - source diffusion region; 407 - drain diffusion region; 409 - contact hole; 410 - bottom electrode; 411 - ferroelectric dielectric layer; 412 - top electrode; 413, 414 - plate line; 415 - word line. DETAILED DESCRIPTION

[0025] The preferred embodiments of the present application will be described herein below with reference to the accompanying drawings; it should be understood, however, that the embodiments described herein are intended to be illustrative only and are not intended to limit the scope of the present application as defined by the appended claims and equivalents thereof. Furthermore, the present application can take many different forms other than the specific embodiments described herein; it should be understood that all such embodiments are within the scope of the present application and appended claims and their equivalents.

[0026] Embodiments of the present application will be described below in greater detail with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that the present application will be more thoroughly and completely understood. It should be understood that the drawings and embodiments of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.

[0027] As used herein, the term "includes" and its variants are open-ended, meaning that "includes but is not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment." The term "another embodiment" means "at least one additional embodiment." The term "some embodiments" means "at least some embodiments."

[0028] It should be noted that the terms "first", "second" and the like in the present application can be used to distinguish different apparatuses, components or parts, but not to limit the order or the interdependence of the functions performed by these apparatuses, components or parts.

[0029] It should be noted that the terms "one", "multiple" mentioned in the present application are illustrative and not restrictive, and those skilled in the art should understand that "one or more" should be understood unless otherwise explicitly indicated in the context. "Multiple" should be understood as two or more.

[0030] The following terms may be mentioned in the present application: CFA: first ferroelectric capacitor; CFB: second ferroelectric capacitor; Transistor: selection transistor, used for gating charge access; PLA: first plate line; PLB: second plate line; WL (Word Line): word line, a wire connected to the gate of the selection transistor, used to control the conduction and cutoff of the selection transistor; BL (Bit Line): bit line, a wire connected to the drain of the selection transistor, used as a channel for data reading; SL (Source Line): source line, a wire connected to the source of the selection transistor, used as a current loop or voltage reference line, and cooperates with the bit line to complete the data read / write operation; +Vpp: positive polarization voltage; -Vpp: negative polarization voltage.

[0031] The related definitions of other terms will be given in the following description.

[0032] Embodiment 1 In the embodiments of the present application, a 1T2FC ferroelectric memory cell is provided, comprising: a selection transistor; a first ferroelectric capacitor electrically connected between a first plate line and the gate of the selection transistor; a second ferroelectric capacitor electrically connected between a second plate line and the gate of the selection transistor; a word line electrically connected to the gate of the selection transistor; a bit line electrically connected to the drain of the selection transistor; a source line electrically connected to the source of the selection transistor; and the polarization state of the ferroelectric capacitor is modulated to represent binary logic states.

[0033] Figure 2 This is a schematic diagram of the 1T2FC ferroelectric memory cell structure according to an embodiment of this application, as shown below. Figure 2 As shown, The 1T2FC ferroelectric memory cell of this application includes a select transistor 201 and two planar ferroelectric capacitors 202 and 203, namely CFA and CFB, symmetrically arranged on both sides of the gate of the select transistor 201. The ferroelectric capacitors CFA and CFB are respectively connected to independent plate lines PLA (Plate Line A) and PLB (Plate Line B), and opposite polarization states can be established on each ferroelectric capacitor. The select transistor 201 has a gate terminal, a source terminal, and a drain terminal, which are respectively connected to the word line (WL), the bit line (BL), and the source line (SL).

[0034] This memory cell is configured to support differential data encoding—one ferroelectric capacitor polarization represents a binary "1", and the other ferroelectric capacitor polarization represents a "0". This 1T2FC (single-select transistor dual ferroelectric capacitor) ferroelectric memory cell has a footprint of 8F² (2F × 4F) and is ideal for high-density integration applications in modern embedded and standalone memory arrays.

[0035] In the embodiments of this application, the ferroelectric capacitor (FeCAP) includes a bottom electrode, a ferroelectric dielectric layer, and a top electrode. The top electrode and the bottom electrode are made of the same material, both being TiN electrodes (TiN is titanium nitride, commonly used as a conductive material for electrodes).

[0036] In the embodiments of this application, the ferroelectric capacitors in the ferroelectric memory cell are manufactured using atomic layer deposition (ALD) and plasma-enhanced ALD (PEALD) techniques to form a high-quality ferroelectric dielectric layer sandwiched between the bottom and top electrodes. Therefore, this ferroelectric memory cell is fully compatible with CMOS (Complementary Metal Oxide Semiconductor) back-end processes, and the ferroelectric capacitors can be integrated above standard logic selection transistors (belonging to the front-end process) without affecting the underlying circuitry.

[0037] Front End Of Line (FEOL): refers to the front-end processes in semiconductor manufacturing, including wafer cleaning, oxidation, photolithography, etching, ion implantation, etc., to form basic components such as selection transistors, preparing for back-end processes (BEOL).

[0038] BEOL: Back-End-of-Line, refers to the phase of semiconductor manufacturing after the formation of selected transistors, including interconnection and packaging processes.

[0039] 8F²: a standard measure of memory cell area, F represents process feature size (e.g. 28 nm).

[0040] In embodiments of the present application, the ferroelectric memory cell adopts a differential write method to store binary data. The differential polarization method using +Vpp and -Vpp voltages is used to write logic values, including: Write logic "1": Apply +Vpp to the plate line PLA of CFA, and ground the other end, so that the polarization vector of CFA is arranged in one direction; At the same time, apply -Vpp to the plate line PLB of CFB, so that the polarization direction is opposite to that of CFA.

[0041] When writing logic "0", the polarity is reversed, that is: Apply -Vpp to the plate line PLA of CFA, and apply +Vpp to the plate line PLB of CFB, so that the polarization states of CFA and CFB are opposite to those when writing logic "1".

[0042] This differential write method ensures non-volatile bistable switching, and binary states are realized by the relative ferroelectric polarization of the two ferroelectric capacitors.

[0043] In embodiments of the present application, the ferroelectric memory cell adopts a current-based read mechanism, and the read operation uses the gate voltage modulation of the selected transistor, which is affected by the net electric field of the polarized ferroelectric capacitor s. When reading: Set PLA to 0V, and apply a small read voltage (Vread) to PLB; The word line (WL) is floating, so that the gate of the selected transistor is a floating node (float) controlled by the capacitive effect of CFA and CFB; A small read voltage (e.g. 0.2-0.7V) is applied to the bit line to start the selected transistor to turn on; According to the relative polarization states of CFA and CFB, the gate voltage induced by the charge distribution is different: if the net polarization reduces the threshold voltage, a high current (ION) is detected, which is interpreted as logic "1"; if the net polarization increases the threshold voltage, a low current (IOFF) is measured, indicating logic "0".

[0044] In the read process, the storage unit works as a floating gate, which can sense the current from the gate. Wherein, +Vpp provides high current (on), -Vpp provides low current (off). This analog current sensing technology enhances the state discrimination ability, supports Multi-Level Cell (MLC) operation, and is suitable for weighted summation scenarios in AI accelerator and in-memory computing.

[0045] In the embodiments of the present application, the ferroelectric storage unit adopts a read-after-discharge scheme. Since the potential problem of floating gate sensing is threshold drift or read interference caused by charge accumulation, the present application solves this problem through a read-after-discharge sequence, without the need for additional circuits to neutralize residual charges. The discharge steps are as follows: After reading the data, all word lines, bit lines, source lines, first plate lines, and second plate line terminals are driven to 0V; the balance state is restored and the floating node charge is released, preventing data retention loss or drift.

[0046] This discharge step can be seamlessly integrated into the read timing of the memory controller, improving architecture reliability and scalability.

[0047] The 1T2FC ferroelectric storage unit of the present application has the following technical effects: (1) By adopting two reverse-polarized ferroelectric capacitors and a core sensing selection transistor, the compatibility with CMOS process is maintained while improving area efficiency and signal margin; (2) A compact (8F²) high-density, multi-bit non-volatile memory can be realized, supporting efficient read and write operations, suitable for in-memory computing applications, effectively solving the limitations of traditional ferroelectric memories in data retention capability and area efficiency; (3) Each ferroelectric capacitor is allowed to be independently polarized, and the reliability is improved by differential sensing; (4) The manufacturing process of the storage unit is compatible with CMOS back-end-of-line (BEOL), and can be extended to 28 nanometer and below process nodes; (5) Compared with existing structures, there are significant advantages in storage density, data retention, computing efficiency, and process compatibility.

[0048] Embodiment 2 The difference between this embodiment and embodiment 1 is that the selection transistor of the 1T2FC ferroelectric memory cell in this embodiment is an n-channel MOSFET transistor. By using a core n-channel MOSFET (nMOS) transistor as the selection transistor, access control and current modulation in read and write operations are achieved. By using two planar ferroelectric capacitors (CFA and CFB) symmetrically arranged on both sides of the gate terminal of the selection transistor, binary information is encoded by the polarization direction as a ferroelectric storage element.

[0049] The 1T2FC ferroelectric memory cell further comprises: Two plate lines (PLA and PLB): PLA is connected to CFA, and PLB is connected to CFB. PLA and PLB are used to apply voltage during read and write to achieve independent polarity control of the two ferroelectric capacitors.

[0050] One word line (WL) is directly connected to the gate of the selection transistor.

[0051] One bit line (BL) and one source line (SL) are respectively coupled to the drain and source of the selection transistor, and are used for current path during sensing and programming operations.

[0052] In the embodiments of the present application, the lateral size of each ferroelectric capacitor (CFA and CFB) is 40 nanometers x 40 nanometers.

[0053] In the embodiments of the present application, the ferroelectric capacitor stack comprises a TiN bottom electrode, a ferroelectric HfZrO2 (HZO) dielectric layer, and a TiN top electrode. The ferroelectric dielectric layer is prepared by atomic layer deposition (ALD), and the TiN top / bottom electrode is prepared by plasma-enhanced ALD (PEALD) deposition. The final structure of the memory cell is fully compatible with the CMOS back-end-of-line (BEOL) process, and the cell size is 8F² (2F x 4F).

[0054] HfZrO2 (HZO): hafnium-zirconium oxide, a high-K (dielectric constant) dielectric material with ferroelectric properties.

[0055] In the embodiments of the present application, during writing of the memory cell, differential binary encoding is achieved by the two ferroelectric capacitors with reverse polarization.

[0056] Figure 3 For a schematic diagram of the differential write logic value according to the embodiments of the present application, reference is made to Figure 3 The differential write process according to the embodiments of the present application is described in detail. The write process is divided into the following two steps according to the target logic state: 1) Writing logic "0" to CFB: applying positive polarization voltage (+Vpp) to CFB through PLB, so that the polarization direction is downward (toward the gate); applying negative polarization voltage (-Vpp) to CFA through PLA, so that the polarization direction is upward (away from the gate).

[0057] 2) Writing logic "1" to CFA: applying negative polarization voltage to CFB through PLB, so that the polarization direction is upward (away from the gate); applying positive polarization voltage to CFA through PLA, so that the polarization direction is downward (toward the gate).

[0058] This reverse polarization generates a net potential at the gate of the selection transistor, modulating the threshold voltage of the device, thus encoding the binary logic value. Therefore, the differential polarization method improves the sensing margin during reading of the ferroelectric memory cell, and has strong anti-noise capability.

[0059] In this embodiment, during reading operation, a current mode sensing mechanism is used to read data.

[0060] Figure 4 For a schematic diagram of reading a logic value according to an embodiment of the present application, reference will be made to Figure 4 The reading process of the embodiment of the present application will be described in detail.

[0061] In the embodiment of the present application, the gate operating voltage of the selection transistor is 1.2V, and the reading operation steps are as follows: A small reading voltage (Vread) is applied to the second plate line PLB, which is sufficient to generate a measurable current and does not interfere with the ferroelectric state; The first plate line PLA is grounded (0V) to provide a reference potential; The word line is floating, so that the gate potential is completely determined by the net effect of the polarized ferroelectric capacitor, so as to realize gate control of the channel conduction; A reading voltage is applied to the bit line to detect the current from the drain to the source, i.e. the drain current (Ids); The logic state is determined according to the measured drain current: High drain current (on state) indicates that the polarization configuration results in a low effective threshold voltage; Low drain current (off state) indicates that the reverse polarization configuration results in a high threshold voltage.

[0062] In the embodiment of the present application, the small reading voltage refers to a voltage in the range of 0.2V-0.7V.

[0063] In the embodiment of the present application, high drain current refers to the current from the drain to the source when the gate voltage of the selection transistor exceeds the threshold voltage, and the channel is completely open, and the current reaches a saturation value. Low drain current refers to the current from the drain to the source when the gate voltage of the selection transistor is lower than the threshold voltage, and the channel does not form a conductive path, and the current is reduced to a very low value.

[0064] In embodiments of the present application, the logic state is determined by detecting the drain current of the select transistor, and judging the logic state according to the net polarization effect of CFA and CFB on the gate potential. The logic state is determined according to the following principle: high drain current represents logic "1", and low drain current represents logic "0".

[0065] In embodiments of the present application, the method for detecting the drain-to-source current (Ids) includes but is not limited to converting the drain-to-source current (Ids) into a voltage signal through a transimpedance amplifier (TIA), quantizing the voltage signal through an ADC (analog-to-digital converter), and comparing the quantized voltage signal with a reference value to determine the logic state.

[0066] In embodiments of the present application, after reading data each time, the floating gate (which can store charges for a long time and has no direct electrical connection) may cause threshold drift or data interference due to residual charges caused by capacitive coupling. The solution is as follows: A post-reading discharge sequence is introduced to drive all WL, BL, SL, PLA, and PLB to 0V. The gate node is restored to a neutral state, and the stray charges accumulated during reading are cleared.

[0067] This discharge process is automatically performed by the memory controller without additional hardware, ensuring long-term reliability.

[0068] The 1T2FC ferroelectric memory cell of the present application is fully compatible with CMOS back-end process integration and is suitable for nodes below 40nm.

[0069] Embodiment 3 In embodiments of the present application, a preparation method of a 1T2FC ferroelectric memory cell is also provided, including the following steps: depositing a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode on a silicon substrate in sequence to form a gate stack of a select transistor; forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation; depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region; forming two ferroelectric capacitors symmetrically on both sides of the gate stack; and connecting the two ferroelectric capacitors to a plate line.

[0070] Figure 5 The flowchart of the preparation method of the 1T2FC ferroelectric memory cell according to Embodiment 1 of the present application is as follows, and the following will be described with reference to Figure 5 The preparation method of the 1T2FC ferroelectric memory cell according to Embodiment 1 of the present application will be described in detail.

[0071] First, in step 501, a shallow trench isolation (STI) is used to define and isolate active area device regions on a silicon substrate.

[0072] In the embodiment of the present application, the step includes: on the silicon substrate, first defining a shallow trench isolation region by photolithography, and then forming an STI (Shallow Trench Isolation) trench with a preset depth in the shallow trench isolation region by dry etching (such as HBr / Cl2 plasma) to isolate a plurality of active device regions 401 on the silicon substrate through the trench.

[0073] In step 502, the surface of the silicon substrate is pretreated.

[0074] In the embodiment of the present application, the step includes: depositing an oxide 402 (such as SiO2, by HDP-CVD) in the formed trench to fill the trench; and removing the excess material by chemical mechanical polishing (CMP) to keep the surface flat. As shown in Figure 6 By depositing the oxide 402 in the trench, a plurality of active device regions 401 (also referred to as active region patterns) are formed on the silicon substrate.

[0075] In step 503, a gate stack is generated on the active device region.

[0076] In the embodiment of the present application, the step includes: Growing or depositing a gate oxide layer 403: growing a gate oxide, such as growing SiO2 (silicon dioxide) or silicon oxynitride gate medium (SiON gate oxide), on the active device region 401, SiON has a higher dielectric constant than SiO2 (improving the interface state of high-K medium); Depositing a high-K medium layer and a gate electrode to define a gate: on the gate oxide layer 403, generating a high-K medium layer 404 (HK dielectric) and a TiN gate electrode 405 (TiN Gate) by ALD to form a gate stack, and forming a gate by photolithography + dry etching; Patterning the gate to form a word line (WL); Performing ion implantation and annealing to form N+ source diffusion region 406 and drain diffusion region 407, and thermal annealing to activate the doping and form a low-resistance junction. As shown in Figure 7 As shown in the figure, the gate stack of the gate oxide layer 403, the high-K medium layer 404 and the TiN gate electrode 405 is sequentially grown on the active device region 401 to form a word line (WL), and the N+ source diffusion region 406 and the drain diffusion region 407 are formed by ion implantation and annealing.

[0077] In step 504, bit lines BL and source lines SL are generated on the source and drain diffusion regions.

[0078] In the embodiments of the present application, the step includes: depositing an interlayer dielectric (ILD) on the source diffusion region 406 and the drain diffusion region 407 and opening a contact hole, respectively connecting the source diffusion region 406 and the drain diffusion region 407, filling the contact hole with a conductive metal (such as tungsten or copper), and forming a source line (SL) and a bit line (BL).

[0079] As shown in FIG. 4B, an interlayer dielectric (ILD) is deposited on the source diffusion region 406 and the drain diffusion region 407, and a source line (SL) and a bit line (BL) are formed on the interlayer dielectric, respectively. Figure 8 9 As shown in FIG. 4B, an interlayer dielectric (ILD) is deposited on the source diffusion region 406 and the drain diffusion region 407, and a source line (SL) and a bit line (BL) are formed on the interlayer dielectric, respectively.

[0080] In the embodiments of the present application, the step 504 further includes: ILD deposition: depositing an oxide (such as SiO2) above the source diffusion region 406 and the drain diffusion region 407 and planarizing by CMP to generate an interlayer dielectric layer; Contact hole formation: performing photolithography on the interlayer dielectric layer and etching to the source / drain diffusion region to form a contact hole; Metal filling: filling the contact hole with a conductive metal.

[0081] In step 505, a ferroelectric capacitor is generated on both sides of the gate.

[0082] In the embodiments of the present application, the step includes: Patterning a ferroelectric capacitor contact hole 409 on the gate, as shown in FIG. 5B; forming a bottom electrode (BE) of the ferroelectric capacitor above the contact hole 409, as shown in FIG. 5C; sequentially depositing a bottom electrode 410, growing a ferroelectric dielectric layer 411, and depositing a top electrode 412 on the bottom electrode (BE), as shown in FIG. 5D; and activating by annealing to complete the stacked structure of the ferroelectric capacitor. Figure 10 Figure 11 Figure 12

[0083] Specifically, by photolithography, a deep hole is formed by etching the ILD to the gate; a TiN bottom electrode is deposited by plasma-enhanced ALD (PEALD); a HfZrO2 ferroelectric film is deposited by ALD to form a ferroelectric dielectric layer; a TiN top electrode is deposited by ALD, and finally the electrode pattern is defined by photolithography stripping.

[0084] In step 506, metal wiring is performed.

[0085] ​​​​In embodiments of the application, metal wiring layers (e.g. M3, M4) are used to define independent plate lines for CFA and CFB; metallization and patterning define word lines (WL) and connect to select transistor gates.

[0086] As shown in FIG. 4B, plate lines 413, 414 (PLA and PLB) are formed on top electrode 412 through interconnect metal layers (e.g. M3, M4); word line 415 and other wiring layers, such as bit lines, source lines, are connected through vias. Further, a SiN etch stop layer is deposited, and top electrode 412 of the ferroelectric capacitor is connected through a via by photolithography; a trench is etched and copper is electroplated to form plate lines 413, 414 (M4) and word line 415 (M3). Figure 13

[0087] In step 507, back-end integration is completed.

[0088] In embodiments of the application, semiconductor back-end process (BE) is performed for passivation and planarization required for packaging, and unit integration is completed, as shown in FIG. 4C. Figure 14

[0089] In embodiments of the application, this step includes: Dimension verification: 2F x 4F (= 8F 2 ) layout (e.g. 28 nm node: lateral gate length 28 nm x vertical metal pitch 56 nm) is confirmed by electron beam detection; Deposition of passivation layer: SiN passivation layer is deposited, and a pad window is opened.

[0090] The 1T2FC ferroelectric memory cell of embodiments of the application ensures high-density scalability, is compatible with 28 nm, 22 nm and more advanced nodes, and is fully compatible with CMOS back-end processes.

[0091] Embodiment 4 In embodiments of the application, a memory array is also provided, including a plurality of 1T2FC ferroelectric memory cells as described above, and a plurality of the memory cells operate in-memory computing operations in a parallel manner.

[0092] In embodiments of the application, a selected row is accessed by a multi-step voltage scheme to avoid interference with half-selected cells and unselected cells.

[0093] A selected row refers to a row of memory cells in a memory array that is selected for read / write operation by activating a word line (WL). A multi-step voltage scheme for accessing a selected row refers to a reliable read / write operation achieved by applying different voltages in stages, for example, decomposing a single high-voltage operation into multiple low-voltage steps to gradually complete row activation, data reading or writing, and pre-charging, thereby balancing performance, power consumption and reliability.

[0094] ​​Definition of selected memory cell: In a memory array, a half-selected cell refers to a memory cell that is only column-selected (word line activated) or row-selected (bit line activated) but not fully selected in a read or write operation. Such a cell is in a potential disturbance state; a fully selected cell refers to a cell whose word line and bit line are both activated (effective voltage applied) and the cell can be read or written; an unselected cell refers to a cell whose word line and bit line are not activated.

[0095] In embodiments of the present application, to avoid the disturbance of voltage selection on adjacent or half-selected cells, a multi-step voltage write scheme (such as 2 / 3 Vpp, 1 / 3 Vpp, etc. fractional voltage) is used. By selecting appropriate Vpp and Vdd (voltage applied to bit line BL and source line SL), the disturbance of unselected cells or half-selected cells is avoided.

[0096] In embodiments of the present application, the write operation of the memory array includes: First, a fractional voltage (such as 2 / 3 Vpp, 1 / 3 Vpp) is applied to reduce the stress on half-selected and unselected cells; Second, a complementary fractional voltage or full voltage is applied to complete the polarization switching of the target cell.

[0097] Complementary fractional voltage: refers to the application of voltages of opposite polarity but different amplitudes to the two complementary ferroelectric capacitors of the target cell, such as +0.6V to one ferroelectric capacitor and -0.4V to the other ferroelectric capacitor, to achieve state switching by differential polarization.

[0098] Full voltage: refers to the application of maximum allowed voltages of opposite polarity to the two complementary ferroelectric capacitors of the target memory cell, such as ±3Vpp, which is much higher than Vc, forcing the ferroelectric domain to completely flip, thereby achieving state switching.

[0099] In some embodiments of a 1T2FC (single select transistor double ferroelectric capacitor) memory array, as shown in Figure 14 except that the storage cells in the rightmost column are half-selected cells, the rest of the storage cells are selected cells. The write "0" operation is divided into two steps: First, as shown in Figure 15As shown, the PLA of the storage cells in the second row is applied with 1 / 3Vpp, the PLB is applied with Vpp, and the same voltage is applied to the PLA and PLB of the storage cells in other rows. By selecting appropriate Vpp and Vdd: 2 / 3Vpp–Vdd < Vc (<Vdd), Vpp < 3Vdd, the unselected cells and semi-selected cells are not disturbed; where Vc represents the coercive voltage, which is defined as the minimum voltage required to reverse the polarization direction of the ferroelectric domain; in the polarization-voltage (P-V) hysteresis loop, Vc is the voltage at which the polarization value crosses zero during the voltage scan. It marks the inflection point at which the ferroelectric material switches between the following two states: positive remanent polarization +Pr (after applying +V>Vc), and negative remanent polarization -Pr (after applying -V<-Vc). The second step is as Figure 16 shown, the PLA of the storage cells in the second row is applied with -Vpp, and the PLB is applied with -1 / 3Vpp. By selecting appropriate Vpp and Vdd: -2 / 3Vpp+Vdd > -Vc(>-Vdd), Vpp < 3Vdd, the unselected cells and semi-selected cells are not disturbed.

[0100] The operation of writing "1" is divided into two steps: The first step is as Figure 17 shown, the PLA of the storage cells in the second row is applied with -1 / 3Vpp, and the PLB is applied with -Vpp. By selecting appropriate Vpp and Vdd: -2 / 3Vpp+Vdd > -Vc(>-Vdd), Vpp < 3Vdd, the unselected cells and semi-selected cells are not disturbed; The second step is as Figure 18 shown, the PLA of the storage cells in the second row is applied with Vpp, and the PLB is applied with 1 / 3Vpp. By selecting appropriate Vpp and Vdd: 2 / 3Vpp–Vdd < Vc(<Vdd), Vpp < 3Vdd, the unselected cells and semi-selected cells are not disturbed.

[0101] In the 1T2FC (single select transistor double ferroelectric capacitor) memory array of some other embodiments, as Figure 19 shown, only the storage cells in the rightmost column are semi-selected cells, and the rest of the storage cells are unselected cells. The operation of writing "0" is divided into two steps: The first step is as Figure 19 shown, the voltage applied to the PLA of the storage cells in the second row is 0V, the PLB is applied with 1 / 2Vpp, and the voltages applied to the PLA and PLB of the rest of the storage cells are both 0V. By selecting appropriate Vpp and Vdd: 1 / 2Vpp < Vdd, 1 / 2Vpp< Vc, the unselected cells and semi-selected cells are not disturbed; The second step is asFigure 20 As shown, the PLA of the second row of memory cells is supplied with a voltage of 1 / 2Vpp, and the PLB is supplied with 0V. By selecting appropriate Vpp and Vdd: 1 / 2Vpp < Vdd, 1 / 2Vpp < Vc, the unselected and partially selected cells are not interfered with.

[0102] Writing a "1" involves two steps: First step, such as Figure 21 As shown, the PLA of the second row of memory cells is supplied with 1 / 2Vpp, and the PLB is supplied with 0V. By selecting appropriate Vpp and Vdd: 1 / 2Vpp < Vdd, 1 / 2Vpp < Vc, the unselected and partially selected cells are not interfered with. The second step, as Figure 22 As shown, the PLA of the second row of memory cells is applied with a voltage of 0V, and the PLB is applied with 1 / 2Vpp. By selecting appropriate Vpp and Vdd: 1 / 2Vpp < Vdd, 1 / 2Vpp < Vc, the unselected and partially selected cells are not interfered with.

[0103] During a read operation, such as Figure 23 As shown, the word line is driven to 0V, the voltage applied to PLA of the second row of memory cells is 0V, the voltage applied to BL is Vd, and the read voltage Vread is applied to PLB, satisfying: Vread < Vc, and the value of Vd is in the range of 0.2V - 0.7V (< Vdd).

[0104] In the embodiments of this application, the logic values ​​in the memory array are stored through differential polarization between two ferroelectric capacitors, and the read margin and noise immunity of the memory array are improved through differential current sensing.

[0105] Example 5 In embodiments of this application, an AI chip is also provided, including the memory array described above. AI chips employing this memory array significantly improve area efficiency and signal tolerance.

[0106] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A 1T2FC ferroelectric memory cell configured in an in-memory computing ferroelectric memory, characterized in that, Comprising: a select transistor; a first ferroelectric capacitor electrically connected between a first plate line and a gate of the select transistor; a second ferroelectric capacitor electrically connected between a second plate line and the gate of the select transistor; a word line electrically connected to the gate of the select transistor; a bit line electrically connected to a drain of the select transistor; a source line electrically connected to a source of the select transistor; a polarization state of the ferroelectric capacitor is modulated to represent a binary logic state.

2. The 1T2FC ferroelectric memory cell of claim 1, wherein, The polarization state of the ferroelectric capacitor is modulated by applying a voltage of opposite polarity to the first ferroelectric capacitor and the second ferroelectric capacitor.

3. The 1T2FC ferroelectric memory cell of claim 1, wherein, When the 1T2FC ferroelectric memory cell is written with a logic "1", a positive polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction along a first direction, while a negative polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction opposite to the first direction.

4. The 1T2FC ferroelectric memory cell of claim 1, wherein, When the 1T2FC ferroelectric memory cell is written with a logic "0", a negative polarization voltage is applied to the first ferroelectric capacitor to make its polarization direction opposite to the first direction, while a positive polarization voltage is applied to the second ferroelectric capacitor to make its polarization direction along the first direction.

5. The 1T2FC ferroelectric memory cell of claim 1, wherein, When the 1T2FC ferroelectric memory cell reads data: a read voltage is applied to the second plate line, while the first plate line is kept at ground; the word line is floated to enable gate-controlled channel conduction; a read voltage is applied to the bit line; a logic state is determined according to a detected drain current of the select transistor.

6. The 1T2FC ferroelectric memory cell of claim 5, wherein, The logic state is determined according to that a high drain current represents a logic "1" and a low drain current represents a logic "0"; The high drain current is a current from the drain to the source of the select transistor when a gate voltage exceeds a threshold voltage to form a conductive channel; The low drain current is a current from the drain to the source of the select transistor when a gate voltage is below the threshold voltage to not form a conductive channel.

7. The 1T2FC ferroelectric memory cell of claim 6, wherein, After reading data, the memory cell discharges the word line, the bit line, the source line, the first plate line and the second plate line to 0V to eliminate residual gate charge and prevent data read interference.

8. A method of fabricating a 1T2FC ferroelectric memory cell, comprising: Comprising the following steps: forming a gate stack of a select transistor by sequentially depositing a gate oxide layer, a high dielectric constant dielectric layer and a TiN gate electrode on a silicon substrate; forming a source diffusion region and a drain diffusion region on the silicon substrate by ion implantation and activation; depositing an interlayer dielectric layer on the source diffusion region and the drain diffusion region; forming two ferroelectric capacitors symmetrically on both sides of the gate stack; connecting the two ferroelectric capacitors to plate lines.

9. The method of claim 8, wherein the 1T2FC ferroelectric memory cell is formed by: After forming the gate stack of the select transistor, further comprising a step of forming a word line.

10. The method of claim 8, wherein the 1T2FC ferroelectric memory cell is formed by: After depositing the interlayer dielectric layer, further comprising steps of forming a bit line and a source line.

11. The method of fabricating a 1T2FC ferroelectric memory cell of claim 8, wherein, The step of forming two ferroelectric capacitors symmetrically on both sides of the gate stack further comprises: depositing a bottom electrode, a ferroelectric dielectric layer and a top electrode sequentially on both sides of the gate electrode to form a symmetric first ferroelectric capacitor and a second ferroelectric capacitor; wherein the ferroelectric dielectric layer is formed by atomic layer deposition, and the bottom electrode and the top electrode are formed by plasma-enhanced atomic layer deposition.

12. A memory array, comprising: A plurality of the 1T2FC ferroelectric memory cells of any one of claims 1-7, the plurality of the 1T2FC ferroelectric memory cells operating in parallel to perform in-memory computing operations.

13. The memory array of claim 12, wherein, The memory array accesses a selected row by way of a plurality of voltages.

14. The memory array of claim 13, wherein, The memory array performs a write operation by applying a stepped voltage to mitigate stress on half-selected and unselected cells and by applying a complementary stepped voltage or a full voltage to switch a polarization state of a target cell.

15. The memory array of claim 12, wherein, A logic value is stored by a differential polarization between the two ferroelectric capacitors in each memory cell.

16. An AI chip, comprising: A memory array comprising the memory cell of any one of claims 13-15.

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