A low-power test circuit for computing errors of a memory-computing integrated circuit

Abstract

The application discloses a low-power test circuit for calculation error of memory-computing integration, which comprises a memory-computing array, a pipeline addition tree and a digital shift addition module. The memory-computing unit in the memory-computing array stores weights in the form of analog signals such as charge quantity or resistance value. i,j Meanwhile, the weight value W i,j is stored in the low several bits of the shift register of the jth digital shift addition circuit S j in the form of a digital signal; a vector is input to the column line of the memory-computing array, each element of the vector is multiplied and added with the weight value at the corresponding position, the memory-computing array completes the multiplication and addition operation in the form of an analog signal, the digital shift addition circuit completes the multiplication and addition operation in the form of a digital signal, and an accurate calculation result is obtained; the multiplication and addition operation result of the memory-computing array is converted into a digital signal through a digital-analog conversion unit, and is compared with the operation result of the digital shift addition circuit, so that the calculation error of the memory-computing array in the memory-computing integration is tested.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing integrated circuit technology, and in particular to a low-power test circuit for in-memory computing error. Background Technology

[0002] Most neural network layers in AI (Artificial Intelligence) algorithms involve a large number of dot product operations between data vectors and weight vectors, with multiplication and addition operations accounting for more than 90% of the arithmetic operations in AI algorithms. Traditional digital circuits or AI chips contain a large number of multipliers and adders to perform multiplication and addition operations in parallel, resulting in large circuit area and power consumption.

[0003] In-memory computing chips use analog signals to perform numerous multiplication and addition operations in AI algorithms. The weighting factors in multiplication are programmed into the in-memory units. During multiplication and addition, only image data needs to be read from external memory (such as DDR memory), eliminating the need to read the weighting factors, thus solving part of the "memory wall" problem, i.e., the data transfer issue. Because analog signals are used to perform multiplication and addition operations, in-memory computing devices with analog circuitry must be used. Analog in-memory computing devices have a small area and low power consumption, enabling large-scale deployment. For AI chips of the same area, the power consumption of in-memory units implemented with analog in-memory computing devices is 1 to 2 orders of magnitude smaller than that of multiplication and addition units in digital circuitry. Therefore, in-memory computing chips have a very high computing power-to-energy ratio.

[0004] While in-memory computing has the advantages mentioned above, one problem is insufficient computational accuracy. That is, the results of multiplication and addition operations obtained using analog in-memory computing devices are inaccurate, while the results obtained by digital circuits are accurate. Therefore, the relevant in-memory computing chips should have error measurement circuits to compensate for the calculation results of analog in-memory computing devices.

[0005] Currently, the in-memory computing units within an integrated memory computing system are mainly implemented using SRAM, RRAM, MRAM, Flash, and CAS units. Summary of the Invention

[0006] The purpose of this invention is to provide a low-power test circuit for in-memory computing errors, so as to solve the problems in the background art.

[0007] To address the aforementioned technical problems, this invention provides a low-power test circuit for in-memory computing errors, comprising an in-memory array, a pipelined addition tree, and a digital shift addition module;

[0008] The memory array consists of M rows and N columns of memory units, each memory unit being F. i,j(i,j) represents the row i and column j of the in-memory unit, i = 0, 1, 2, 3, ..., M-1, j = 0, 1, 2, 3, ..., N-1; the row lines of each row in the in-memory unit are connected to a digital-to-analog converter (AD).

[0009] The in-memory array performs the multiplication and accumulation of vectors and weights in the form of analog semaphores;

[0010] The pipeline addition tree and the digital shift addition module constitute a partial product shift compression summation module, which performs vector and weight multiplication and accumulation in the form of digital semaphores.

[0011] The current in each row of the in-memory array is converted into a digital signal by an analog-to-digital converter (ADC). This digital signal is subtracted from the calculation result of the pipelined addition tree to obtain the calculation error of the in-memory array.

[0012] In one implementation, the digital shift plus module includes a data register DR and a weight register WR;

[0013] The data register DR is used to shift the input vector data and at the same time provide data ds for each column of the storage array;

[0014] The function of the weight register WR is to shift the weights and generate a partial product PP of each bit of the data and each bit of the weight.

[0015] In one embodiment, the pipeline addition tree consists of four stages: L0, L1, L2, and L3. The first three stages sum the partial products of all inputs, and the L3 stage accumulates the partial products of all bits.

[0016] In one embodiment, a storage unit F in the storage array i,j The weight W is written through external circuitry. i,j The weight W i,j Stored in the memory unit F in the form of analog signals i,j middle;

[0017] Among them, in the storage unit F i,j When performing weight programming, the weight is written into the weight register WR in the form of a digital semaphore, and the weight W... i,j It is represented by an 8-bit digital value.

[0018] In one implementation, the column lines of the memory array are input to an N-dimensional vector V = {E0, E1, E2, ..., E...} N-1}, each element E of the vector k(k = 0, 1, 2, ..., N-1) is represented by an 8-bit digital value; the corresponding elements of the vector V are input to N digital shift-add modules, and the j-th element is written to the digital shift-add module S. j In the middle; given the start signal, the storage array and all digital shift-add modules begin calculating the partial product PP of vector V and N weights. j .

[0019] In one implementation, the data register DR is an 8-bit shift register that shifts 1 bit to the least significant bit each time; the weight register WR is a 15-bit shift register that shifts 1 bit to the most significant bit each time.

[0020] If the least significant bit of the data register DR is 1, then all bits of the weight register WR will be used as the partial product output PP. j ,

[0021] If the least significant bit of the data register DR is 0, output PP as a partial product. j .

[0022] In one embodiment, in the pipelined addition tree, in the first-stage pipeline L0, the partial product of each digital shift-add module is output as PP. j The first pipeline uses N / 2 adders to add the results pairwise. In the second pipeline L1, the compressed N / 2 results from the first pipeline L0 are added pairwise using N / 4 adders. In the third pipeline L2, the compressed N / 4 results from the second pipeline L1 are added pairwise using N / 8 adders. In the final pipeline L3, one adder is used to obtain the result of the multiplication and addition operation of vector V and N weight values. If N / 2, N / 4, N / 8... cannot produce an integer, the largest integer less than or equal to the result is taken.

[0023] This invention provides a low-power test circuit for in-memory computing errors. Through digital circuit shifting and addition, a pipelined addition tree, and an in-memory array, it tests the errors generated by multiplication and addition operations performed by the in-memory array in an in-memory computing chip. For multiplication and addition operations of a vector of dimension N with N weights, this in-memory computing error test circuit saves N multipliers and N-1 full adders, significantly reducing circuit area and power consumption. Attached Figure Description

[0024] Figure 1 A schematic diagram of a low-power test circuit for in-memory computing error provided by the present invention;

[0025] Figure 2 A schematic diagram of the structure of the digital shift addition module is provided for this invention;

[0026] Figure 3 This is a schematic diagram of the pipeline addition tree structure provided by the present invention;

[0027] Figure 4 A schematic diagram of key signal timing for a low-power test circuit for in-memory computing errors provided by the present invention;

[0028] Figure 5 This is a schematic diagram of the working process of the low-power test circuit for in-memory computing error provided by the present invention. Detailed Implementation

[0029] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a low-power test circuit for in-memory computing errors proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0030] Figure 1 The diagram shows the overall structure of the low-power test circuit for in-memory computing error proposed in this invention. The in-memory computing units CM are connected by row lines sl and column lines ds to form a 5-row, 12-column in-memory array CIM_ARRAY. Each row line is connected to a digital-to-analog converter (A / D). Figure 1 Each small circle in the array represents a storage unit (CM). The PPSCS (Partial Production Shifting-Compress Summation) module performs vector-weight multiplication and accumulation in the form of digital semaphores, yielding an accurate result; the storage array CIM_ARRAY performs vector-weight multiplication and accumulation in the form of analog semaphores. The PPSCS module consists of two sub-circuits: a digital shift-add module and a pipelined adder tree.

[0031] Figure 2 The diagram shows the structure of a digital shifter module, which mainly consists of two parts: an 8-bit data register DR and a 15-bit weight register WR. The data register DR is used to shift the input vector data and provide data ds for each column of the storage array; the weight register WR is used to shift the weights and generate the partial product PP of each bit of the data and each bit of the weight.

[0032] Figure 3 The diagram shown is a structural diagram of a pipeline addition tree. The function of this addition tree is to add... Figure 2The partial products PP of each bit are accumulated to obtain the product and sum of the input vector and weights. The pipelined addition tree consists of 4 stages: L0, L1, L2, and L3. The first 3 stages sum the partial products of all inputs, and the L3 stage accumulates the partial products of all bits.

[0033] Figure 4 The diagram shown is a signal timing diagram of one possible input data for a low-power test circuit for in-memory computing error.

[0034] The following steps are described in one possible implementation, and the process is as follows: Figure 5 As shown, it includes the following steps:

[0035] (1) Step 101: Write the weight value W to the memory cell at position (i,j). i,j , where i represents the i-th row and j represents the j-th column. Figure 1 A 5x12 in-memory array CIM_ARRAY is given, where each row line is connected to an analog-to-digital converter ADi (i = 0, 1, 2, 3, 4). When writing weights, the row line of the i-th row is pulled high and the column line of the j-th column is pulled high. By maintaining the high level for different durations, different amounts of charge or different conductance values ​​are stored in the in-memory unit CM.

[0036] At the same time, the 8-bit wide weight value W i,j The lower 8 bits of the weight register WR in the digital shift and add module are written through the interface {w0,w1,w2,w3,w4,w5,w6,w7}, i.e., the weight value W = {W7,W6,W5,W4,W3,W2,W1,W0}. The higher 7 bits of the weight register WR are written as 0, i.e., {W8,W9,W10,W11,W12,W13,W14} = 0000000. See [link / reference needed]. Figure 2 .

[0037] (2) Step 102: Input a 12-dimensional vector into the storage array CIM_ARRAY. The first element of this vector is E0 = {d7,d6,d5,d4,d3,d2,d1,d6,d5,d4,d3,d5,d6,d4,d5,d6,d5,d6,d7,d6,d7,d8,d9,d9,d1,d9,d9,d9,d9,d 10} = 10110011 = 179, see Figure 4 The data signal in the middle, and the remaining elements E1 to E 11 Both are 0; E0 is stored in the data register DR of the digital shifter-adder module, see... Figure 2 The least significant bit drive signal ds of the data register DR is connected to the column line of column 0 of the memory array CIM_ARRAY; and so on. Figure 3The ds output signal of the j-th digital shift-add module Sj is connected to the j-th column line of the in-memory array CIM_ARRAY. Simultaneously, the in-memory start signal start is given, and the start signal is high for one clock cycle. (See...) Figure 4 .

[0038] (3) Step 103: In each calculation, the data register DR in the digital shift and add module S0 shifts one bit towards the low-order bit, and the weight register WR shifts one bit towards the high-order bit. Simultaneously, the counter cnt counts once per storage operation. See [link to relevant documentation]. Figure 4 At times 1, 2, 3, 4, 5, 6, 7, and 8, Figure 2 The values ​​of ds are 1, 1, 0, 0, 1, 1, 0, 1, driving the memory array CIM_ARRAY to accumulate the analog current, and then generating the multiplication-accumulation result through the analog-to-digital converter circuit AD0. (See...) Figure 1 The resad0 signal in the counter; at times cnt = 1, 2, 3, 4, 5, 6, 7, 8, Figure 2 The values ​​of the middle part product PP are {W,0}, {W,00}, {0}, {0}, {W,0000}, {W,00000}, {0}, {W,0000000}, that is... Figure 4 The PP signals in the code are: W, W*, 0, 0, W*16, W*32, 0, W*128.

[0039] (4) Step 104: The pipelined addition tree performs a partial product PP of all number shifts and addition modules for each iteration. j To accumulate, see Figure 3 For the 12 partial products, a 4-stage pipelined adder tree can be used to accumulate all partial products. The ADDER(2,2) and the accumulator register ACCR in the L3 pipeline stage constitute the accumulator, and the adders in other pipeline stages complete the addition of every two partial products. The accumulator counter cnt is initialized to 0.

[0040] Because a 4-stage pipelined addition tree is used, at times cnt 4, 5, 6, 7, 8, 1, 2, 3, the sum of the partial products of the digital shift-add module at times 1, 2, 3, 4, 5, 6, 7, 8 reaches the adder input before the accumulator register ACCR in the L3 pipeline. At times cnt 5, 6, 7, 8, 1, 2, 3, 4, the multiply-accumulated result is obtained at the output Q of the accumulator register ACCR. That is, the values ​​of the partial multiply-accumulated results res_mac at each time point are W, W*3, W*3, W*3, W*19, W*51, W*51, W*179, respectively. (See...) Figure 4 and Figure 3 The res_mac signal in the system.

[0041] (5) In steps 105 and 104, the multiplication-accumulation result res_mac obtained when the counter cnt is 4 is subtracted from the result resad0 calculated by the in-memory array CIM_ARRAY in step 103 using the subtractor SUB0. This subtracts the error value comp0 between the multiplication-accumulation result calculated by the in-memory array CIM_ARRAY and the exact result. See Figure 1 .

[0042] For the sake of brevity, not all possible combinations of different storage unit weights and different data inputs in the above embodiments are described. However, as long as these combinations do not contradict each other, they should be considered to be within the scope of this specification.

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power test circuit for in-memory computing error, characterized in that, This includes in-memory arrays, pipelined addition trees, and digital shift addition modules; The memory array consists of M rows and N columns of memory units, each memory unit being F. i,j (i,j) represents the row i and column j of the in-memory unit, i = 0, 1, 2, 3, ..., M-1, j = 0, 1, 2, 3, ..., N-1; the row lines of each row in the in-memory unit are connected to a digital-to-analog converter (AD). The in-memory array performs the multiplication and accumulation of vectors and weights in the form of analog semaphores; The pipeline addition tree and the digital shift addition module constitute a partial product shift compression summation module, which performs vector and weight multiplication and accumulation in the form of digital semaphores. The current in each row of the in-memory array is converted into a digital signal by an analog-to-digital converter (ADC). This digital signal is subtracted from the calculation result of the pipelined addition tree to obtain the calculation error of the in-memory array.

2. The low-power test circuit for in-memory computing error as described in claim 1, characterized in that, The digital shift plus module includes a data register DR and a weight register WR; The data register DR is used to shift the input vector data and at the same time provide data ds for each column of the storage array; The function of the weight register WR is to shift the weights and generate a partial product PP of each bit of the data and each bit of the weight.

3. The low-power test circuit for in-memory computing error as described in claim 2, characterized in that, The pipelined addition tree consists of four stages: L0, L1, L2, and L3. The first three stages sum the partial products of all inputs, and the L3 stage accumulates the partial products of all bits.

4. The low-power test circuit for in-memory computing error as described in claim 3, characterized in that, One of the memory computing units F in the memory computing array i,j The weight W is written through external circuitry. i,j The weight W i,j Stored in the memory unit F in the form of analog signals i,j middle; Among them, in the storage unit F i,j When performing weight programming, the weight is written into the weight register WR in the form of a digital semaphore, and the weight W... i,j It is represented by an 8-bit digital value.

5. The low-power test circuit for in-memory computing error as described in claim 4, characterized in that, The column input of the memory array is an N-dimensional vector V = {E0, E1, E2, ..., E...} N-1 }, each element E of the vector k (k = 0, 1, 2, ..., N-1) is represented by an 8-bit digital value; the corresponding elements of the vector V are input to N digital shift-add modules, and the j-th element is written to the digital shift-add module S. j In the middle; given the start signal, the storage array and all digital shift-add modules begin calculating the partial product PP of vector V and N weights. j .

6. The low-power test circuit for in-memory computing error as described in claim 5, characterized in that, The data register DR is an 8-bit shift register that shifts 1 bit to the least significant bit each time; the weight register WR is a 15-bit shift register that shifts 1 bit to the most significant bit each time. If the least significant bit of the data register DR is 1, then all bits of the weight register WR will be used as the partial product output PP. j , If the least significant bit of the data register DR is 0, output PP as a partial product. j .

7. The low-power test circuit for in-memory computing error as described in claim 6, characterized in that, In the pipelined addition tree, in the first-stage pipeline L0, the partial product of each digital shift-add module is output as PP. j Use N / 2 adders to add the products pairwise; In the second-stage pipeline L1, the compressed N / 2 results output from the first-stage pipeline L0 are added pairwise using N / 4 adders; in the third-stage pipeline L2, the compressed N / 4 results output from the second-stage pipeline L1 are added pairwise using N / 8 adders. In the final pipeline L3, one adder is used to obtain the result of the multiplication and addition operation of vector V and N weight values; if N / 2, N / 4, N / 8... cannot be obtained as an integer, the largest integer less than or equal to the result is taken.

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