Method and device for reducing flash error bits, storage control chip and storage medium

Abstract

The application provides a method and device for reducing the number of error bits, a storage control chip and a storage medium. The method comprises the following steps: reading a preset offset voltage of a Flash, and obtaining an error bit number matched with the preset offset voltage; performing right offset adjustment on the preset offset voltage according to a first adjustment method, to obtain a first offset voltage, wherein the error bit number change value of the first offset voltage exceeds a change threshold; performing left offset adjustment on the preset offset voltage according to a second adjustment method, to obtain a second offset voltage, wherein the error bit number change value of the second offset voltage exceeds the change threshold; and obtaining a target offset voltage based on the first offset voltage and the second offset voltage by using the quadratic function characteristic. According to the first offset voltage and the second offset voltage, the target offset voltage is obtained by using the characteristics of the analog quadratic function curve, and the target offset voltage can effectively reduce the number of error bits of the Flash, thereby ensuring the accuracy of the Flash data reading.

Description

Technical Field

[0001] This invention relates to the field of Flash technology, and in particular to a method, apparatus, memory control chip, and memory medium for reducing the number of Flash error bits. Background Technology

[0002] NAND Flash (abbreviated as Flash) is a type of Flash memory. It has advantages such as large capacity and fast rewriting speed, and is suitable for storing large amounts of data. Therefore, it has been increasingly widely used in the industry.

[0003] Flash memory is composed of several storage cells. Flash memory that stores 1 bit of data is called SLC (Single Level Cell); flash memory that stores 2 bits of data is called MLC (Multiple Level Cell); flash memory that stores 3 bits of data is called TLC (Triple Level Cell); and flash memory that stores 4 bits of data is called QLC (Quad Level Cell).

[0004] Over time, electrons stored in the memory cells are lost, causing a change in the threshold voltage of the memory cells, i.e., a shift. Data stored in flash memory chips must be read using this threshold voltage. If data is read using the pre-configured threshold voltage, incorrect data reading will occur. If too many memory cells experience bit flips, the flash memory cannot utilize the ECC error correction capabilities of the memory controller chip to correct the erroneous bits, leading to data errors. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, apparatus, storage control chip and storage medium for reducing the number of Flash error bits, which can achieve a good threshold voltage and ensure the accuracy of Flash data reading.

[0006] The first aspect of this application provides a method for reducing the number of Flash error bits, comprising: Read the preset offset voltage of the Flash memory and obtain the error bit value that matches the preset offset voltage; The preset offset voltage is right-biased according to the first adjustment method. The change value of the error bit value that matches the preset offset voltage after the current adjustment and the error bit value that matches the preset offset voltage after the previous adjustment is calculated to obtain the first offset voltage whose change value exceeds the change threshold. According to the second adjustment method, the preset offset voltage is adjusted to the left, and the change value between the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage is calculated to obtain the second offset voltage whose change value exceeds the change threshold. By utilizing the properties of a quadratic function, the target offset voltage is obtained based on the first offset voltage and the second offset voltage.

[0007] Further, in one preferred embodiment, the step of right-biasing the preset offset voltage according to the first adjustment method, calculating the change in the error bit value matching the currently adjusted preset offset voltage with the error bit value matching the previously adjusted preset offset voltage, and obtaining a first offset voltage where the change value exceeds a change threshold, includes: Configure the right offset step size; Based on the right offset step size, the preset offset voltage is gradually increased, and the adjusted preset offset voltage is matched with the error bit value. Calculate the difference between the number of error bits that match the currently adjusted preset offset voltage and the number of error bits that match the previously adjusted preset offset voltage to obtain several first differences; If the absolute value of the first difference is greater than or equal to the change threshold, then the currently adjusted preset offset voltage is determined to be the first offset voltage.

[0008] Further, in one preferred embodiment, the step of adjusting the preset offset voltage to the left according to the second adjustment method, calculating the change in the error bit value matching the currently adjusted preset offset voltage with the error bit value matching the previously adjusted preset offset voltage, and obtaining a second offset voltage where the change value exceeds a change threshold, includes: Configure the left skew step size; Based on the left offset step size, the preset offset voltage is gradually reduced, and the error bit value that matches the adjusted preset offset voltage is obtained. Calculate the difference between the number of error bits that match the current adjusted preset offset voltage and the number of error bits that match the preset offset voltage before the previous adjustment, and obtain several second differences; If the absolute value of the second difference is greater than or equal to the change threshold, then the currently adjusted preset offset voltage is determined to be the second offset voltage.

[0009] Further, in one preferred embodiment, determining that the currently adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference is greater than or equal to the change threshold includes: If the absolute value of the second difference is greater than or equal to the change threshold, then the preset offset voltage before and after the current adjustment is used as the base point to determine the first objective function; The second objective function is determined by matching the error bit value with the first offset voltage; Calculate the intersection point of the first objective function and the second objective function; Using the intersection point as a base point, locate the perpendicular point of the intersection point on the error bit number curve; The vertical point is used as the second offset voltage.

[0010] A second aspect of this application provides an apparatus for reducing the number of Flash error bits, comprising: The read module is used to read the preset offset voltage of the Flash memory and obtain the error bit value that matches the preset offset voltage. The right bias module is used to right bias the preset offset voltage according to the first adjustment method, calculate the change value of the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain the first offset voltage whose change value exceeds the change threshold. The left bias module is used to adjust the preset offset voltage to the left according to the second adjustment method, calculate the change value between the error bit value that matches the currently adjusted preset offset voltage and the error bit value that matches the previously adjusted preset offset voltage, and obtain a second offset voltage in which the change value exceeds the change threshold. The target module is used to obtain the target offset voltage based on the first offset voltage and the second offset voltage by utilizing the properties of a quadratic function.

[0011] Further, in one preferred embodiment, the right bias module includes: The first long cell is used to configure the right offset step size; The right adjustment unit is used to gradually increase the preset offset voltage according to the right offset step size, and obtain the error bit value that matches the adjusted preset offset voltage. The first calculation unit is used to calculate the difference between the number of error bits that the current adjusted preset offset voltage matches and the number of error bits that the previous adjusted preset offset voltage matches, and obtain several first differences. The first target unit is configured to determine that the adjusted preset offset voltage is the first offset voltage if the absolute value of the first difference is greater than or equal to the change threshold.

[0012] Further, in one preferred embodiment, the left bias module includes: The second step size unit is used to configure the left offset step size; The left adjustment unit is used to gradually reduce the preset offset voltage according to the left offset step size, and obtain the error bit value that matches the adjusted preset offset voltage. The second calculation unit is used to calculate the difference between the number of error bits that the current adjusted preset offset voltage matches and the number of error bits that the previous adjusted preset offset voltage matches, and to obtain several second differences. The second target unit is used to determine that the currently adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference is greater than or equal to the change threshold.

[0013] Further, in one preferred embodiment, the second target unit includes: The first function subunit is used to determine the first objective function by taking the preset offset voltage before and after the current adjustment as the base point if the absolute value of the second difference is greater than or equal to the change threshold. The second function subunit is used to determine the second objective function by matching the error bit value with the first offset voltage; The intersection point calculation subunit is used to calculate the intersection point between the first objective function and the second objective function; The projection subunit is used to locate the perpendicular point of the intersection point on the error bit number curve based on the intersection point as the base point; A confirmation subunit is used to take the vertical point as the second offset voltage.

[0014] The first aspect of this application provides a memory control chip, including: the means described above for reducing the number of Flash error bits.

[0015] A fourth aspect of this application provides a computer-readable storage medium storing executable code that, when executed by a processor of an electronic device, causes the processor to perform the method described above for reducing the number of Flash error bits.

[0016] The technical solution of this application includes: reading a preset offset voltage of the Flash memory and obtaining the error bit value that matches the preset offset voltage; adjusting the preset offset voltage to the right according to a first adjustment method to obtain a first offset voltage where the change in the number of error bits exceeds a change threshold; adjusting the preset offset voltage to the left according to a second adjustment method to obtain a second offset voltage where the change in the number of error bits exceeds a change threshold; and obtaining a target offset voltage based on the first and second offset voltages using the characteristics of a quadratic function. This application obtains the target offset voltage by analogy to a quadratic function curve, based on the obtained first and second offset voltages. The target offset voltage can effectively reduce the number of error bits in the Flash memory and ensure the accuracy of Flash data reading. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for reducing the number of Flash error bits according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of an apparatus for reducing the number of Flash error bits according to an embodiment of this application; Figure 3 The diagram shown is a schematic diagram of the structure of a storage control chip in one embodiment of this application; Figure 4 The diagram shown is a structural schematic of an electronic device according to an embodiment of this application; Figure 5 The graph shown is a curve showing the relationship between offset voltage and the number of error bits. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description of the invention is provided below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0020] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly attached to the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] In related technologies, over time, electrons stored in memory cells are lost, causing a change in the threshold voltage of the memory cells, i.e., a shift. Data stored in flash memory chips must be read using this threshold voltage; if data is read using a pre-configured threshold voltage, incorrect data reading will occur. If too many memory cells experience bit flips, the flash memory cannot utilize the ECC error correction capabilities of the memory controller chip to correct the erroneous bits, leading to data errors.

[0023] Therefore, in order to solve the above-mentioned technical problems, this application provides a method for reducing the number of Flash error bits, which can obtain a good threshold voltage and ensure the accuracy of Flash read data.

[0024] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1 The diagram shown is a flowchart illustrating a method for reducing the number of Flash error bits in one embodiment of this application.

[0026] Please see Figure 1 A method for reducing the number of Flash error bits includes the following steps: Step S110: Read the preset offset voltage of Flash and obtain the error bit value that matches the preset offset voltage.

[0027] Threshold voltage is a key parameter that determines the state of a Flash memory cell. When the memory controller chip sends a read command to the Flash, the Flash needs to perform a read operation based on the pre-configured threshold voltage. Different threshold voltages will result in different data being read from the memory cell.

[0028] The offset voltage is used to adjust the threshold voltage. Adjustments to the threshold voltage are made by configuring the offset voltage. It's understood that the offset voltage can be positive or negative. A positive offset voltage indicates an increase in the threshold voltage for data reading; a negative offset voltage indicates a decrease in the threshold voltage for data reading. The relationship between the threshold voltage and the offset voltage is shown in Equation 1).

[0029] Adjusted threshold voltage V th =Threshold voltage V before adjustment th +Offset voltage V off 1) like Figure 5 The diagram shows the relationship between offset voltage and the number of error bits in Flash memory. Figure 5 The horizontal axis represents different offset voltages, and the vertical axis represents the number of error bits. According to... Figure 5 It can be seen that the relationship curve between the two is analogous to a quadratic function curve, with the lowest point of the curve being the lowest point of the number of error bits, and the curve exhibits symmetry. Furthermore, as the offset voltage increases or decreases, the change in the number of error bits tends to level off. Even if the offset voltage value is subsequently increased or decreased, the impact on the number of error bits is negligible. These characteristics are maintained even after high-temperature aging of the Flash memory. The difference lies in the curve shift, which means that the originally configured threshold voltage may no longer be the optimal voltage reading point. The technical problem to be solved by the technical solution of this embodiment is to obtain this voltage reading point. Combining the characteristic that the relationship curve between offset voltage and the number of error bits is analogous to a quadratic function curve, in this embodiment, the lowest point of the curve can be obtained by first finding the points on both sides of the curve where the change in the number of error bits is most significant, and then using these two points where the change in the number of error bits is most significant on both sides: X T = (X R +X L ) / twenty two) It should be noted that, as Figure 5 Point T shown is the target point, "X" T "" represents the x-coordinate of the target point, i.e., the offset voltage value; X represents the point on the right side of the curve where the change in the number of error bits is most significant; X L That is, the point on the left side of the curve where the change in the number of error bits is most obvious.

[0030] In this embodiment, the preset offset voltage of the Flash memory is read. The preset offset voltage is pre-configured, and for most Flash memory, the voltage value at this point is usually 0V (e.g., ...). Figure 5Point A (as shown) indicates that the threshold voltage was not adjusted, and the Flash read operation was completed using the factory-configured threshold voltage. It's also important to note that both the threshold voltage and the offset voltage are expressed in hexadecimal notation internally within the Flash memory. The corresponding error bit value can be obtained based on the preset offset voltage.

[0031] Step S120: Adjust the preset offset voltage to the right according to the first adjustment method, calculate the change value between the error bit value matched with the current adjusted preset offset voltage and the error bit value matched with the previous adjusted preset offset voltage, and obtain the first offset voltage whose change value exceeds the change threshold.

[0032] It should be noted that in this embodiment, the first offset voltage is obtained in the following way: 1) Configure the right offset step size; 2) Gradually increase the preset offset voltage according to the right offset step size, and obtain the error bit value that matches the adjusted preset offset voltage; 3) Calculate the difference between the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain several first differences; 4) If the absolute value of the first difference is greater than or equal to the change threshold, then the current adjusted preset offset voltage is determined to be the first offset voltage.

[0033] The right offset step size is the voltage value adjusted by the preset offset voltage each time (the value of the right offset step size is configured according to specific circumstances and is not specifically limited here). In this embodiment, the threshold voltage is adjusted by continuously increasing the preset offset voltage, and the error bit value that matches the adjusted preset offset voltage is obtained (equivalent to the error bit value that matches the adjusted threshold voltage).

[0034] To better understand the technical principle of the first adjustment method in this embodiment, the following explanation is based on the specific examples listed in Table 1.

[0035] Number of right deviations Right deviation step length Preset offset voltage Threshold voltage before adjustment Adjusted threshold voltage Error bit count 0 0.1V 0V 2.0V 2.0V 20-bit 1 0.1V 0.1V 2.0V 2.1V 22-bit 2 0.1V 0.2V 2.1V 2.2V 28-bit 3 0.1V 0.3V 2.2V 2.3V 32-bit 4 0.1V 0.4V 2.3V 2.4V 40-bit 5 0.1V 0.5V 2.4V 2.5V 70-bit Table 1 Based on the case in Table 1, the threshold voltage was adjusted a total of 5 times, increasing by 0.1V each time. Each threshold voltage had a corresponding number of error bits. Subsequently, the difference between the number of error bits matching the adjusted preset offset voltage and the number of error bits matching the original preset offset voltage was calculated, resulting in several first differences, as shown in Table 2.

[0036] Number of right deviations First difference 1 2Bit 2 6-bit 3 4-bit 4 8-bit 5 30-bit Table 2 It is understandable that the number of error bits in the Flash changes each time the threshold voltage is adjusted. The system checks if the absolute value of the first difference is greater than or equal to the change threshold. If so, the adjusted preset offset voltage is determined to be the first offset voltage; otherwise, the right skew step size is reconfigured, and steps 1) to 4) are used to locate the first offset voltage. It should be noted that in this embodiment, the change threshold is configured to 20 bits, and the value of the change threshold can be set according to the specific situation of the Flash. Furthermore, due to limited hardware computing power, it is impossible to perform unlimited right skew adjustments to the threshold voltage regardless of cost. In this embodiment, if the first offset voltage is not located after 200 right skew attempts, it is determined that the right skew step size configuration is incorrect and needs to be reconfigured. Steps 1) to 4) are then executed again based on the newly configured right skew step size. Configuring the maximum number of right skew attempts aims to prevent entering an infinite loop, which would prevent obtaining the optimal threshold voltage.

[0037] Upon assessment, when the 5th right-skew adjustment was performed, the first difference (30 bits) was greater than the change threshold (20 bits), meeting the condition. Therefore, the preset offset voltage (0.5V) after the 5th right-skew adjustment was locked as the first offset voltage. Based on the first offset voltage, the threshold voltage (2.5V) was determined to be the rightmost point where the change in the number of Flash error bits was most significant during the right-skew adjustment (e.g., ...). Figure 5 Point B is shown.

[0038] Step S130: Adjust the preset offset voltage to the left according to the second adjustment method, calculate the change value between the error bit value matched with the current adjusted preset offset voltage and the error bit value matched with the previous adjusted preset offset voltage, and obtain the second offset voltage whose change value exceeds the change threshold.

[0039] It should be noted that, similarly, a second adjustment method with the same principle as the first adjustment method is used to obtain the second offset voltage: 5) Configure the left offset step size; 6) According to the left offset step size, gradually reduce the preset offset voltage and obtain the error bit value that matches the adjusted preset offset voltage; 7) Calculate the difference between the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain several second differences; 8) If the absolute value of the second difference is greater than or equal to the change threshold, then the current adjusted preset offset voltage is determined to be the second offset voltage.

[0040] The left offset step size is the voltage value adjusted by the preset offset voltage each time (the value of the left offset step size is configured according to specific circumstances and is not specifically limited here). In this embodiment, the threshold voltage is adjusted by continuously decreasing the preset offset voltage, and the error bit value that matches the adjusted preset offset voltage is obtained (equivalent to the error bit value that matches the adjusted threshold voltage).

[0041] Please provide an explanation using the specific examples listed in Table 3.

[0042] Number of times left deviation Left deviation step length Preset offset voltage Threshold voltage before adjustment Adjusted threshold voltage Error bit count 0 0.2V 0V 2.0V 2.0V 22-bit 1 0.2V -0.2V 2.0V 1.8V 25-bit 2 0.2V -0.4V 1.8V 1.6V 28-bit 3 0.2V -0.6V 1.6V 1.4V 34-bit 4 0.2V -0.8V 1.4V 1.2V 39Bit 5 0.2V -1.0V 1.2V 1.0V 71Bit Table 3 Based on the case in Table 3, the threshold voltage was adjusted a total of 5 times, decreasing by 0.1V each time. Each threshold voltage had a corresponding number of error bits. Subsequently, the difference between the number of error bits matching the adjusted preset offset voltage and the number of error bits matching the original preset offset voltage was calculated, resulting in several second differences, as shown in Table 4.

[0043] Number of times left deviation Second difference 1 3-bit 2 3-bit 3 6-bit 4 5-bit 5 31-bit Table 4 Understandably, similar to right-bias adjustment, the number of error bits in the Flash changes each time the threshold voltage is adjusted to left. It is determined whether the absolute value of the second difference is greater than or equal to the change threshold. If so, the adjusted preset offset voltage is confirmed to be the second offset voltage; otherwise, the right-bias step size is reconfigured, and steps 5) to 8) are used to locate the second offset voltage. Furthermore, the number of left-bias adjustments should be the same as the number of right-bias adjustments; left-bias adjustments cannot be performed indefinitely. In this embodiment, if the second offset voltage is not located after 200 left-bias adjustments, the left-bias step size is determined to be incorrect and needs to be reconfigured. Steps 5) to 8) are then executed again based on the newly configured left-bias step size. Configuring the maximum number of left-bias adjustments also aims to prevent an infinite loop, ultimately preventing the acquisition of the optimal threshold voltage.

[0044] Upon assessment, when the 5th left-skew adjustment was performed, the second difference (31 bits) was greater than the change threshold (20 bits), meeting the condition. Therefore, the preset offset voltage (0.5V) after the 5th left-skew adjustment was locked as the second offset voltage. Based on the second offset voltage, the threshold voltage (1.5V) was determined to be the leftmost point where the change in the number of Flash error bits was most significant during the left-skew adjustment (e.g., ...). Figure 5 Point D is shown.

[0045] Step S140: Using the properties of a quadratic function, the target offset voltage is obtained based on the first offset voltage and the second offset voltage.

[0046] It should be noted that the first adjustment method yields the first target offset voltage; the second adjustment method yields the second target offset voltage. Utilizing the properties of a quadratic function (e.g., formula 2), the target offset voltage can be obtained (e.g., ...). Figure 5 Point K is shown.

[0047] X T = (0.5 ± 1.0) / 2 = -0.25V X will be obtained T Substituting into Formula 1), we obtain the adjusted threshold voltage V. th =2.0-0.25=1.75V. When performing a data read operation under this threshold voltage, the accuracy of Flash data reading can be guaranteed.

[0048] Based on the first and second offset voltages, this application utilizes the relationship between the number of Flash error bits and the offset voltage point, analogous to the characteristics of a quadratic function curve, to obtain the target offset voltage. The target offset voltage can effectively reduce the number of Flash error bits and ensure the accuracy of Flash data reading.

[0049] Further, as a preferred embodiment, the second adjustment method is used to obtain the second target offset voltage, which is as follows: 9) Configure the left offset step size; 10) According to the left offset step size, gradually reduce the preset offset voltage and obtain the error bit value that matches the adjusted preset offset voltage; 11) Calculate the difference between the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain several second differences; 12) If the absolute value of the second difference is greater than or equal to the change threshold, then use the preset offset voltage before and after the current adjustment as the base point to determine the first objective function; 13) Determine the second objective function using the error bit value that matches the first offset voltage; 14) Calculate the intersection point of the first objective function and the second objective function; 15) Based on the intersection point as the base point, locate the perpendicular point of the intersection point on the error bit value curve; 16) Use the perpendicular point as the second offset voltage.

[0050] It should be noted that in this embodiment, the principle of steps 9) to 11) is the same as that of steps 5) to 7), and the principle will not be repeated here. The difference lies in steps 12) to 16). Since the curve showing the relationship between the offset voltage and the number of error bits is symmetrical, when the first offset voltage is obtained using the first adjustment method, according to the symmetry of the curve, the second offset voltage should show a high degree of symmetry with the first offset voltage. However, the right offset step size and the left offset step size may be different, and the second offset voltage is very likely to deviate from the point symmetrical to the first offset voltage by a certain distance. That is, the obtained second offset voltage may not have a high degree of symmetry with the first target offset voltage.

[0051] Therefore, to eliminate this error, when the absolute value of the second difference is determined to be greater than or equal to the change threshold, the preset offset voltage before and after the adjustment is used as the base point to determine the first objective function, i.e., the threshold voltage before and after the 5th left offset adjustment as shown in Table 3, which are (1.2, 39) and (1.0, 71) respectively. Based on these two points, the first objective function Y=KX+b can be determined, as follows. Figure 5As shown, the first objective function is a linear function, and its corresponding graph is a straight line. Subsequently, the second objective function Y=C (C=70) is determined based on the error bit value matched with the first offset voltage, which corresponds to the number of error bits corresponding to the threshold voltage after the 5th left offset adjustment in Table 1. Figure 5 As shown, the second objective function is a constant function, and its corresponding graph is also a straight line perpendicular to the Y-axis. The intersection of these two objective functions is calculated, and using the intersection point as a base point, the perpendicular point of the intersection point to the error bit count curve is located (e.g., ...). Figure 5 Point E (as shown) is used as the second offset voltage.

[0052] This embodiment first determines the target range where the second offset voltage lies. Then, based on the symmetry of the curve, using the first offset voltage as a symmetry point, the second offset voltage is found within the target range. Compared to the previous method of directly using the adjusted preset offset voltage as the second offset voltage, the second offset voltage obtained in this embodiment has a high degree of symmetry with the first offset voltage, and can infinitely approach the symmetry point of the most realistic first offset voltage. Finally, the target offset voltage (point T) is obtained based on the first offset voltage (point B) and the second offset voltage (point E).

[0053] It should be noted that, as Figure 5 The points T and K shown have fewer error bits than K, and are closer to the lowest point of the curve. This proves that by eliminating the error in steps 9) to 16), a target offset voltage that is closer to the lowest point of the curve can be obtained.

[0054] Corresponding to the foregoing method embodiments, this application also provides an apparatus and corresponding embodiments for reducing the number of Flash error bits.

[0055] Figure 2 A schematic diagram of a device for reducing the number of Flash error bits according to an embodiment of this application is shown.

[0056] Please see Figure 2 An apparatus 200 for reducing the number of error bits in Flash memory includes: a read module 210, a right bias module 220, a left bias module 230, and a target module 240. Wherein: The reading module 210 is used to read the preset offset voltage of the Flash and obtain the error bit value that matches the preset offset voltage.

[0057] The right bias module 220 is used to right bias the preset offset voltage according to the first adjustment method, calculate the change value of the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain the first offset voltage whose change value exceeds the change threshold.

[0058] The left bias module 230 is used to adjust the preset offset voltage to the left according to the second adjustment method, calculate the change value between the error bit value matched with the current adjusted preset offset voltage and the error bit value matched with the previous adjusted preset offset voltage, and obtain the second offset voltage whose change value exceeds the change threshold.

[0059] The target module 240 is used to obtain the target offset voltage based on the first offset voltage and the second offset voltage by utilizing the characteristics of a quadratic function.

[0060] Further, please refer to Figure 2 In one preferred embodiment, the right offset module 220 includes: a first step lengthening unit 221, a right adjustment unit 222, a first calculation unit 223, and a first target unit 224. Wherein: The first long unit 221 is used to configure the right offset step size.

[0061] The right adjustment unit 222 is used to gradually increase the preset offset voltage according to the right offset step size, and obtain the error bit value that matches the adjusted preset offset voltage.

[0062] The first calculation unit 223 is used to calculate the difference between the number of error bits that match the currently adjusted preset offset voltage and the number of error bits that match the previously adjusted preset offset voltage, and obtain several first differences.

[0063] The first target unit 224 is used to determine that the adjusted preset offset voltage is the first offset voltage if the absolute value of the first difference is greater than or equal to the change threshold.

[0064] Further, please refer to Figure 2 In one preferred embodiment, the left offset module 230 includes: a second step size unit 231, a left adjustment unit 232, a second calculation unit 233, and a second target unit 234. Wherein: The second step unit 231 is used to configure the left offset step size.

[0065] The left adjustment unit 232 is used to gradually reduce the preset offset voltage according to the left offset step size, and obtain the error bit value that matches the adjusted preset offset voltage.

[0066] The second calculation unit 233 is used to calculate the difference between the number of error bits that match the currently adjusted preset offset voltage and the number of error bits that match the previously adjusted preset offset voltage, and obtain several second differences.

[0067] The second target unit 234 is used to determine that the adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference is greater than or equal to the change threshold.

[0068] Further, please refer to Figure 2 In one preferred embodiment, the second target unit 234 includes: a first function subunit 2341, a second function subunit 2342, an intersection calculation subunit 2343, a projection subunit 2344, and a confirmation subunit 2345. Wherein: The first function subunit 2341 is used to determine the first objective function by taking the preset offset voltage before and after the current adjustment as the base point if the absolute value of the second difference is greater than or equal to the change threshold.

[0069] The second function subunit 2342 is used to determine the second objective function by matching the error bit value with the first offset voltage.

[0070] The intersection calculation subunit 2343 is used to calculate the intersection point of the first objective function and the second objective function.

[0071] Projection subunit 2344 is used to locate the perpendicular point of the intersection point on the error bit number curve based on the intersection point as the base point.

[0072] The confirmation subunit 2345 is used to use the vertical point as the second offset voltage.

[0073] like Figure 3 The diagram shown is a structural schematic of a storage control chip according to an embodiment of this application.

[0074] Please refer to 3, a storage control chip 300, including the above-described device 200 for reducing the number of Flash error bits.

[0075] Based on the first and second offset voltages, this application utilizes the relationship between the number of Flash error bits and the offset voltage point, analogous to the characteristics of a quadratic function curve, to obtain the target offset voltage. The target offset voltage can effectively reduce the number of Flash error bits and ensure the accuracy of Flash data reading.

[0076] Please see Figure 4 Another embodiment of this application illustrates a computing electronic device 400 including a processor 410 and a memory 420.

[0077] The processor 410 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0078] The general-purpose processor can be a microprocessor or any conventional processor. Memory 410 can include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices.

[0079] The ROM can store static data or instructions required by the processor 420 or other modules of the computer. The permanent storage device can be a read-write storage device. The permanent storage device can be a non-volatile storage device that retains stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device uses a high-capacity storage device (e.g., magnetic or optical disk, flash memory) as the permanent storage device.

[0080] In other implementations, the persistent storage device can be a removable storage device (e.g., a floppy disk or optical drive). System memory can be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. System memory can store some or all of the instructions and data required by the processor during runtime.

[0081] In addition, memory 420 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical discs may also be used.

[0082] In some embodiments, memory 420 may include a removable storage device that is readable and / or writable, such as a laser disc (CD), a read-only digital multifunction optical disc (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disc, an ultra-high density optical disc, a flash memory card (e.g., SD card, mini SD card, and Micro-SD card), a magnetic floppy disk, etc. Computer-readable storage media do not contain carrier waves or transient electronic signals transmitted wirelessly or via wire. Executable code is stored on memory 420, which, when processed by processor 410, can cause processor 410 to perform some or all of the methods described above.

[0083] Furthermore, the method according to this application can also be implemented as a computer program or computer program product, which includes computer program code instructions for performing some or all of the steps in the method described above.

[0084] Alternatively, this application may be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or computer program or computer instruction code) thereon, which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform part or all of the steps of the methods described above according to this application.

[0085] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for reducing the number of error bits in Flash memory, characterized in that, include: Read the preset offset voltage of the Flash memory and obtain the error bit value that matches the preset offset voltage; The preset offset voltage is right-biased according to the first adjustment method. The change value of the error bit value that matches the preset offset voltage after the current adjustment and the error bit value that matches the preset offset voltage after the previous adjustment is calculated to obtain the first offset voltage whose change value exceeds the change threshold. According to the second adjustment method, the preset offset voltage is adjusted to the left, and the change value between the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage is calculated to obtain the second offset voltage whose change value exceeds the change threshold. By utilizing the properties of a quadratic function, the target offset voltage is obtained based on the first offset voltage and the second offset voltage.

2. The method for reducing the number of Flash error bits according to claim 1, characterized in that, The step of right-biasing the preset offset voltage according to the first adjustment method, calculating the change in the error bit value matching the currently adjusted preset offset voltage with the error bit value matching the previously adjusted preset offset voltage, and obtaining a first offset voltage where the change value exceeds a change threshold includes: Configure the right offset step size; Based on the right offset step size, the preset offset voltage is gradually increased, and the adjusted preset offset voltage is matched with the error bit value. Calculate the difference between the number of error bits that match the currently adjusted preset offset voltage and the number of error bits that match the previously adjusted preset offset voltage to obtain several first differences; If the absolute value of the first difference is greater than or equal to the change threshold, then the currently adjusted preset offset voltage is determined to be the first offset voltage.

3. The method for reducing the number of Flash error bits according to claim 2, characterized in that, The step of adjusting the preset offset voltage to the left according to the second adjustment method, calculating the change in the error bit value matching the currently adjusted preset offset voltage with the error bit value matching the previously adjusted preset offset voltage, and obtaining the second offset voltage where the change value exceeds the change threshold includes: Configure the left skew step size; Based on the left offset step size, the preset offset voltage is gradually reduced, and the error bit value that matches the adjusted preset offset voltage is obtained. Calculate the difference between the number of error bits that match the current adjusted preset offset voltage and the number of error bits that match the preset offset voltage before the previous adjustment, and obtain several second differences; If the absolute value of the second difference is greater than or equal to the change threshold, then the currently adjusted preset offset voltage is determined to be the second offset voltage.

4. The method for reducing the number of Flash error bits according to claim 3, characterized in that, The step of determining that the currently adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference is greater than or equal to the change threshold includes: If the absolute value of the second difference is greater than or equal to the change threshold, then the preset offset voltage before and after the current adjustment is used as the base point to determine the first objective function; The second objective function is determined by matching the error bit value with the first offset voltage; Calculate the intersection point of the first objective function and the second objective function; Using the intersection point as a base point, locate the perpendicular point of the intersection point on the error bit number curve; The vertical point is used as the second offset voltage.

5. An apparatus for reducing the number of error bits in Flash memory, characterized in that, include: The read module is used to read the preset offset voltage of the Flash memory and obtain the error bit value that matches the preset offset voltage. The right bias module is used to right bias the preset offset voltage according to the first adjustment method, calculate the change value of the error bit value that matches the current adjusted preset offset voltage and the error bit value that matches the previous adjusted preset offset voltage, and obtain the first offset voltage whose change value exceeds the change threshold. The left bias module is used to adjust the preset offset voltage to the left according to the second adjustment method, calculate the change value between the error bit value that matches the currently adjusted preset offset voltage and the error bit value that matches the previously adjusted preset offset voltage, and obtain a second offset voltage in which the change value exceeds the change threshold. The target module is used to obtain the target offset voltage based on the first offset voltage and the second offset voltage by utilizing the properties of a quadratic function.

6. The apparatus for reducing the number of Flash error bits according to claim 5, characterized in that, The right offset module includes: The first long cell is used to configure the right offset step size; The right adjustment unit is used to gradually increase the preset offset voltage according to the right offset step size, and obtain the error bit value that matches the adjusted preset offset voltage. The first calculation unit is used to calculate the difference between the number of error bits that the current adjusted preset offset voltage matches and the number of error bits that the previous adjusted preset offset voltage matches, and obtain several first differences. The first target unit is configured to determine that the adjusted preset offset voltage is the first offset voltage if the absolute value of the first difference is greater than or equal to the change threshold.

7. The apparatus for reducing the number of Flash error bits according to claim 6, characterized in that, The left offset module includes: The second step size unit is used to configure the left offset step size; The left adjustment unit is used to gradually reduce the preset offset voltage according to the left offset step size, and obtain the error bit value that matches the adjusted preset offset voltage. The second calculation unit is used to calculate the difference between the number of error bits that the current adjusted preset offset voltage matches and the number of error bits that the previous adjusted preset offset voltage matches, and to obtain several second differences. The second target unit is used to determine that the currently adjusted preset offset voltage is the second offset voltage if the absolute value of the second difference is greater than or equal to the change threshold.

8. The apparatus for reducing the number of Flash error bits according to claim 7, characterized in that, The second target unit includes: The first function subunit is used to determine the first objective function by taking the preset offset voltage before and after the current adjustment as the base point if the absolute value of the second difference is greater than or equal to the change threshold. The second function subunit is used to determine the second objective function by matching the error bit value with the first offset voltage; The intersection point calculation subunit is used to calculate the intersection point between the first objective function and the second objective function; The projection subunit is used to locate the perpendicular point of the intersection point on the error bit number curve based on the intersection point as the base point; A confirmation subunit is used to take the vertical point as the second offset voltage.

9. A storage control chip, comprising: The apparatus for reducing the number of Flash error bits according to any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The device stores executable code that, when executed by a processor of an electronic device, causes the processor to perform the method for reducing the number of Flash error bits as described in any one of claims 1 to 4.

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