Bridged packaging methods and packaging structures

Abstract

This application provides a bridging packaging method and packaging structure. The method includes providing a substrate with a first conductive post; one end of the first conductive post is flush with a first surface of the substrate, and the other end is embedded in the substrate. A first mounting groove is formed on one side of the first surface of the substrate, and a first chip is mounted in the first mounting groove. The first chip includes a body portion and a flange layer connected to the body portion, with the edge of the flange layer extending beyond the edge of the body portion. The body portion is located in the first mounting groove, and the portion of the flange layer extending beyond the body portion overlaps the first surface. A first wiring layer electrically connected to the first conductive post is formed on one side of a second surface, and a second wiring layer electrically connected to the first conductive post is formed on one side of the first surface. The first chip is electrically connected to at least one of the first wiring layer and the second wiring layer. By using a first chip with a flange layer, warpage deformation during the packaging process can be effectively improved, thereby enhancing the packaging quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a bridging packaging method and packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet technology employs a new design approach to package small chips with different functions together, forming a heterogeneous integrated chip packaging structure. Silicon bridge technology achieves electrical connections between chips by embedding small bridge chips with multiple RDLs (redistribution layers) in a substrate, effectively reducing manufacturing costs while maintaining high-density interconnect capabilities. The substrates contain different materials, some organic and some inorganic. Their coefficients of thermal expansion and elastic moduli (Young's modulus) are inconsistent, making them susceptible to thermal stress that can cause delamination of the interface layers, thus affecting product performance. Summary of the Invention

[0003] The purpose of this invention is to provide a bridging packaging method and packaging structure that can effectively improve warpage deformation in the packaging process and improve packaging quality.

[0004] In a first aspect, the present invention provides a bridging packaging method, comprising:

[0005] A substrate is provided; wherein a first conductive pillar is provided within the substrate; the substrate has a first surface and a second surface disposed opposite to each other; one end of the first conductive pillar is flush with the first surface, and the other end is embedded within the substrate;

[0006] A first mounting groove is formed on one side of the first surface of the substrate;

[0007] The first mounting groove is filled with a semi-cured first colloid;

[0008] A first chip is mounted in the first mounting slot; wherein the first chip includes a main body and a flange layer connected to one end of the main body, the edge of the flange layer extending beyond the edge of the main body; the main body is located in the first mounting slot, and the portion of the flange layer extending beyond the main body overlaps the first surface;

[0009] Grind the second surface until the end of the first conductive post near the second surface is exposed;

[0010] A first wiring layer electrically connected to the first conductive post is formed on one side of the second surface;

[0011] A second wiring layer electrically connected to the first conductive pillar is formed on one side of the first surface;

[0012] The first chip is electrically connected to at least one of the first wiring layer and the second wiring layer.

[0013] In an optional embodiment, the first chip includes a third surface and a fourth surface disposed opposite to each other; the third surface is provided with a first electrical connection portion, and the flange layer is disposed on the fourth surface; the first chip is provided with a second conductive post connected to the first electrical connection portion; one end of the second conductive post away from the first electrical connection portion extends toward the fourth surface and does not exceed the fourth surface.

[0014] In an optional embodiment, during the step of grinding the second surface, the first electrical connection and the first conductive post are exposed, with the end face of the first electrical connection facing the second surface and the end face of the first conductive post facing the second surface being flush.

[0015] In the step of forming a first wiring layer that is electrically connected to the first conductive post on one side of the second surface: the first electrical connection portion and the first wiring layer are electrically connected.

[0016] In an optional embodiment, the step of forming a second wiring layer electrically connected to the first conductive post on one side of the first surface includes:

[0017] The fourth surface of the first chip is ground or a window is made to expose the second conductive pillar;

[0018] The second wiring layer is electrically connected to the first conductive post and the second conductive post, respectively.

[0019] In an optional embodiment, the flange layer has a sealant portion on the side facing the third surface;

[0020] The step of mounting the first chip in the first mounting slot includes:

[0021] The first chip squeezes the first adhesive to cause a portion of the first adhesive to overflow onto the first surface; the flange layer is fixed to the first surface using the overflowed first adhesive, and the adhesive-blocking portion is used to prevent the overflowed first adhesive from spreading to areas outside the flange layer.

[0022] In an optional embodiment, the step of forming a second wiring layer electrically connected to the first conductive post on one side of the first surface includes:

[0023] Grinding removes the flange layer so that the end face of the second conductive post facing the first surface is flush with the end face of the first conductive post facing the first surface.

[0024] A second wiring layer is formed; the first conductive post and the second conductive post are electrically connected to the second wiring layer respectively.

[0025] In an optional embodiment, before the step of mounting the first chip in the first mounting slot, the method further includes: preparing the first chip;

[0026] The steps for fabricating the first chip include:

[0027] A wafer is provided; a second conductive pillar is provided inside the wafer; the wafer includes a third surface and a fourth surface disposed opposite to each other; one end face of the second conductive pillar is flush with the third surface, and the other end face is embedded in the wafer;

[0028] A first electrical connection portion that is electrically connected to the second conductive post is formed on the third surface;

[0029] Thinning the wafer from the fourth surface;

[0030] The wafer is cut to separate it into the first chip.

[0031] In an optional embodiment, the first electrical connection includes a connected third wiring layer and a third conductive post; the step of forming the first electrical connection electrically connected to the second conductive post on the third surface includes:

[0032] A third wiring layer electrically connected to the second conductive pillar is formed on the third surface;

[0033] The third conductive post is formed on the third wiring layer; the third conductive post and the third wiring layer are electrically connected.

[0034] In an optional implementation, the step of dicing the wafer to separate it into the first chip includes:

[0035] The wafer is first cut to a depth less than the thickness of the wafer, forming a separation groove;

[0036] The bottom of the separation groove is cut a second time, with a preset distance between the cutting position and the groove wall, forming a single first chip with a flange layer.

[0037] In a second aspect, the present invention provides a packaging structure, prepared using the bridging packaging method as described in any of the foregoing embodiments, the packaging structure comprising:

[0038] A substrate having a first conductive pillar therein; the substrate having a first surface and a second surface disposed opposite to each other; one end of the first conductive pillar being flush with the first surface and the other end being flush with the second surface;

[0039] A first chip has a third surface and a fourth surface disposed opposite to each other; the chip is provided with a first electrical connection portion and a second conductive post that are electrically connected; the end face of the first electrical connection portion away from the second conductive post is flush with the second surface, and the end face of the second conductive post away from the first electrical connection portion is flush with the first surface.

[0040] A first wiring layer is disposed on the second surface and is electrically connected to the first conductive post and the first electrical connection portion, respectively.

[0041] A second wiring layer is disposed on the first surface and is electrically connected to the first conductive post and the second conductive post, respectively.

[0042] In an optional embodiment, the first electrical connection portion includes a third conductive post, which is electrically connected to the second conductive post; or, the first electrical connection portion includes a connected third conductive post and a third wiring layer, wherein the side of the third wiring layer away from the third conductive post is electrically connected to the second conductive post.

[0043] In an optional embodiment, a pad is further included; the pad is disposed at the end of the second conductive post away from the first electrical connection portion, and the pad is electrically connected to the second conductive post and the second wiring layer respectively;

[0044] And / or, the pad is located at the end of the first electrical connection portion away from the second conductive post, and the pad is electrically connected to the first electrical connection portion and the first wiring layer respectively.

[0045] In an optional embodiment, the first wiring layer is electrically connected to a first solder ball; the second wiring layer is electrically connected to a second solder ball;

[0046] A second chip is connected to one side of the first solder ball and / or one side of the second solder ball; the second chip is encapsulated in a molding compound.

[0047] In an optional embodiment, a third chip is also included; the molding compound encapsulates the third chip, which is a dummy chip; the third chip is not electrically connected to the first wiring layer or the second wiring layer.

[0048] The bridging packaging method and packaging structure provided in this invention have the following advantages:

[0049] The bridging packaging method and packaging structure provided in this invention embeds a first chip in a substrate, and the first chip has a flange layer that overlaps with a first surface of the substrate. During the thermal process, the flange layer provides support and prevents warping, effectively improving warping deformation during the packaging process, enhancing packaging quality, and ultimately improving product performance. Attached Figure Description

[0050] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0051] Figure 1 One of the process diagrams for the bridging packaging method provided in the embodiments of the present invention;

[0052] Figure 2 This is a schematic diagram of a first structure of the first chip in the bridging packaging method provided in an embodiment of the present invention.

[0053] Figure 3 for Figure 2 A schematic diagram of the structure in which the first chip is mounted on the substrate;

[0054] Figure 4 This is a schematic diagram of a second structure of the first chip in the bridging packaging method provided in an embodiment of the present invention.

[0055] Figure 5 for Figure 4 A schematic diagram of the structure in which the first chip is mounted on the substrate;

[0056] Figure 6 This is a second schematic diagram of the manufacturing process of the bridging packaging method provided in an embodiment of the present invention;

[0057] Figure 7 The third schematic diagram of the manufacturing process of the bridging packaging method provided in the embodiment of the present invention;

[0058] Figure 8 Fourth schematic diagram of the manufacturing process of the bridging packaging method provided in the embodiments of the present invention;

[0059] Figure 9 One of the process diagrams for another bridging packaging method provided in an embodiment of the present invention;

[0060] Figure 10 A second schematic diagram of the manufacturing process of another bridging packaging method provided in an embodiment of the present invention;

[0061] Figure 11 This is one of the process diagrams for fabricating the first chip in the bridging packaging method provided in the embodiments of the present invention;

[0062] Figure 12 This is a second schematic diagram of the process for fabricating the first chip in the bridging packaging method provided in this embodiment of the invention;

[0063] Figure 13 A schematic diagram of the first packaging structure provided in an embodiment of the present invention;

[0064] Figure 14 A schematic diagram of the second packaging structure provided in an embodiment of the present invention;

[0065] Figure 15 The packaging structure provided in this embodiment of the invention includes a schematic diagram of a third chip.

[0066] Icons: 100 - Package structure; 110 - Substrate; 111 - First surface; 112 - Second surface; 113 - First conductive pillar; 114 - First mounting groove; 115 - First colloid; 120 - First chip; 121 - Main body; 122 - Flange layer; 1221 - Adhesive barrier; 123 - Third surface; 124 - Fourth surface; 125 - First electrical connection; 1251 - Third wiring layer; 1252 - Third conductive pillar; 126 - Second conductive pillar; 130 - First carrier; 131-Bonding adhesive layer; 133-Second carrier; 141-First dielectric layer; 142-First wiring layer; 143-Second dielectric layer; 144-First bump; 145-First solder ball; 161-Second chip; 162-Molded package; 163-Second colloid; 164-Third chip; 171-Third dielectric layer; 172-Second wiring layer; 173-Fourth dielectric layer; 174-Second solder ball; 175-Metal layer; 180-Wafer; 181-Separation groove; 190-Pad. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0068] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0069] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0070] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0071] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0072] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0073] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0074] This invention proposes a bridging packaging method that embeds a first chip within a substrate to achieve high-density packaging. Furthermore, the first chip has a flange layer, which provides support and prevents warping during the packaging process, effectively mitigating warping deformation, preventing structural delamination or cracking, improving packaging quality, and ultimately enhancing product performance.

[0075] Please combine Figure 1 The bridging encapsulation method mainly includes the following steps:

[0076] S1. A substrate 110 is provided; a first conductive post 113 is provided within the substrate 110; the substrate 110 has a first surface 111 and a second surface 112 disposed opposite to each other; one end of the first conductive post 113 is flush with the first surface 111, and the other end is embedded in the substrate 110. The substrate 110 is made of silicon-based or germanium-based substrate, or is made of, but not limited to, silicon oxide, phosphosilicate glass, fluorinated glass, or glass. Alternatively, the substrate 110 may also be made of molding compound material, such as ABF resin, epoxy resin, spherical silicon micropowder, or polymer. The thickness of the substrate 110 is approximately 600um-1500um. The first conductive post 113 may be fabricated using a TSV through-hole process.

[0077] S2. A first mounting groove 114 is formed on one side of the first surface 111 of the substrate 110. Optionally, the first mounting groove 114 is formed on the first surface 111 of the substrate 110 by means of dry etching or chemical etching, and the first mounting groove 114 is used to mount the first chip 120.

[0078] S3. Mount the first chip 120. This includes steps S31 and S32.

[0079] S31. A semi-cured first colloid 115 is filled into the first mounting groove 114. Optionally, a liquid first colloid 115 is filled into the first mounting groove 114 using a coating process. The first colloid 115 is heated and baked to a semi-cured state. The baking temperature is approximately 50 to 80 degrees Celsius, and the baking time is approximately 5 to 15 minutes, so that the first colloid 115 becomes a film, i.e., a semi-cured state.

[0080] Please combine Figure 2 and Figure 3 S32. A first chip 120 is mounted in the first mounting groove 114. The first chip 120 includes a main body 121 and a flange layer 122 connected to one end of the main body 121, with the edge of the flange layer 122 extending beyond the edge of the main body 121. The main body 121 is located in the first mounting groove 114, and the portion of the flange layer 122 extending beyond the main body 121 overlaps with the first surface 111 of the substrate 110.

[0081] Optionally, during the mounting process, the first chip 120 is pressed into the first adhesive 115 of the first mounting groove 114 using a mounting head. The vacuum in the first mounting groove 114 is removed, ensuring that the first adhesive 115 is pressed into the groove without voids. During the pressing of the first chip 120, the first adhesive 115 overflows from the opening of the first mounting groove 114 onto the first surface 111 of the substrate 110. The overflowing first adhesive 115 contacts the flange layer 122 of the first chip 120, thus achieving adhesion. It can be understood that the gap between the main body 121 of the first chip 120 and the groove wall of the first mounting groove 114 is filled with the first adhesive 115, achieving adhesion to the main body 121. The first adhesive 115 overflowing from the opening of the first mounting groove 114 achieves adhesion and fixation to the flange layer 122. Afterwards, the first adhesive 115 is heated and baked. The baking temperature is 120 to 180 degrees Celsius, and the baking time is 15 to 30 minutes, so that the first colloid 115 is completely cured.

[0082] Optionally, the first chip 120 includes a third surface 123 and a fourth surface 124 disposed opposite to each other. The third surface 123 has a first electrical connection portion 125, and a flange layer 122 is disposed on the fourth surface 124. The first chip 120 has a second conductive post 126 connected to the first electrical connection portion 125. One end of the second conductive post 126 away from the first electrical connection portion 125 extends toward the fourth surface 124 but does not exceed the fourth surface 124. In this embodiment, the first electrical connection portion 125 includes a connected third wiring layer 1251 and a third conductive post 1252. The side of the third wiring layer 1251 away from the third conductive post 1252 is electrically connected to the second conductive post 126.

[0083] Combination Figure 4 and Figure 5 Optionally, the flange layer 122 has an annular adhesive barrier 1221 on the side facing the third surface 123. During the mounting of the first chip 120, the first adhesive 115 is compressed, causing a portion of the first adhesive 115 to overflow onto the first surface 111 of the substrate 110. The flange layer 122 is fixed to the first surface 111 by the overflowed first adhesive 115, and the adhesive barrier 1221 prevents the overflowed first adhesive 115 from diffusing outside the flange layer 122. Furthermore, during vacuuming, the adhesive barrier 1221 prevents the first adhesive 115 from overflowing onto the back side of the flange layer 122. Optionally, when the substrate 110 uses a molding compound material, the first adhesive 115 is made of the same material as the substrate 110 to mitigate deformation and warping caused by differences in thermal expansion coefficients.

[0084] S4. Grind the second surface 112 until the end face of the first conductive post 113 near the second surface 112 is exposed.

[0085] Combination Figure 6 and Figure 7Optionally, a first carrier 130 is taken, and a debondable bonding adhesive layer 131 is coated on the surface of the first carrier 130. The bonding adhesive layer 131 can be separated from the first carrier 130 by irradiation with ultraviolet light or by laser debonding.

[0086] The first surface 111 of the substrate 110 is attached to the first carrier 130. The second surface 112 of the substrate 110 faces upward. The second surface 112 is then polished. In this embodiment, a two-stage polishing process is employed. The first stage is coarse polishing, which uses mechanical polishing to reduce the thickness of the substrate 110. The second stage is fine polishing, which uses chemical polishing. In the chemical polishing process, polishing fluids such as ammonia, hydrofluoric acid, or citric acid are used to polish the second surface 112 of the substrate 110 under the pressure of a polishing pad and centrifugal force, thereby exposing the end face of the first conductive post 113 near the second surface 112. It can be understood that the chemical polishing fluid can remove free metal ions from the surface of the substrate 110, thus cleaning the surface.

[0087] In this embodiment, the plane of the bottom of the first mounting groove 114 and the end face of the first conductive post 113 near the second surface 112 are on the same plane. After the first chip 120 is mounted, the end face of the first conductive post 113 near the second surface 112 and the end face of the third conductive post 1252 are on the same plane. In this way, while grinding the second surface 112 to expose the first conductive post 113, the third conductive post 1252 of the first chip 120 can also be exposed, which facilitates the subsequent electrical connection of the first wiring layer 142 to the first conductive post 113 and the third conductive post 1252 respectively.

[0088] S5. A first wiring layer 142 electrically connected to the first conductive post 113 is formed on one side of the second surface 112.

[0089] Optionally, a first dielectric layer 141 is formed on the second surface 112 using a spin coating or spray coating process. The material of the first dielectric layer 141 includes, but is not limited to, polyimide, benzocyclobutene, etc. A photomask with a patterned layer is placed over the first dielectric layer 141. A first patterned opening is formed on the first dielectric layer 141 using an exposure and development process, and metal is filled into the first patterned opening using electroplating, sputtering, or chemical plating to form a first wiring layer 142.

[0090] A second dielectric layer 143 is formed on the first dielectric layer 141 using a spin coating or spray coating process. The material of the second dielectric layer 143 includes, but is not limited to, polyimide, benzocyclobutene, etc. A photomask with a patterned layer is placed over the second dielectric layer 143. A first opening is formed on the second dielectric layer 143 using an exposure and development process, exposing the first wiring layer 142. Metal is filled into the first opening using electroplating, sputtering, or chemical plating to form a first solder ball 145. Specifically, metal is first electroplated into the first opening to form a first bump 144, which is electrically connected to the first wiring layer 142. Optionally, the first bump is made of copper pillar. Formic acid is used as a reducing agent to remove oxides from the surface of the first bump 144 through high temperature and chemical reaction, which helps to promote the bonding force between the first bump 144 and the solder. Then, at least one of titanium, titanium-tungsten, nickel, tin-silver, tin-silver-copper, and tin-bismuth is electroplated onto the surface of the first bump 144 to form the first solder ball 145.

[0091] S6. Attach the second chip 161 to one side of the first wiring layer 142.

[0092] Optionally, the second chip 161 is mounted onto the first solder ball 145 using a hot-press bonding process or a flip-chip bonding process. A second adhesive 163 is formed using a dispensing process to protect the solder structure at the first solder ball 145. A molding compound 162 encapsulating the second chip 161 is formed on the second dielectric layer 143 using a molding compound process.

[0093] Remove the first carrier 130. Optionally, debond the first carrier 130 and the substrate 110 by irradiating with ultraviolet light. It should be noted that after removing the first carrier 130, the flange layer 122 of the first chip 120 can provide support, preventing stress contraction of the molding compound 162 after the removal of the first carrier 130, thereby preventing warping of the substrate 110. If the substrate 110 uses a molding compound material, stress contraction of the molding compound 162 and the molding compound material of the substrate 110 can be avoided after the removal of the first carrier 130, thus preventing warping deformation. It should be understood that a high elastic modulus means that the material is not easily elastically deformed when subjected to external forces. The substrate 110 with a silicon interposer has a high Young's modulus, reaching 160 GPa to 190 GPa. The Young's modulus of the molding compound 162 is greatly affected by temperature changes. For example, the Young's modulus of the molding compound 162 at 25°C is between 3 GPa and 6 GPa. At a curing temperature such as 260°C, the Young's modulus of the molding compound 162 will decrease to about 1 GPa to 3 GPa. Therefore, the molding compound 162 is prone to deformation and warping.

[0094] S7. A second wiring layer 172 electrically connected to the first conductive post 113 is formed on one side of the first surface 111.

[0095] Optionally, the substrate 110 is flipped so that the first surface 111 faces upward. The flange layer 122 of the first chip 120 is removed by grinding, exposing the second conductive pillar 126 from the first surface 111. A third dielectric layer 171, a second wiring layer 172, a fourth dielectric layer 173, and a second solder ball 174 are formed on the first surface 111. The process steps are similar to step S5 described above and will not be repeated here.

[0096] S8. Using a cutting process, the packaged product is cut and separated into individual products to complete the manufacturing process. Please refer to... Figure 8 .

[0097] It should be noted that in some embodiments, the second chip 161 may also be mounted on one side of the second wiring layer 172, or the second chip 161 may be mounted on both sides of the substrate 110 (one side of the first wiring layer 142 and one side of the second wiring layer 172), without specific limitations.

[0098] Please combine Figure 9 and Figure 10 Optionally, before step S7, a second carrier 133 is mounted on one side of the first solder ball 145, and after step S7 is completed, the second carrier 133 is removed. Optionally, after forming the second wiring layer 172 and the metal layer 175, the second carrier 133 is removed, and a second chip 161 is mounted on one side of the first wiring layer 142 and encapsulated. Then, second solder balls 174 are formed on the metal layer 175, and the chips are cut and separated into individual products.

[0099] If the second chip 161 is mounted only on the second wiring layer 172 side, the process steps are: S1 to S5, S7, S6, S8.

[0100] If the second chip 161 is mounted on both sides of the substrate 110, the process steps are: S1 to S7, S6, and S8. In this embodiment, the second chip 161 is mounted on the side of the first chip 120 that has the third conductive post 1252.

[0101] Optionally, in the step of removing the flange layer 122 of the first chip 120, after removing the flange layer 122, the end face of the second conductive post 126 away from the first electrical connection portion 125 is exposed, and the end face of the second conductive post 126 facing the first surface 111 and the end face of the first conductive post 113 facing the first surface 111 are flush. This facilitates the electrical connection of the second wiring layer 172 with the first conductive post 113 and the second conductive post 126 respectively.

[0102] The first chip 120 is electrically connected to at least one of the first wiring layer 142 and the second wiring layer 172. In this embodiment, the first chip 120 is electrically connected to both the first wiring layer 142 and the second wiring layer 172.

[0103] In this embodiment, the fabrication method of the first chip 120 is roughly as follows:

[0104] Please combine Figure 11 and Figure 12 A wafer 180 is provided. A second conductive post 126 is provided within the wafer 180. The wafer 180 includes a third surface 123 and a fourth surface 124 disposed opposite to each other; one end face of the second conductive post 126 is flush with the third surface 123, and the other end face is embedded within the wafer 180. A first electrical connection portion 125 electrically connected to the second conductive post 126 is formed on the third surface 123. The first electrical connection portion 125 includes a connected third wiring layer 1251 and a third conductive post 1252. The step of forming the first electrical connection portion 125 electrically connected to the second conductive post 126 on the third surface 123 includes:

[0105] A third wiring layer 1251 electrically connected to the second conductive post 126 is formed on the third surface 123. A third conductive post 1252 is formed on the third wiring layer 1251; the third conductive post 1252 and the third wiring layer 1251 are electrically connected. The process for forming the third wiring layer 1251 can refer to the process in step S5 above, and the method for forming the third conductive post 1252 can adopt the process for forming the first bump 144 in step S5, which will not be described again here.

[0106] The wafer 180 is thinned from the fourth surface 124; then the wafer 180 is diced to separate it into individual first chips 120. The dicing process can employ two dicing steps to form a flange layer 122 on one side of the fourth surface 124. Optionally, the wafer 180 is diced for the first time to a depth less than the thickness of the wafer 180, forming a separation groove 181. The difference between the dicing depth and the thickness of the wafer 180 is the thickness of the flange layer 122. The bottom of the separation groove 181 is diced for the second time, with a predetermined distance between the dicing position and the groove wall. This predetermined distance is the extension width of the flange layer 122 beyond the main body 121 of the first chip 120. This process forms a single first chip 120 with the flange layer 122.

[0107] Please combine Figure 13 This invention also provides a packaging structure 100, fabricated using the bridging packaging method described in any of the foregoing embodiments. The packaging structure 100 includes: a substrate 110, a first chip 120, a first wiring layer 142, and a second wiring layer 172. A first conductive post 113 is provided within the substrate 110; the substrate 110 has a first surface 111 and a second surface 112 disposed opposite to each other. One end of the first conductive post 113 is flush with the first surface 111, and the other end is flush with the second surface 112.

[0108] A first chip 120 is embedded in a substrate 110. The first chip 120 has a third surface 123 and a fourth surface 124 disposed opposite to each other. The first chip 120 has a first electrical connection portion 125 and a second conductive post 126 electrically connected. The end face of the first electrical connection portion 125 away from the second conductive post 126 is flush with the second surface 112, and the end face of the second conductive post 126 away from the first electrical connection portion 125 is flush with the first surface 111. A first wiring layer 142 is disposed on the second surface 112 and is electrically connected to the first conductive post 113 and the first electrical connection portion 125, respectively. A second wiring layer 172 is disposed on the first surface 111 and is electrically connected to the first conductive post 113 and the second conductive post 126, respectively. By embedding the first chip 120 in the substrate 110, high-density packaging can be achieved, improving product integration. Furthermore, it can improve the warpage deformation of the substrate 110 and the molding compound 162 during the packaging process, improving packaging quality and product performance.

[0109] Optionally, the first electrical connection portion 125 includes a third conductive post 1252, which is electrically connected to the second conductive post 126. Alternatively, the first electrical connection portion 125 includes a connected third conductive post 1252 and a third wiring layer 1251, with the side of the third wiring layer 1251 away from the third conductive post 1252 electrically connected to the second conductive post 126. The third wiring layer 1251 may be omitted in some embodiments.

[0110] Please combine Figure 14 Optionally, the package structure 100 further includes a pad 190 electrically connected to the second conductive post 126, and the second wiring layer 172 is electrically connected to the pad 190. The pad 190 can increase the electrical contact area of ​​the second conductive post 126 and the second wiring layer 172, thereby improving electrical connection performance. The pad 190 can be formed during the fabrication of the first chip 120, or it can be formed after the first chip 120 is mounted and before the fabrication of the second wiring layer 172; no specific limitation is made here. It is understood that in some embodiments, the pad 190 can be located at the end of the first electrical connection portion 125 away from the second conductive post 126, and the pad 190 is electrically connected to the first wiring layer 142. Alternatively, pads 190 can be provided on both sides of the second conductive post 126 and the third conductive post 1252 to improve electrical connection performance.

[0111] Of course, in some embodiments, pads 190 can also be provided on any one or both end faces of the first conductive post 113. The pads 190 are used to connect with the wiring layer, thereby increasing the contact area between the first conductive post 113 and the wiring layer and thus improving the electrical connection performance.

[0112] Optionally, the first wiring layer 142 is electrically connected to a first bump 144, and the first bump 144 is electrically connected to a first solder ball 145. The second wiring layer 172 is electrically connected to a metal layer 175, and the metal layer 175 is electrically connected to a second solder ball 174. A second chip 161 is connected to one side of the first solder ball 145 and / or one side of the second solder ball 174; the molding compound 162 covers the second chip 161. This allows the second chip 161 to be mounted on either side or both sides of the substrate 110, with the first chip 120 and the second chip 161 interconnected, improving integration and achieving high-density packaging.

[0113] Please combine Figure 15 Optionally, in some embodiments, the package structure 100 further includes a third chip 164. The third chip 164 is a dummy chip. The dummy chip is also mounted during the mounting of the second chip 161. The dummy chip has no electrical connection to either the first wiring layer 142 or the second wiring layer 172. The second molding compound 162 simultaneously encapsulates both the second chip 161 and the dummy chip. The material of the third chip 164 can be any one or more of silicon-based, germanium-based, ceramic, glass, aluminum sheet, and gallium nitride. The dummy chip can improve heat dissipation and support performance, as well as alleviate warpage caused by molding stress. Optionally, if the substrate 110 is made of a molding compound material, a dummy chip can be disposed within the substrate 110 to further prevent structural warpage.

[0114] Optionally, the first chip 120 can be a device such as an inductor, voltage regulator, resistor, capacitor, transistor, or diode. The first chip 120 is designed with an active wiring layer and a second conductive pillar 126. The flange layer 122 of the first chip 120 is made of chip material. The flange layer 122 of the first chip 120 provides support, thereby preventing warping of the substrate 110 structure after the carrier is removed. It should be understood that in some embodiments, the third wiring layer 1251 may also be omitted.

[0115] The bridging packaging method and packaging structure 100 provided in this embodiment of the invention have the following beneficial effects:

[0116] The bridging packaging method and packaging structure 100 provided in this embodiment of the invention employ a first chip 120 with a flange layer 122 embedded in a substrate 110 during the packaging process, thereby improving the chip integration and facilitating high-density packaging with a compact structure. Furthermore, it helps to mitigate warpage deformation of the substrate 110 and the molding compound 162 during the packaging process, improving packaging quality and product performance.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A bridging packaging method, characterized in that, include: A substrate is provided; wherein a first conductive pillar is provided within the substrate; The substrate has a first surface and a second surface disposed opposite to each other; one end of the first conductive post is flush with the first surface, and the other end is embedded in the substrate; A first mounting groove is formed on one side of the first surface of the substrate; The first mounting groove is filled with a semi-cured first colloid; A first chip is mounted in the first mounting slot; wherein the first chip includes a main body and a flange layer connected to one end of the main body, the edge of the flange layer extending beyond the edge of the main body; the main body is located in the first mounting slot, and the portion of the flange layer extending beyond the main body overlaps the first surface; the flange layer has an adhesive-blocking portion on the side facing the first surface; the first chip compresses the first adhesive, causing a portion of the first adhesive to overflow onto the first surface; the flange layer is fixed to the first surface by the overflowed first adhesive, and the adhesive-blocking portion is used to prevent the overflowed first adhesive from spreading to areas outside the flange layer. Grind the second surface until the end of the first conductive post near the second surface is exposed; A first wiring layer electrically connected to the first conductive pillar is formed on one side of the second surface; A second wiring layer electrically connected to the first conductive pillar is formed on one side of the first surface; The first chip is electrically connected to at least one of the first wiring layer and the second wiring layer.

2. The bridging packaging method according to claim 1, characterized in that, The first chip includes a third surface and a fourth surface disposed opposite to each other; the third surface is provided with a first electrical connection portion, and the flange layer is disposed on the fourth surface; the first chip is provided with a second conductive post connected to the first electrical connection portion; one end of the second conductive post away from the first electrical connection portion extends toward the fourth surface and does not exceed the fourth surface.

3. The bridging packaging method according to claim 2, characterized in that, In the step of grinding the second surface, the first electrical connection and the first conductive post are exposed, and the end face of the first electrical connection facing the second surface and the end face of the first conductive post facing the second surface are flush. In the step of forming a first wiring layer that is electrically connected to the first conductive post on one side of the second surface: the first electrical connection portion and the first wiring layer are electrically connected.

4. The bridging packaging method according to claim 2, characterized in that, The step of forming a second wiring layer electrically connected to the first conductive post on one side of the first surface includes: The fourth surface of the first chip is ground to expose the second conductive pillar; The second wiring layer is electrically connected to the first conductive post and the second conductive post, respectively.

5. The bridging packaging method according to claim 2, characterized in that, The step of forming a second wiring layer electrically connected to the first conductive post on one side of the first surface includes: Grinding removes the flange layer so that the end face of the second conductive post facing the first surface is flush with the end face of the first conductive post facing the first surface. A second wiring layer is formed; the first conductive post and the second conductive post are electrically connected to the second wiring layer respectively.

6. The bridging packaging method according to claim 1, characterized in that, Before the step of mounting the first chip in the first mounting slot, the method further includes: preparing the first chip; The steps for fabricating the first chip include: A wafer is provided; a second conductive pillar is provided inside the wafer; the wafer includes a third surface and a fourth surface disposed opposite to each other; one end face of the second conductive pillar is flush with the third surface, and the other end face is embedded in the wafer; A first electrical connection portion that is electrically connected to the second conductive post is formed on the third surface; Thinning the wafer from the fourth surface; The wafer is cut to separate it into the first chip.

7. The bridging packaging method according to claim 6, characterized in that, The first electrical connection includes a connected third wiring layer and a third conductive post; the step of forming the first electrical connection electrically connected to the second conductive post on the third surface includes: A third wiring layer electrically connected to the second conductive pillar is formed on the third surface; The third conductive post is formed on the third wiring layer; the third conductive post and the third wiring layer are electrically connected.

8. The bridging packaging method according to claim 6, characterized in that, The step of cutting the wafer into the first chip includes: The wafer is first cut to a depth less than the thickness of the wafer, forming a separation groove; The bottom of the separation groove is cut a second time, with a preset distance between the cutting position and the groove wall, forming a single first chip with a flange layer.

9. A packaging structure, characterized in that, The package structure is manufactured using the bridging packaging method as described in any one of claims 1 to 8, and the package structure includes: A substrate having a first conductive pillar therein; the substrate having a first surface and a second surface disposed opposite to each other; one end of the first conductive pillar being flush with the first surface and the other end being flush with the second surface; A first chip has a third surface and a fourth surface disposed opposite to each other; the chip is provided with a first electrical connection portion and a second conductive post that are electrically connected; the end face of the first electrical connection portion away from the second conductive post is flush with the second surface, and the end face of the second conductive post away from the first electrical connection portion is flush with the first surface; the first electrical connection portion includes a third conductive post, and the third conductive post and the second conductive post are electrically connected. A first colloid fills the gap between the sidewall of the first chip and the substrate, and also fills the gap between the plurality of third conductive pillars; A first wiring layer is disposed on the second surface and is electrically connected to the first conductive post and the first electrical connection portion, respectively. A second wiring layer is disposed on the first surface and is electrically connected to the first conductive post and the second conductive post, respectively.

10. The packaging structure according to claim 9, characterized in that, The first electrical connection portion further includes a third wiring layer connected to the third conductive post, wherein the side of the third wiring layer away from the third conductive post is electrically connected to the second conductive post.

11. The packaging structure according to claim 9, characterized in that, It also includes pads; the pads are located at the end of the second conductive post away from the first electrical connection portion, and the pads are electrically connected to the second conductive post and the second wiring layer respectively. And / or, the pad is located at the end of the first electrical connection portion away from the second conductive post, and the pad is electrically connected to the first electrical connection portion and the first wiring layer respectively.

12. The packaging structure according to claim 9, characterized in that, The first wiring layer is electrically connected to a first solder ball; the second wiring layer is electrically connected to a second solder ball; A second chip is connected to one side of the first solder ball and / or one side of the second solder ball; the second chip is encapsulated in a molding compound.

13. The packaging structure according to claim 12, characterized in that, It also includes a third chip; the molding compound covers the third chip, which is a dummy chip; the third chip is not electrically connected to the first wiring layer or the second wiring layer.

14. The packaging structure according to any one of claims 9 to 13, characterized in that, The substrate is made of a molding compound, and a dummy chip is disposed within the substrate.

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