A packaging method of a car-grade chip and a packaging structure of a car-grade chip

Abstract

The application relates to the technical field of chips, and provides a packaging method of an automotive-grade chip and a packaging structure of the automotive-grade chip, which comprises the following steps: S1: providing a core plate, a power module and a heat dissipation copper block; a third wiring layer is prepared on the core plate to form a first semi-finished product plate; a first through groove and a second through groove are processed on the first semi-finished product plate; the power module is installed into the first through groove, and the heat dissipation copper block is installed into the second through groove; the power module comprises a chip and a base copper block, and the chip is arranged on the base copper block; S2: a second wiring layer is prepared to form a second semi-finished product plate; a first recess is formed on the second wiring layer; S3: a first wiring layer is prepared; and the base copper block and the heat dissipation copper block are in heat conduction connection.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, and more specifically, relates to a packaging method and packaging structure for automotive-grade chips. Background Technology

[0002] Modern chips are very common. To facilitate heat dissipation, a heat sink copper block is usually placed and thermally connected to the chip. Existing chip packaging and heat dissipation methods can be found in the processing flow of the first to sixth wiring layers and the copper block in (Chinese Invention Patent; Application No.: 2025110705168; Subject: A Packaging Method and Structure for Automotive-Grade Chips). The second wiring layer is usually fabricated using hot pressing during processing. After cooling, the second wiring layer shrinks, which can easily cause the substrate to bend.

[0003] Existing chip packaging methods can be found in the L1 to L6 chip packaging methods used in (Chinese Invention Patent; Publication No.: CN118763009A; Subject Title: A Packaging Method and Packaging Structure for Automotive-Grade Chips; Publication Date: 2024.10.11). The L1 layer corresponds to the first wiring layer in this application, the L2 layer corresponds to the second wiring layer in this application, the L3 layer corresponds to the third wiring layer in this application, and the L4 layer corresponds to the fourth wiring layer in this application.

[0004] Existing chip packaging methods can be found in the L1 to L6 chip packaging methods used in (Chinese Invention Patent; Publication No.: CN115841959A; Subject Title: A Packaging Structure and Method for a High-Power Chip; Publication Date: 2023.03.24). The L1 layer corresponds to the first wiring layer in this application, the L2 layer corresponds to the second wiring layer in this application, the L3 layer corresponds to the third wiring layer in this application, and the L4 layer corresponds to the fourth wiring layer in this application. Summary of the Invention

[0005] The purpose of this invention is to provide a packaging method for automotive-grade chips to solve the technical problem in the prior art where the second wiring layer is usually made by hot pressing during the processing, and the second wiring layer shrinks after cooling, which can easily cause the board to bend.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is: to provide a packaging method for automotive-grade chips, comprising:

[0007] S1: Provide a core board, a power module, and a heat dissipation copper block; prepare a third wiring layer on the core board to form a first semi-finished board; process a first through slot and a second through slot on the first semi-finished board; install the power module into the first through slot and the heat dissipation copper block into the second through slot; the power module includes: a chip and a base copper block, the chip being disposed on the base copper block;

[0008] S2: Prepare a second wiring layer to form a second semi-finished board; open a first groove on the second wiring layer;

[0009] S3: Prepare the first wiring layer; the base copper block and the heat dissipation copper block are thermally connected.

[0010] Furthermore, the first semi-finished board also includes: a fourth wiring layer laid on the core board; the thickness of the third wiring layer is greater than the thickness of the fourth wiring layer, and the core board has a first side and a second side respectively; the third wiring layer is located on the first side and the fourth wiring layer is located on the second side.

[0011] Further, step S2, "preparing a second wiring layer to form a second semi-finished board," includes:

[0012] S21: Multiple layers of semi-cured resin sheets and a layer of copper foil are sequentially stacked on the surface of the third wiring layer and pressed together to form the second wiring layer. The resin is heated and melted, and then filled the gap between the power module and the inner wall of the first through slot before curing.

[0013] S22: Remove the fourth wiring layer so that the surfaces of the base copper block and the heat dissipation copper block are flush with the second side.

[0014] Further, step S2, "creating a first groove on the second wiring layer," includes:

[0015] S23: A plurality of first interruptions are made on the second wiring layer, which are spaced apart from each other;

[0016] S24: The first groove is formed on the second wiring layer, and the first groove connects to a plurality of the first discontinuities.

[0017] Furthermore, there are multiple first grooves; the multiple first grooves intersect to form a first rectangular grid; the power module and the heat dissipation copper block are respectively located within the first rectangular grid.

[0018] Furthermore, a first discontinuity slit is fabricated on the second wiring layer using ultraviolet laser cutting; and / or a first groove is fabricated on the second wiring layer using ultraviolet laser cutting.

[0019] Furthermore, step S3, "preparing the first wiring layer," includes:

[0020] S31: The first wiring layer is formed by laminating multiple layers of semi-cured resin sheets and a layer of copper foil onto the surface of the second wiring layer;

[0021] S32: A second groove is formed on the first wiring layer.

[0022] Furthermore, step S32, "creating a second groove on the first wiring layer," includes:

[0023] S321: A plurality of second interruptions are made on the first wiring layer, which are spaced apart from each other;

[0024] S322: A second groove is formed on the first wiring layer, the second groove connecting a plurality of second discontinuities.

[0025] Furthermore, there are multiple second grooves; the multiple second grooves intersect to form a second rectangular grid; the power module and the heat dissipation copper block are respectively located within the second rectangular grid.

[0026] Furthermore, a second interruption slit is processed on the first wiring layer using ultraviolet laser cutting; and / or a second groove is processed on the first wiring layer using ultraviolet laser cutting.

[0027] Furthermore, it also includes: a heat sink; the heat sink is thermally connected to the base copper block and the heat dissipation copper block respectively.

[0028] Furthermore, it also includes: a thermally conductive insulating layer; the thermally conductive insulating layer is laid on the second side surface and covers the surfaces of the heat dissipation copper block and the base copper block; the heat sink is thermally connected to the base copper block through the thermally conductive insulating layer; the thermally conductive insulating layer is located between the base copper block and the heat sink; the thermally conductive insulating layer is located between the heat dissipation copper block and the heat sink.

[0029] Furthermore, the base copper block is spaced apart from the inner wall of the first through groove.

[0030] Furthermore, it also includes: a positioning boss disposed on the inner wall of the first through groove; the positioning boss is located in the gap between the inner wall of the first through groove and the power module.

[0031] Furthermore, the number of positioning bosses is multiple; the first through groove is a square hole, and the positioning bosses are respectively provided on the four side walls of the first through groove.

[0032] Furthermore, there are multiple power modules, multiple first through slots, multiple heat dissipation copper blocks, and multiple second through slots; the multiple power modules correspond one-to-one with the multiple first through slots, and the multiple heat dissipation copper blocks correspond one-to-one with the multiple second through slots.

[0033] This invention also provides a packaging structure for an automotive-grade chip, comprising: a core board, a power module, a heat dissipation copper block, a first wiring layer, a second wiring layer, and a third wiring layer; the core board and the third wiring layer form a first semi-finished board; the first semi-finished board is provided with a first through slot and a second through slot; the power module is disposed in the first through slot, and the heat dissipation copper block is disposed in the second through slot; the power module includes: a chip and a base copper block, the chip being disposed on the base copper block; the core board, the third wiring layer, and the second wiring layer form a second semi-finished board; a first groove is provided on the second wiring layer; the base copper block and the heat dissipation copper block are thermally connected.

[0034] The beneficial effects of the automotive-grade chip packaging method provided by this invention are as follows: Compared with the prior art, the automotive-grade chip packaging method provided by this invention provides a core board, on which a third wiring layer is formed. The core board and the third wiring layer together constitute a first semi-finished board. A first through slot and a second through slot are formed on the first semi-finished board. A power module can be installed in the first through slot, and a heat sink copper block can be installed in the second through slot. The power module includes a chip and a base copper block. The chip is disposed on the base copper block, and the base copper block and the heat sink copper block are thermally connected, so that the heat on the chip can be dissipated through the base copper block and the heat sink copper block. A first groove is formed on the second wiring layer, which divides the second wiring layer into multiple regions. The first groove can reduce the mutual influence of stress between different regions on the second wiring layer. When the second wiring layer is subjected to stress, the first groove can release part of the stress inside the second wiring layer, reducing the bending of the core board caused by the stress inside the second wiring layer. Attached Figure Description

[0035] Figure 1 A schematic diagram of the core board, third wiring layer, and fourth wiring layer provided in an embodiment of the present invention. Figure 1 ;

[0036] Figure 2 A schematic diagram of the core board, third wiring layer, and fourth wiring layer provided in an embodiment of the present invention. Figure 2 ;

[0037] Figure 3 A schematic diagram showing the first and second through slots on the core board provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram illustrating the configuration of the positioning boss provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram illustrating the installation of the adhesive tape according to an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the installation of the power module and the heat sink copper block provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the second wiring layer provided in an embodiment of the present invention;

[0042] Figure 8 Provided for embodiments of the present invention Figure 7 A diagram illustrating the removal of the tape;

[0043] Figure 9 A schematic diagram illustrating the arrangement of the first blind hole according to an embodiment of the present invention;

[0044] Figure 10 This is a schematic diagram of the copper layer filling the first blind via provided in an embodiment of the present invention;

[0045] Figure 11 A schematic diagram of a circuit pattern fabricated on the second wiring layer provided in an embodiment of the present invention;

[0046] Figure 12 This is a schematic diagram of the first wiring layer provided in an embodiment of the present invention;

[0047] Figure 13 A schematic diagram illustrating the arrangement of the second blind hole according to an embodiment of the present invention;

[0048] Figure 14 This is a schematic diagram of the copper layer filling the second blind via provided in an embodiment of the present invention;

[0049] Figure 15 A schematic diagram of removing the fourth wiring layer provided in an embodiment of the present invention;

[0050] Figure 16 This is a schematic diagram showing the bottom surfaces of the core board, base copper block, and heat dissipation copper block provided in an embodiment of the present invention after they have been polished.

[0051] Figure 17 A schematic diagram of the circuit fabrication on the first wiring layer provided in an embodiment of the present invention;

[0052] Figure 18 This is a schematic diagram of forming a solder mask layer on a first wiring layer according to an embodiment of the present invention;

[0053] Figure 19 A schematic diagram of the base copper block and the heat dissipation copper block provided in an embodiment of the present invention;

[0054] Figure 20 Schematic diagram of stress orientation distribution provided for embodiments of the present invention Figure 1 ;

[0055] Figure 21 Schematic diagram of stress orientation distribution provided for embodiments of the present invention Figure 2 ;

[0056] Figure 22 Schematic diagram of stress orientation distribution provided for embodiments of the present invention Figure 3 ;

[0057] Figure 23 This is a schematic diagram showing the distribution of the first groove provided in an embodiment of the present invention;

[0058] Figure 24 A schematic diagram showing the distribution of the first discontinuity joint provided in an embodiment of the present invention;

[0059] Figure 25 A schematic diagram of the first groove provided in an embodiment of the present invention. Figure 1 ;

[0060] Figure 26 A schematic diagram of the first groove provided in an embodiment of the present invention. Figure 2 ;

[0061] Figure 27 This is an assembly diagram of the heat sink provided in an embodiment of the present invention;

[0062] Figure 28 This is a schematic diagram of chip distribution provided in an embodiment of the present invention;

[0063] Figure 29 This is a flowchart illustrating the packaging process of an asymmetric automotive-grade chip provided in an embodiment of the present invention.

[0064] The following are the labeling elements in the figure:

[0065] 1-Core board; 11-First through slot; 111-Positioning boss; 12-Second through slot; 2-Power module; 21-Chip; 22-Base copper block; 31-First wiring layer; 31a-L1 copper foil; 31b-L1 dielectric layer; 32-Second wiring layer; 32a-L2 copper foil; 32b-L2 dielectric layer; 321-First gap; 322-First groove; 33-Third wiring layer; 34-Fourth wiring layer; 4-Heat dissipation copper block; 51-Thermal conductive insulation layer; 52-Heat sink; 61-Tape; 63-First blind hole; 64-Second blind hole; 65-Solder resist layer. Detailed Implementation

[0066] It should be noted that the specific embodiments are only used to explain the present invention and are not intended to limit the present invention.

[0067] It should be noted that, in the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Here, A and B can be singular or plural, respectively.

[0068] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as "connected to" or "attached to" another component, it can be directly connected to or indirectly connected to that other component. When a component is referred to as "fixed to" or "set on" another component, it can be directly on or indirectly on that other component.

[0069] It should be noted that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0070] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0071] It should be noted that the term "multiple" means two or more, unless otherwise explicitly specified.

[0072] Please refer to the following: Figures 1 to 29 The packaging method for automotive-grade chips provided by this invention will now be described. The packaging method for automotive-grade chips includes: S1: providing a core board 1, a power module 2, and a heat sink copper block 4; preparing a third wiring layer 33 on the core board 1 to form a first semi-finished board; processing a first through slot 11 and a second through slot 12 on the first semi-finished board; installing the power module 2 into the first through slot 11 and installing the heat sink copper block 4 into the second through slot 12; the power module 2 includes: a chip 21 and a base copper block 22, the chip 21 being disposed on the base copper block 22; S2: preparing a second wiring layer 32 to form a second semi-finished board; forming a first groove 322 on the second wiring layer 32; S3: preparing the first wiring layer 31; the base copper block 22 and the heat sink copper block 4 are thermally connected.

[0073] Thus, a core board 1 is provided, and a third wiring layer 33 is formed on one surface of the core board 1. The core board 1 and the third wiring layer 33 together form a first semi-finished board. A first through slot 11 and a second through slot 12 are formed on the first semi-finished board. The power module 2 can be installed in the first through slot 11, and the heat sink copper block 4 can be installed in the second through slot 12. The power module 2 includes a chip 21 and a base copper block 22. The chip 21 is disposed on the base copper block 22, and the base copper block 22 is thermally connected to the heat sink copper block 4, so that the heat on the chip 21 can be dissipated through the base copper block 22 and the heat sink copper block 4. A first groove 322 is formed on the second wiring layer 32. The first groove 322 divides the second wiring layer 32 into multiple regions. The first groove 322 can reduce the mutual influence of stress between different regions on the second wiring layer 32. When the second wiring layer 32 is subjected to stress, the first groove 322 can release part of the stress inside the second wiring layer 32, reducing the bending of the core board 1 caused by the stress inside the second wiring layer 32.

[0074] In one embodiment, the first through groove 11 is a hole.

[0075] In one embodiment, the second through groove 12 is a hole.

[0076] In one embodiment, the first groove 322 is a slit. In one embodiment, the second wiring layers 32 on both sides of the first groove 322 can be separated by the first groove 322. In one embodiment, the first groove 322 separates the second wiring layers 32 into different regions that are spaced apart from each other and are independent of each other.

[0077] In one embodiment, the second groove is a slit. In one embodiment, the first wiring layers on both sides of the second groove can be separated by the second groove. In one embodiment, the second groove separates the first wiring layer 31 into different regions that are spaced apart from each other and are independent of each other.

[0078] In one embodiment, the top of the base copper block 22 has a cavity, and the chip 21 is disposed in the cavity.

[0079] In one embodiment, the first wiring layer 31 is thermally connected to the base copper block 22 and the heat dissipation copper block 4, respectively.

[0080] In one embodiment, the second wiring layer 32 is thermally connected to the base copper block 22 and the heat dissipation copper block 4, respectively.

[0081] In one embodiment, the base copper block 22 and the heat dissipation copper block 4 are thermally connected by L1 copper foil 31a.

[0082] In one embodiment, the base copper block 22 and the heat dissipation copper block 4 are thermally connected by L2 copper foil 32a.

[0083] In one embodiment, the first wiring layer 31, L1 copper foil 31a (i.e., the copper foil of the first wiring layer 31), L1 dielectric layer 31b (i.e., the dielectric layer of the first wiring layer 31), the second wiring layer 32, L2 copper foil 32a (i.e., the copper foil of the second wiring layer 32), L2 dielectric layer 32b (i.e., the dielectric layer of the second wiring layer 32), the third wiring layer 33, the fourth wiring layer 34, the copper foil of the fourth wiring layer 34, and the fourth wiring layer 34 can be found in: (Chinese Invention Patent; Publication No.: CN118763009A; Subject Title: A Packaging Method and Packaging Structure for Automotive-Grade Chips; Publication Date: 2024.10.11).

[0084] In one embodiment, chip 21 is either a MOSFET chip or an IGBT chip. MOSFET stands for "Metal-Oxide-Semiconductor Field-Effect Transistor"; IGBT stands for "Insulated Gate Bipolar Transistor".

[0085] Further, please refer to Figures 1 to 28 As a specific embodiment of the automotive-grade chip packaging method provided by the present invention, the first semi-finished board further includes: a fourth wiring layer 34 laid on the core board 1; the thickness of the third wiring layer 33 is greater than the thickness of the fourth wiring layer 34, and the core board 1 has a first side and a second side respectively; the third wiring layer 33 is located on the first side, and the fourth wiring layer 34 is located on the second side. Thus, the thickness of the third wiring layer 33 is greater than the fourth wiring layer 34; when the second wiring layer 32 is laid on the third wiring layer 33, the core board 1 is not easily bent towards the third wiring layer 33 side.

[0086] Further, please refer to Figures 1 to 28 As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, step S2, "preparing the second wiring layer 32 to form the second semi-finished board," includes: S21: sequentially stacking multiple layers of semi-cured resin sheets and a layer of copper foil on the surface of the third wiring layer 33 and pressing them together to form the second wiring layer 32; the resin is heated and melted, filling the gap between the power module 2 and the inner wall of the first through slot 11, and then cured; S22: removing the fourth wiring layer 34 so that the surfaces of the base copper block 22 and the heat dissipation copper block 4 are flush with the second side surface, respectively. Thus, the resin is heated and melted during the heating and pressure transmission process, filling the gap between the power module 2 and the core board 1 before curing, resulting in a void-free filling effect between the side wall of the power module 2 and the inner wall of the core board 1, thereby avoiding high-voltage breakdown caused by local thinning of the dielectric layer or the presence of air gaps.

[0087] Further, please refer to Figures 1 to 28As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, step S2, "forming a first groove 322 on the second wiring layer 32", includes: S23: forming a plurality of mutually spaced first gaps 321 on the second wiring layer 32; S24: forming a first groove 322 on the second wiring layer 32, the first groove 322 connecting the plurality of first gaps 321. Thus, the first gaps 321 are processed first on the second wiring layer 32, and then the first groove 322 is processed, improving the processing efficiency of the first groove 322.

[0088] Further, please refer to Figures 1 to 28 In one specific embodiment of the automotive-grade chip packaging method provided by the present invention, there are multiple first grooves 322; the multiple first grooves 322 intersect to form a first rectangular grid; the power module 2 and the heat dissipation copper block 4 are respectively located within the first rectangular grid. In this way, each first groove 322 can release the stress of the second wiring layer 32, and the first rectangular grid can confine the stress to mutually independent areas.

[0089] Further, please refer to Figures 1 to 28 As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, a first interruption slit 321 is processed on the second wiring layer 32 using ultraviolet laser cutting; and / or a first groove 322 is processed on the second wiring layer 32 using ultraviolet laser cutting. Thus, ultraviolet laser cutting is highly efficient.

[0090] Further, please refer to Figures 1 to 28 As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, step S3, "preparing the first wiring layer," includes: S31: stacking multiple layers of semi-cured resin sheets and a layer of copper foil on the surface of the second wiring layer 32 and laminating them to form the first wiring layer 31; S32: forming a second groove on the first wiring layer 31. Thus, the second groove on the first wiring layer 31 divides the first wiring layer 31 into multiple regions. The second groove can reduce the mutual influence of stress between different regions on the first wiring layer 31; when the first wiring layer 31 is subjected to stress, the second groove can release part of the stress inside the first wiring layer 31, reducing the bending of the core board 1 caused by the stress inside the first wiring layer 31.

[0091] Further, please refer to Figures 1 to 28As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, step S32, "forming a second groove on the first wiring layer 31," includes: S321: forming a plurality of mutually spaced second gaps on the first wiring layer 31; S322: forming a second groove on the first wiring layer 31, the second groove connecting the plurality of second gaps. Thus, the second gaps are processed first on the first wiring layer 31, and then the second groove is processed, improving the processing efficiency of the second groove.

[0092] Further, please refer to Figures 1 to 28 In one specific embodiment of the automotive-grade chip packaging method provided by the present invention, there are multiple second grooves; these multiple second grooves intersect to form a second rectangular grid; the power module 2 and the heat dissipation copper block 4 are respectively located within the second rectangular grid. Thus, each second groove can release the stress of the first wiring layer 31, and the second rectangular grid can confine the stress to mutually independent areas.

[0093] Further, please refer to Figures 1 to 28 As a specific embodiment of the packaging method for automotive-grade chips provided by the present invention, a second interruption slit is processed on the first wiring layer 31 using ultraviolet laser cutting; and / or a second groove is processed on the first wiring layer 31 using ultraviolet laser cutting. Thus, ultraviolet laser cutting is highly efficient.

[0094] Further, please refer to Figures 1 to 28 As a specific embodiment of the automotive-grade chip packaging method provided by the present invention, it further includes: a heat sink 52; the heat sink 52 is thermally connected to the base copper block 22 and the heat dissipation copper block 4 respectively. In this way, the heat sink 52 can dissipate heat from the base copper block 22 and the heat dissipation copper block 4.

[0095] Further, please refer to Figures 1 to 28 As a specific embodiment of the automotive-grade chip packaging method provided by the present invention, it further includes: a thermally conductive insulating layer 51; the thermally conductive insulating layer 51 is laid on the second side and covers the surfaces of the heat sink copper block 4 and the base copper block 22; the heat sink 52 is thermally connected to the base copper block 22 through the thermally conductive insulating layer 51; the thermally conductive insulating layer 51 is located between the base copper block 22 and the heat sink 52; the thermally conductive insulating layer 51 is located between the heat sink copper block 4 and the heat sink 52. Thus, the heat sink copper block 4 and the base copper block 22 can transfer heat to the heat sink 52 through the thermally conductive insulating layer 51.

[0096] Further, please refer to Figures 1 to 28 In one specific embodiment of the automotive-grade chip packaging method provided by the present invention, the base copper block 22 and the inner wall of the first through groove 11 are spaced apart. Thus, the base copper block 22 and the inner wall of the first through groove 11 are separated from each other to improve insulation capability.

[0097] Further, please refer to Figures 1 to 28 As a specific embodiment of the automotive-grade chip packaging method provided by the present invention, it further includes: a positioning boss 111 disposed on the inner wall of the first through groove 11; the positioning boss 111 is located in the gap between the inner wall of the first through groove 11 and the power module 2. In this way, the positioning boss 111 can make the position of the power module 2 more precise.

[0098] Further, please refer to Figures 1 to 28 In one specific embodiment of the automotive-grade chip packaging method provided by the present invention, the number of positioning bosses 111 is multiple; the first through slot 11 is a square hole, and positioning bosses 111 are respectively provided on the four side walls of the first through slot 11. In this way, multiple positioning bosses 111 can position the power module 2 together.

[0099] Further, please refer to Figures 1 to 28 In one specific embodiment of the automotive-grade chip packaging method provided by the present invention, there are multiple power modules 2, multiple first through slots 11, multiple heat dissipation copper blocks 4, and multiple second through slots 12; the multiple power modules 2 correspond one-to-one with the multiple first through slots 11, and the multiple heat dissipation copper blocks 4 correspond one-to-one with the multiple second through slots 12. In this way, multiple power modules 2 can be installed in different first through slots 11, increasing the number of power modules 2 and the total power.

[0100] Please see Figures 1 to 28The present invention also provides a packaging structure for an automotive-grade chip, comprising: a core board 1, a power module 2, a heat dissipation copper block 4, a first wiring layer 31, a second wiring layer 32, and a third wiring layer 33; the core board 1 and the third wiring layer 33 form a first semi-finished board; the first semi-finished board is provided with a first through slot 11 and a second through slot 12; the power module 2 is disposed in the first through slot 11, and the heat dissipation copper block 4 is disposed in the second through slot 12; the power module 2 includes: a chip 21 and a base copper block 22, the chip 21 being disposed on the base copper block 22; the core board 1, the third wiring layer 33, and the second wiring layer 32 form a second semi-finished board; a first groove 322 is provided on the second wiring layer 32; the base copper block 22 and the heat dissipation copper block 4 are thermally connected. Thus, a core board 1 is provided, and a third wiring layer 33 is formed on one surface of the core board 1. The core board 1 and the third wiring layer 33 together form a first semi-finished board. A first through slot 11 and a second through slot 12 are formed on the first semi-finished board. The power module 2 can be installed in the first through slot 11, and the heat sink copper block 4 can be installed in the second through slot 12. The power module 2 includes a chip 21 and a base copper block 22. The chip 21 is disposed on the base copper block 22, and the base copper block 22 is thermally connected to the heat sink copper block 4, so that the heat on the chip 21 can be dissipated through the base copper block 22 and the heat sink copper block 4. A first groove 322 is formed on the second wiring layer 32. The first groove 322 divides the second wiring layer 32 into multiple regions. The first groove 322 can reduce the mutual influence of stress between different regions on the second wiring layer 32. When the second wiring layer 32 is subjected to stress, the first groove 322 can release part of the stress inside the second wiring layer 32, reducing the bending of the core board 1 caused by the stress inside the second wiring layer 32.

[0101] In one embodiment, the process flow of a packaging method for an automotive-grade chip is as follows:

[0102] [Processing Step 1] Please refer to Figure 1 A double-sided copper-clad laminate with a copper thickness of 1.29 mm is prepared. This double-sided copper-clad laminate has a three-layer structure, including an upper third metal layer (i.e., the third wiring layer 33), a lower fourth metal layer (i.e., the fourth wiring layer 34), and a middle third dielectric layer (i.e., the core board 1). The thickness of the third metal layer is 33 μm, and the thickness of the fourth metal layer is 18 μm. That is to say, the double-sided copper-clad laminate is a male-female copper structure. The reason for choosing a male-female copper structure is that this type of copper-clad laminate will slightly warp towards the thinner copper side. In this case, it warps slightly downwards, which can offset the degree of upward warping of the five-layer and seven-layer semi-finished boards in subsequent processes.

[0103] [Processing Step 2] Please refer to Figure 2 In step 1, the inner layer pattern is transferred on the double-sided copper-clad board, and the circuit pattern is etched on the third metal layer and the fourth metal layer to form the third wiring layer 33 and the fourth wiring layer 34.

[0104] In one embodiment, regarding "pattern transfer" in this application: "Pattern transfer" is a collective term for a series of photolithography processes in printed circuit board (PCB) manufacturing that accurately transfer a designed circuit pattern from film (or digital mask) to the surface of a copper clad laminate (CCL) or a prepreg resin layer. Its core purpose is to form a photolithographic resist pattern on the substrate that is completely consistent with the circuit design, so that the required conductive lines can be accurately etched or electroplated subsequently.

[0105] [Processing Step 3] Please refer to [Step 3] Figure 3 and Figure 4 The three-layer semi-finished board formed in step 2 is machined with through slots (i.e., the first through slot 11 and the second through slot 12) using an automatic optical alignment milling machine. Each embedded power module 2 and heat dissipation copper block 4 has a separate through slot corresponding to it.

[0106] The through-slot dimensions are 60μm larger on each side than both the power module 2 and the heat sink copper block 4, and each slot wall is designed with two protrusions (i.e., positioning protrusions 111) with a bottom width of 300μm and a height of 30μm. The advantage of this design is that it compresses the actual gap between the through-slot and the power module 2 to 60-30=30μm. Combined with the through-slot's ±50μm positional accuracy and ±50μm dimensional accuracy, the maximum actual offset of the power module 2 becomes ±(30μm). 2 +50 2 +50 2 ) 0.5 The accuracy of ±76.8μm can significantly reduce the risk of blind holes being misaligned with the chip 21 pads on the power module 2 during subsequent laser drilling processes.

[0107] [Processing Step 4] Please refer to Figure 5 and Figure 6 In step 3, the three-layer semi-finished board is browned on the third wiring layer 33 and the fourth wiring layer 34. High-temperature tape 61 is attached to the fourth wiring layer 34 with the adhesive side of the tape 61 facing the through groove. Therefore, the board through groove (i.e. the first through groove 11 and the second through groove 12) is transformed into a blind groove (wherein, the first through groove 11 and the second through groove 12 form two different blind grooves respectively).

[0108] The automotive-grade power module 2 and the heat sink copper block 4 are browned on the surface and then manually placed into the blind slots (i.e., the first through slot 11 and the second through slot 12) in step 3. The power module 2 and the heat sink copper block 4 are fixed with tape 61. Each substrate contains 12 power modules 2 and 6 heat sink copper blocks 4.

[0109] In one embodiment, "browning treatment" in this application refers to a chemical roughening process performed on the copper surface during PCB manufacturing, also known as "browning" or "browning oxidation." Its main purpose is to significantly improve the mechanical interlocking force and chemical bonding strength between the subsequent adhesive film, semi-cured resin sheet, or dry film and the copper surface by generating a micron-sized brown oxide film or roughening layer on the copper surface, thereby ensuring that delamination or separation does not occur between layers during multilayer board lamination. In one embodiment, for example, in a specific oxidizing solution (common formulations include sodium hypochlorite / sulfite systems, sodium nitrite + hydrochloric acid systems, or iminophosphates, etc.), a trace oxidation reaction occurs on the copper surface, generating a layer of brownish copper oxide (Cu2O / CuO) and / or copper hydroxy compounds. Simultaneously, a small amount of copper selectively dissolves, forming a rough honeycomb or needle-like microstructure.

[0110] [Processing Step 5] Please refer to [Step 5] Figure 7 The first lamination process (forming the second wiring layer 32) is as follows: two lamination sheets (prepreg sheets in this case) are placed on the third wiring layer 33 of the three-layer semi-finished board formed in step 3, followed by a copper foil, and then high-temperature lamination is performed to form a five-layer semi-finished board. During the high-temperature lamination process, the resin in the lamination sheets melts due to heat, flows in and fills the gap between the power module 2 and the blind slot wall, and then the resin cures, firmly embedding the power module 2 inside the substrate.

[0111] [Processing Step 6] Please refer to [Step 6] Figure 8 Remove the high-temperature tape 61 from the fourth wiring layer 34 of the five-layer semi-finished board formed in step 5, and then pass it through the fabric grinding line to grind away the brown film on the fourth wiring layer 34.

[0112] [Processing Step 7] Please refer to [Step 7] Figure 9 In step 6, the five-layer semi-finished board is patterned and transferred. The copper foil between the second wiring layer 32 and the chip 21, and between the second wiring layer 32 and the copper heat sink 4, and directly above the φ230μm copper heat sink 4, is etched away to form a φ230μm circular etched window. Then, a laser drilling machine is used to laser ablate the window to form a φ230μm first blind via 63.

[0113] [Processing Step 8] Please refer to [Step 8] Figure 10 In step 7, the five-layer semi-finished board is electroplated to fill the first blind hole 63 and form a first thermally conductive copper pillar with a diameter of φ230μm. At the same time, the thickness of the second metal layer (i.e., L2 copper foil 32a) is increased.

[0114] [Processing Step 9] Please refer to [Step 9] Figure 11 In step 8, the five-layer semi-finished board is subjected to single-sided pattern transfer, and the circuit is etched on the second metal layer (i.e., L2 copper foil 32a) to form the second wiring layer 32.

[0115]

Processing Step 10

[0116] [Step 11] Please refer to Figure 12 The second pressing process is as follows: two pressing sheets (pre-cured sheets in this case) are placed on the second wiring layer 32 of the five-layer structure semi-finished board formed in step 10, and then a copper foil is placed on top before high-temperature pressing to form a seven-layer structure semi-finished board.

[0117] [Step 12] Please refer to Figure 13 In step 11, the seven-layer semi-finished board is transferred to a new pattern. The copper foil directly above the φ230μm heat dissipation copper block 4 between the first wiring layer 31 and the second wiring layer 32 is etched away to form a φ230μm circular etched window. Then, a laser drilling machine is used to laser ablate the window to form a φ230μm second blind hole 64.

[0118] [Processing Step 13] Please refer to [link / reference] Figure 14 In step 12, the seven-layer semi-finished board is electroplated to fill the second blind hole 64 and form a second thermally conductive copper pillar with a diameter of φ230μm. At the same time, the thickness of the first metal layer (i.e., the copper foil 31a of the first wiring layer) is increased.

[0119] [Processing Step 14] Please refer to [link / reference] Figure 15 In step 13, the seven-layer semi-finished board is subjected to single-sided copper reduction, and the fourth wiring layer 34 is etched away to form a six-layer semi-finished board. After completion, the copper at the bottom of the base copper block 22 and the heat dissipation copper block 4 will also be etched away with a thickness of about 50μm. At the same time, the resin filling the gap between the copper block and the tank wall will be partially exposed at the bottom of the semi-finished board.

[0120] [Processing Step 15] Please refer to [Step 15] Figure 16 The six-layer semi-finished board formed in step 14 is then used as a single-sided ceramic grinding plate to cut off the exposed resin protrusions at the bottom, in order to level the bottom surface of the six-layer semi-finished board.

[0121] [Processing Step 16] Please refer to [link / reference] Figure 17 The six-layer semi-finished board formed in step 15 is subjected to single-sided pattern transfer. The circuit is etched on the first metal layer (i.e., the copper foil 31a of the first wiring layer) to form the first wiring layer 31.

[0122] [Processing Step 17] Please refer to [Step 17] Figure 18 The six-layer semi-finished board formed in step 16 is then subjected to solder resist silkscreen printing, solder resist exposure, solder resist development, and post-curing to form solder resist layer 65.

[0123]

Step 18

[0124] [Processing Step 19] Please refer to [link / reference] Figures 19 to 26 The six-layer semi-finished board formed in step 18 is cut and shaped using a milling machine to form a substrate with the smallest unit size.

[0125] Figure 19 For: the substrate with the smallest unit size (back side facing up).

[0126] Thermal expansion and contraction are fundamental laws governing phenomena. Therefore, in step 5 of this case, during the high-temperature pressing process after arranging the prepreg and copper foil on the three-layer semi-finished board, both the three-layer semi-finished board and the prepreg will expand. Once the pressure transfer is complete and the temperature returns to room temperature, each layer of the resulting five-layer semi-finished board will then contract (contracting towards the center of the substrate, such as...). Figure 20 (As shown). The pressed sheet is a prepreg, which is a prepreg material formed by impregnating fiberglass cloth (such as glass fiber cloth) with epoxy resin (or other types of resin) to form stage B (partially cured). Due to the polymerization reaction of resin monomers during the pressing process, the expansion of the prepreg during the hot pressing process and the shrinkage of the second dielectric layer formed by it after cooling are particularly severe, while the shrinkage of other layers after cooling is much less.

[0127] Some existing substrates employ a top-to-bottom symmetrical structure. The contraction of the second dielectric layer (i.e., L2 dielectric layer 32b) causes upward warping, while the contraction of the fourth dielectric layer (i.e., the dielectric layer of the fourth wiring layer) causes downward warping. These two processes cancel each other out, resulting in an overall non-warping substrate (e.g., ...). Figure 21 ).

[0128] The substrate in this application has an asymmetrical structure. The severe shrinkage of the second dielectric layer (i.e., L2 dielectric layer 32b) after lamination and cooling causes significant upward warping of the five-layer semi-finished board (e.g., ...). Figure 22 As shown). The first dielectric layer (i.e., L1 dielectric layer 31b) also suffers from severe shrinkage towards the center of the substrate after lamination and cooling, and the cumulative effect causes further warping of the seven-layer semi-finished board.

[0129] To address the substrate warping issue during the process, the prepregs in steps 5 and 11 are pre-cut with slits using a die (e.g., Figure 23 As shown), the slot design rules are as follows: a. Slot width 0.5mm; b. All slots are located outside the effective unit of the substrate, along the edge line of the smallest unit of the substrate, and the center line of the slot is 0.75mm away from the edge line of the smallest unit of the substrate; c. Intermittent slots, with a connecting rib of 2mm length spaced every 6mm of slot.

[0130] Please see Figure 24 The location of the slit in the prepreg.

[0131] After the substrate completes the lamination processes in steps 5 and 11, it will be further cut using UV laser depth control along the prepreg seam. The depth control standard is to expose the third wiring layer 33 (e.g., Figure 25 (As shown).

[0132] The purpose of using die-cutting to create slits in the prepreg, and for UV-controlled depth cutting in five-layer / seven-layer prepreg boards, is to disperse the thermal stress between the second and first dielectric layers (e.g., ...). Figure 26 As shown in the figure, this significantly improves the problem of low production efficiency caused by warping during the board manufacturing process.

[0133] Actual measurements confirmed that the warpage rates of the improved five-layer and seven-layer semi-finished boards decreased, the decrease in production efficiency caused by process board warping decreased, and the scrap rate of final products caused by process board warping decreased.

[0134] In one embodiment, see Figure 27 and Figure 28 Each substrate embeds 12 power modules2 (a total of 36 SiC automotive-grade chips) and 6 heat dissipation copper blocks4, increasing the power density by 31% compared to the previous version.

[0135] The bottom surfaces of the base copper block 22 and the heat dissipation copper block 4 are directly exposed. The substrate (i.e., the core board 1) can be directly welded to the water-cooled heat sink 52 after pressure transmission through a high thermal conductivity insulating material. After the working heat of the chip 21 is conducted to the base copper block 22 and the heat dissipation copper block 4, it is further conducted to the water-cooled heat sink 52 through the high thermal conductivity insulating layer 51, thereby improving the heat transfer efficiency.

[0136] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A packaging method for an automotive-grade chip, characterized in that, include: S1: Provide a core board, a power module, and a heat dissipation copper block; prepare a third wiring layer on the core board to form a first semi-finished board; process a first through slot and a second through slot on the first semi-finished board; install the power module into the first through slot and the heat dissipation copper block into the second through slot; the power module includes: a chip and a base copper block, the chip being disposed on the base copper block; S2: Prepare a second wiring layer to form a second semi-finished board; open a first groove on the second wiring layer; the first groove divides the second wiring layer into multiple regions, and the second wiring layers on both sides of the first groove can be separated by the first groove; the first groove can release some of the stress inside the second wiring layer; S3: Prepare the first wiring layer; the base copper block and the heat dissipation copper block are thermally connected through the copper foil of the first wiring layer.

2. The packaging method for automotive-grade chips as described in claim 1, characterized in that, The first semi-finished board further includes: a fourth wiring layer laid on the core board; the thickness of the third wiring layer is greater than the thickness of the fourth wiring layer, and the core board has a first side and a second side respectively; the third wiring layer is located on the first side and the fourth wiring layer is located on the second side.

3. The packaging method for automotive-grade chips as described in claim 2, characterized in that, Step S2, "preparing the second wiring layer to form the second semi-finished board", includes: S21: Multiple layers of semi-cured resin sheets and a layer of copper foil are sequentially stacked on the surface of the third wiring layer and pressed together to form the second wiring layer. The resin is heated and melted, and then filled the gap between the power module and the inner wall of the first through slot before curing. S22: Remove the fourth wiring layer so that the surfaces of the base copper block and the heat dissipation copper block are flush with the second side.

4. The packaging method for automotive-grade chips as described in claim 1, characterized in that, Step S2, "creating a first groove on the second wiring layer", includes: S23: A plurality of first interruptions are made on the second wiring layer, which are spaced apart from each other; S24: The first groove is formed on the second wiring layer, and the first groove connects to a plurality of the first discontinuities.

5. The packaging method for automotive-grade chips as described in claim 4, characterized in that, The number of the first grooves is multiple; the multiple first grooves intersect to form a first rectangular grid; the power module and the heat dissipation copper block are respectively located within the first rectangular grid.

6. The packaging method for automotive-grade chips as described in claim 4, characterized in that, A first interruption slit is formed on the second wiring layer using ultraviolet laser cutting; and / or a first groove is formed on the second wiring layer using ultraviolet laser cutting.

7. The packaging method for automotive-grade chips as described in claim 1, characterized in that, The "preparation of the first wiring layer" in step S3 includes: S31: The first wiring layer is formed by laminating multiple layers of semi-cured resin sheets and a layer of copper foil onto the surface of the second wiring layer; S32: A second groove is formed on the first wiring layer.

8. The packaging method for automotive-grade chips as described in claim 7, characterized in that, Step S32, "creating a second groove on the first wiring layer", includes: S321: A plurality of second interruptions are made on the first wiring layer, which are spaced apart from each other; S322: A second groove is formed on the first wiring layer, the second groove connecting a plurality of second discontinuities.

9. The packaging method for automotive-grade chips as described in claim 8, characterized in that, The number of the second grooves is multiple; the multiple second grooves intersect to form a second rectangular grid; the power module and the heat dissipation copper block are respectively located within the second rectangular grid.

10. The packaging method for automotive-grade chips as described in claim 8, characterized in that, A second interruption slit is fabricated on the first wiring layer using ultraviolet laser cutting; and / or a second groove is fabricated on the first wiring layer using ultraviolet laser cutting.

11. The packaging method for automotive-grade chips as described in claim 3, characterized in that, Also includes: Heat sink; the heat sink is thermally connected to the base copper block and the heat dissipation copper block respectively.

12. The packaging method for automotive-grade chips as described in claim 11, characterized in that, Also includes: Thermally conductive insulating layer; The thermally conductive insulating layer is laid on the second side and covers the surfaces of the heat dissipation copper block and the base copper block; The heat sink is thermally connected to the base copper block through the thermally conductive insulating layer; the thermally conductive insulating layer is located between the base copper block and the heat sink; the thermally conductive insulating layer is located between the heat sink copper block and the heat sink.

13. The packaging method for automotive-grade chips as described in claim 1, characterized in that, The base copper block is spaced apart from the inner wall of the first through groove.

14. The packaging method for automotive-grade chips as described in claim 13, characterized in that, Also includes: A positioning boss is provided on the inner wall of the first through groove; the positioning boss is located in the gap between the inner wall of the first through groove and the power module.

15. The packaging method for automotive-grade chips as described in claim 14, characterized in that, The number of positioning bosses is multiple; the first through groove is a square hole, and the positioning bosses are respectively provided on the four side walls of the first through groove.

16. The packaging method for automotive-grade chips as described in claim 1, characterized in that, The number of power modules, the first through slot, the heat dissipation copper block, and the second through slot are all multiple; the multiple power modules and the multiple first through slots correspond one-to-one, and the multiple heat dissipation copper blocks and the multiple second through slots correspond one-to-one.

17. The packaging structure of an automotive-grade chip, characterized in that, include: The system comprises a core board, a power module, a heat dissipation copper block, a first wiring layer, a second wiring layer, and a third wiring layer; the core board and the third wiring layer form a first semi-finished board; the first semi-finished board is provided with a first through slot and a second through slot; the power module is disposed in the first through slot, and the heat dissipation copper block is disposed in the second through slot; the power module includes a chip and a base copper block, the chip being disposed on the base copper block; the core board, the third wiring layer, and the second wiring layer form a second semi-finished board; a first groove is provided on the second wiring layer; the first groove divides the second wiring layer into multiple regions, and the second wiring layers on both sides of the first groove can be separated by the first groove; the first groove can release some of the stress inside the second wiring layer; the base copper block and the heat dissipation copper block are thermally connected through the copper foil of the first wiring layer.

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