Power conversion device, control method thereof, and switching drive chip

Abstract

The application provides a power conversion device and a control method thereof and a switch driving chip. In the power conversion device, a controller controls a gate voltage of a first switch tube to decrease, controls the rate of change of the gate voltage to decrease when the gate voltage is greater than a second threshold value and the voltage difference between a first electrode and a second electrode is greater than or equal to a first threshold value, controls the gate voltage to increase first and then decrease until the first switch tube is turned off. When the voltage difference is less than the first threshold value and the gate voltage is less than or equal to a third threshold value, the controller controls the gate voltage to decrease at a third rate, and when the length of time for which the gate voltage decreases is greater than or equal to a first time threshold value and the voltage difference is less than the first threshold value, the controller controls the gate voltage to decrease until the first switch tube is turned off. The application can reduce the voltage stress and EMI generated by the switch tube in different application scenarios, improve the turn-off efficiency and reduce the turn-off loss.

Description

Technical Field

[0001] This application relates to the field of switch control technology, specifically to a power conversion device and its control method, and a switch driver chip. Background Technology

[0002] Power conversion devices can turn a switching transistor on or off by transmitting drive current to its control terminal (e.g., the gate). During the turn-off process, the channel current and the channel voltage across the transistor overlap, resulting in turn-off losses.

[0003] Typically, in some applications, power conversion devices can reduce turn-off losses by accelerating the turn-off speed of the switching transistor, thereby shortening the overlap between the channel current and channel voltage. However, in other applications, if the power conversion device controls the switching transistor to turn off rapidly, the channel voltage across the transistor may change abruptly under the influence of a large current, resulting in significant voltage stress across the transistor. This is especially problematic when a short-circuit fault occurs in the power conversion device or load, as the current flowing through the transistor increases dramatically, exacerbating the stress issue. Therefore, how to reduce the turn-off losses of the switching transistor while simultaneously reducing the voltage stress it generates in different application scenarios is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a power conversion device and its control method, as well as a switch driver chip. In different application scenarios of the switching transistor, such as when the current flowing through the switching transistor increases significantly or when the current flowing through the switching transistor is small, the power conversion device can effectively reduce the voltage stress and EMI generated by the switching transistor, while improving the turn-off efficiency and reducing the turn-off loss, thereby extending the service life of the switching transistor and improving the overall efficiency and performance of the power conversion device.

[0005] In a first aspect, this application provides a power conversion device, which includes a controller, a first switch and a second switch connected in series; the gate of the first switch is connected to the controller, the first electrode of the first switch is connected to the second switch, and the second electrode of the first switch is connected to the positive terminal of a DC bus or the negative terminal of a DC bus. The controller is configured to: when the turn-off time of the first switch arrives, control the gate voltage of the first switch to decrease at a first rate of change; when the voltage difference between the first electrode and the second electrode increases to be greater than or equal to a first threshold and the gate voltage is greater than a second threshold, control the rate of change of the gate voltage to switch to a second rate of change, and switch the rate of change of the gate voltage to a second rate of change. After switching to the second rate of change, the gate voltage is controlled to increase first and then decrease until the first switch is turned off; the absolute value of the second rate of change is less than the absolute value of the first rate of change; or, when the voltage difference is less than the first threshold and the gate voltage decreases to less than or equal to the third threshold, the rate of change of the gate voltage decrease is controlled to switch to the third rate of change, and when the time length for the gate voltage to decrease at the third rate of change is greater than or equal to the first time threshold and the voltage difference is less than the first threshold, the rate of change of the gate voltage decrease is controlled to switch to the fourth rate of change until the first switch is turned off; the third threshold is less than the second threshold, the absolute value of the third rate of change is less than the absolute value of the first rate of change, and the absolute value of the third rate of change is less than the absolute value of the fourth rate of change.

[0006] In this embodiment, when the first switch turns off, the controller controls the gate voltage of the first switch to decrease at a first rate of change, which can effectively reduce the voltage stress and electromagnetic interference (EMI) generated by the first switch. Furthermore, when the controller detects that the voltage difference between the first and second electrodes is greater than or equal to a first threshold, it can quickly determine whether the current of the first switch is abnormally increased based on the magnitude of the gate voltage. Specifically, if the gate voltage is still greater than a second threshold when the voltage difference is greater than or equal to the first threshold, it indicates that the current flowing through the first switch is abnormally increased. At this time, the controller first controls the rate of decrease of the gate voltage to switch to a second rate of change to slow down the rate of decrease of the gate voltage, and then controls the gate voltage to increase to counteract the excessively rapid decrease in voltage difference caused by the abnormal increase in current, thereby timely controlling the voltage stress and EMI of the first switch and preventing damage to the first switch caused by the abnormal increase in current. Then, the controller controls the gate voltage to switch from increasing to decreasing until the first switch is turned off, which can improve the turn-off efficiency of the first switch and reduce turn-off losses throughout the entire turn-off process. Furthermore, when the gate voltage decreases at a first rate of change, if the voltage difference is still less than the first threshold when the gate voltage decreases to be equal to or less than the third threshold, it indicates that the current of the first switch is within the normal range, i.e., the current has not increased abnormally. At this time, the controller first controls the rate of change of the gate voltage to switch to the third rate of change to control the voltage stress and EMI of the first switch. Then, when the controller detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to the first time threshold, if the voltage difference is still less than the first threshold, it indicates that the current flowing through the first switch is within a normal small range, i.e., the current is very small, and the voltage stress and EMI generated by the turn-off of the first switch will also be very small. At this time, the controller can accelerate the turn-off speed of the first switch by controlling the gate voltage to decrease rapidly at a fourth rate of change until the first switch is completely turned off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses. Thus, in this application, the controller detects whether the current flowing through the first switch increases abnormally when the first switch is turned off, thereby timely controlling the voltage stress and EMI of the first switch to reduce, while also improving the turn-off efficiency of the first switch and reducing turn-off losses. In addition, the controller can detect whether the current flowing through the first switch is within a normal small range when the first switch is turned off, so as to control the first switch to turn off quickly in a timely manner, so as to maximize the turn-off efficiency of the first switch and reduce the turn-off loss, while ensuring that the voltage stress and EMI generated by the first switch are small, and the applicability is strong.

[0007] In one possible implementation, the controller is further configured to: maintain the rate of decrease of the gate voltage at the third rate of change as the third rate of change when the duration of the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold; and switch the rate of decrease of the gate voltage to the fifth rate of change when the gate voltage continues to decrease at the third rate of change and the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold; wherein the absolute value of the third rate of change is less than the absolute value of the fifth rate of change.

[0008] In this embodiment, when the gate voltage decreases at a third rate of change, if the controller detects that the duration of the gate voltage decrease at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. At this time, the controller controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, when the controller detects that the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, it indicates that the current flowing through the first switch is within the normal light load range, i.e., the current flowing through the first switch is relatively small, and the voltage stress and EMI generated by the first switch being turned off will also be relatively small. At this time, the controller switches the rate of change of the gate voltage to a fifth rate of change to control the first switch to turn off quickly, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses, making it highly applicable.

[0009] In one possible implementation, the controller is further configured to: maintain the rate of decrease of the gate voltage at the third rate of change as the third rate of change when the time duration for which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold; and switch the rate of decrease of the gate voltage to the fifth rate of change when the gate voltage continues to decrease at the third rate of change and the time duration for which the voltage difference increases from the first voltage difference to the second voltage difference is greater than or equal to a second time threshold; wherein the absolute value of the third rate of change is less than the absolute value of the fifth rate of change; and the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0010] In this embodiment, when the gate voltage decreases at a third rate of change, if the controller detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal small range. At this time, the controller controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, if the controller detects that the time for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to a second time threshold, it indicates that the current flowing through the first switch is within the normal light load range, i.e., the current flowing through the first switch is relatively small. Therefore, the voltage stress and EMI generated by the first switch being turned off will also be relatively small. At this time, the controller switches the rate of change of the gate voltage to a fifth rate of change to control the first switch to turn off quickly, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses, making it highly applicable.

[0011] In one possible implementation, the controller is further configured to: when the time duration for which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, control the rate of change of the gate voltage to remain at the third rate of change; and when the gate voltage continues to decrease at the third rate of change, and the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold and the voltage difference is greater than or equal to a fourth threshold, control the gate voltage to first increase and then decrease until the first switch is turned off.

[0012] In this embodiment, when the gate voltage decreases at a third rate of change, if the controller detects that the duration of the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. At this time, the controller controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, if the controller detects that the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold, it indicates that the current flowing through the first switch is within the normal heavy load range, i.e., the current flowing through the first switch is relatively large, and the voltage stress and EMI generated by the first switch being turned off will also be relatively large. At this time, the controller first controls the gate voltage to increase to offset the excessively rapid decrease in voltage difference caused by the large current, thereby controlling the voltage stress and EMI of the first switch to decrease. Then, the controller controls the gate voltage to switch from increasing to decreasing until the first switch is turned off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses.

[0013] In one possible implementation, the controller is further configured to: maintain the rate of decrease of the gate voltage at the third rate of change at a time length greater than or equal to a first time threshold and the voltage difference greater than or equal to the first threshold; and control the gate voltage to first increase and then decrease until the first switch is turned off when the gate voltage continues to decrease at the third rate of change, the time length during which the voltage difference increases from the first voltage difference to the second voltage difference is less than a second time threshold and the voltage difference is greater than or equal to a fourth threshold; wherein the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0014] In this embodiment, when the gate voltage decreases at a third rate of change, if the controller detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. At this time, the controller controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, if the controller detects that the time for the voltage difference to increase from the first voltage difference to the second voltage difference is less than a second time threshold, it indicates that the current flowing through the first switch is within the normal heavy load range, i.e., the current flowing through the first switch is relatively large, and the voltage stress and EMI generated by the first switch being turned off will also be relatively large. At this time, the controller first controls the gate voltage to increase to offset the excessively rapid decrease in voltage difference caused by the large current, thereby controlling the voltage stress and EMI of the first switch to decrease. Then, the controller controls the gate voltage to switch from increasing to decreasing until the first switch is turned off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses.

[0015] In one possible implementation, the first threshold satisfies:

[0016]

[0017] Where Vbus is the DC bus voltage, N is a positive integer greater than or equal to 2, n is equal to 1 or 2, and n is less than N.

[0018] In this embodiment, the value of the first threshold is related to the DC bus voltage, and the specific value of the first threshold can be flexibly adjusted according to actual needs (N and n are adjustable), with a wide range of application scenarios.

[0019] In one possible implementation, the second threshold is in the range of 6 to 7 volts, and the third threshold is in the range of 4 to 5 volts.

[0020] In this embodiment, when the first switch decreases at a first rate of change, if the controller detects that the gate voltage of the first switch is greater than 6 volts (a second threshold) when the voltage difference is greater than or equal to a first threshold, the controller can quickly determine that the current flowing through the first switch has increased abnormally. Furthermore, when the first switch decreases at the first rate of change, if the gate voltage is less than or equal to 4 volts (a third threshold), and the voltage difference is less than the first threshold, the controller can determine that the current flowing through the first switch has not increased abnormally. This implementation is simple and highly reliable.

[0021] In one possible implementation, the first time threshold ranges from 10 to 30 nanoseconds.

[0022] In this embodiment, if the voltage difference is still less than the first threshold when the gate voltage decreases at a third rate of change for a duration greater than or equal to 10 nanoseconds to 30 nanoseconds, it indicates that the current flowing through the first switch is within a normal small range, that is, the current flowing through the first switch is very small.

[0023] In one possible implementation, the second time threshold ranges from 10 to 30 nanoseconds.

[0024] In this embodiment, when the gate voltage decreases at a third rate of change, if the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to 15 nanoseconds, it indicates that the current flowing through the first switch is within the normal light load range, i.e., the current flowing through the first switch is relatively small. Conversely, if the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is less than 15 nanoseconds, it indicates that the current flowing through the first switch is within the normal heavy load range, i.e., the current flowing through the first switch is relatively large.

[0025] Secondly, this application also provides a control method for a power conversion device, applied to a power conversion device including a first switch and a second switch connected in series; the gate of the first switch is connected to a controller, the first electrode of the first switch is connected to the second switch, and the second electrode of the first switch is connected to the positive terminal of a DC bus or to the negative terminal of a DC bus. The method includes:

[0026] When the turn-off time of the first switch arrives, the gate voltage of the first switch is controlled to decrease at a first rate of change.

[0027] When the voltage difference between the first electrode and the second electrode increases to a level greater than or equal to a first threshold and the gate voltage is greater than a second threshold, the rate of decrease of the control gate voltage switches to a second rate of decrease. After the rate of decrease of the control gate voltage switches to the second rate of decrease, the control gate voltage first increases and then decreases until the first switch is turned off; the absolute value of the second rate of decrease is less than the absolute value of the first rate of decrease; or,

[0028] When the voltage difference is less than the first threshold and the gate voltage decreases to less than or equal to the third threshold, the rate of decrease of the gate voltage is controlled to switch to the third rate of decrease. When the time length for which the gate voltage decreases at the third rate of decrease is greater than or equal to the first time threshold and the voltage difference is less than the first threshold, the rate of decrease of the gate voltage is controlled to switch to the fourth rate of decrease until the first switch is turned off. The third threshold is less than the second threshold, the absolute value of the third rate of decrease is less than the absolute value of the first rate of decrease, and the absolute value of the third rate of decrease is less than the absolute value of the fourth rate of decrease.

[0029] In one possible implementation, the method further includes: when the time duration for which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change and the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, controlling the rate of change of the gate voltage to switch to a fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change.

[0030] In one possible implementation, the method further includes: when the time duration for which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change and the time duration for which the voltage difference increases from the first voltage difference to the second voltage difference is greater than or equal to a second time threshold, controlling the rate of change of the gate voltage to switch to a fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change; and the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0031] In one possible implementation, the method further includes: when the time length during which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change, and the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold and the voltage difference is greater than or equal to a fourth threshold, controlling the gate voltage to first increase and then decrease until the first switch is turned off.

[0032] In one possible implementation, the method further includes: when the gate voltage decreases at a third rate of change for a duration greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of decrease of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change, and the time duration from the first voltage difference to the second voltage difference is less than the second time threshold and the voltage difference is greater than or equal to a fourth threshold, controlling the gate voltage to first increase and then decrease until the first switch is turned off; the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0033] In one possible implementation, the first threshold satisfies:

[0034]

[0035] Where Vbus is the DC bus voltage, N is a positive integer greater than or equal to 2, n is equal to 1 or 2, and n is less than N.

[0036] In one possible implementation, the second threshold is in the range of 6 to 7 volts, and the third threshold is in the range of 4 to 5 volts.

[0037] In one possible implementation, the first time threshold ranges from 10 to 30 nanoseconds.

[0038] In one possible implementation, the second time threshold ranges from 10 to 30 nanoseconds.

[0039] Thirdly, this application provides a switch driver chip, which includes the controller in the first aspect of this application and any possible implementation thereof. The switch driver chip is connected to a first switch transistor and a second switch transistor. The switch driver chip is used to drive the first switch transistor to turn on or off, and to drive the second switch transistor to turn on or off.

[0040] The beneficial effects of the solutions provided in the second and third aspects above can be referred to the description in the first aspect above, and will not be repeated here. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the power conversion device provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of a signal waveform of a switching transistor provided in an embodiment of this application;

[0043] Figure 3 This is another structural schematic diagram of the power conversion device provided in the embodiments of this application;

[0044] Figure 4This is another signal waveform diagram of the switching transistor provided in an embodiment of this application;

[0045] Figure 5 A schematic diagram of the current of the first switching transistor provided in an embodiment of this application;

[0046] Figure 6 A schematic diagram of a signal waveform of the first switching transistor provided in an embodiment of this application.

[0047] Figure 7 This is another schematic diagram of the signal waveform of the first switching transistor provided in an embodiment of this application;

[0048] Figure 8 Another signal waveform diagram of the first switching transistor provided in an embodiment of this application;

[0049] Figure 9 Another signal waveform diagram of the first switching transistor provided in an embodiment of this application;

[0050] Figure 10 A schematic flowchart of the control method for the power conversion device provided in this application. Detailed Implementation

[0051] The power conversion device provided in this application embodiment can be applied in switching power supplies, secondary power supplies, tertiary power supplies, or other power conversion devices. Depending on the circuit topology, the power conversion device can specifically be a boost converter, a buck converter, a buck-boost converter, or a resonant converter, etc. For example, the circuit topology of the power conversion device can be found in [reference needed]. Figure 1 As shown, Figure 1 This is a schematic diagram of the power conversion device provided in an embodiment of this application. Figure 1 As shown, the power conversion device includes three bridge arms connected in parallel between the positive terminal BUS+ and the negative terminal BUS- of the DC bus. Each bridge arm includes two switching transistors connected in series, with the connection point of the two transistors serving as the midpoint of the bridge arm. The midpoint of each bridge arm can be connected to an external load. By controlling the operation of the switching transistors in the three bridge arms, the power conversion device can convert the DC power supplied by the DC source into three-phase AC power to supply power to the load. It is understood that the circuit structure description of the power conversion device in this application is only an example of one power conversion device, and the circuit structure of the power conversion device can be flexibly adjusted according to different functional requirements.

[0052] During the operation of a power conversion device, the device controls the switching transistors of each bridge arm to turn on or off by transmitting drive current to the control electrodes (e.g., gates) of the transistors. During the turn-off process, there is an overlap between the channel current and channel voltage of the power transistor, resulting in turn-off losses. For an example, please refer to [link to example]. Figure 2 , Figure 2 This is a schematic diagram of a signal waveform of a switching transistor provided in an embodiment of this application. Ic represents the magnitude of the channel current (i.e., the current flowing through the switching transistor) during the turn-off process, and Vq represents the magnitude of the channel voltage (i.e., the voltage across the switching transistor) during the turn-off process. During the turn-off process, the current Ic flowing through the switching transistor gradually decreases, while the voltage Vq across the switching transistor gradually increases, thus forming overlapping shaded regions. The larger the area of ​​this shaded region, the greater the turn-off loss of the switching transistor.

[0053] In some applications, power conversion devices can accelerate the turn-off speed of transistors to reduce the overlap between the current flowing through the transistor and the voltage across it. Typically, in some applications, accelerating the turn-off speed shortens the overlap between the channel current and channel voltage, thereby reducing turn-off losses. However, in other applications, if the power conversion device controls the transistor to turn off rapidly, the channel voltage across the transistor may abruptly change under the influence of a large current, leading to significant voltage stress across the transistor. This is especially problematic when a short circuit occurs in the power conversion device or load, as the current flowing through the transistor increases dramatically, exacerbating stress issues. Excessive voltage stress can damage the transistor, shorten its lifespan, and generate severe EMI, affecting the stable operation of the power conversion device. Therefore, how to reduce turn-off losses of transistors in different application scenarios while simultaneously reducing voltage stress and EMI is a technical problem that urgently needs to be solved by those skilled in the art.

[0054] Therefore, this application provides a power conversion device that can effectively reduce the voltage stress and EMI generated by the switching transistor in different application scenarios, such as when the current flowing through the switching transistor increases significantly or when the current flowing through the switching transistor is small. At the same time, it can improve the turn-off efficiency and reduce the turn-off loss, thereby extending the service life of the switching transistor and improving the overall efficiency and performance of the power conversion device.

[0055] The above are merely examples of application scenarios for the power conversion device provided in this application, and are not exhaustive. This application does not limit the application scenarios.

[0056] The following content combines Figures 3 to 9The specific implementation principle of the power conversion device provided in the embodiments of this application will be introduced.

[0057] In this embodiment of the application, the above-mentioned Figure 1 As can be seen, a power conversion device includes at least one bridge arm, and each bridge arm is connected in parallel between the positive terminal and the negative terminal of the DC bus. When a power conversion device includes multiple bridge arms, the specific implementation of each bridge arm can be referenced interchangeably. For ease of understanding, the following description uses one bridge arm of a power conversion device as an example.

[0058] Please see Figure 3 , Figure 3 This is another structural schematic diagram of the power conversion device provided in an embodiment of this application. Figure 3 The power conversion device shown is connected to a DC source via a DC bus. This device includes a first switch Q1 and a second switch Q2. The first electrode of the first switch Q1 is connected to the first electrode of the second switch Q2, the second electrode of the first switch Q1 is connected to the positive terminal BUS+ of the DC bus, and the second electrode of the second switch Q2 is connected to the negative terminal BUS- of the DC bus. The connection point SW between the first switch Q1 and the second switch Q2 is used to connect an external load. It should be noted that... Figure 3 The positions of the first switch Q1 and the second switch Q2 shown can be interchanged, and this application embodiment does not limit this.

[0059] The power conversion device also includes a controller, which is connected to the control electrodes of the first switch Q1 and the second switch Q2, respectively. During the operation of the power conversion device, the controller transmits drive current to the control electrodes of the first switch Q1 or the second switch Q2 to control the first switch Q1 and the second switch Q2 to turn on or off, thereby converting the DC power provided by the DC source and outputting it through the connection point SW to supply power to the load.

[0060] The switching transistor (first switching transistor Q1 or second switching transistor Q2) can be, but is not limited to, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), an Insulated-Gate Bipolar Transistor (IGBT), or a SiC power transistor. Assuming the switching transistor in this embodiment is a MOSFET, its gate is the aforementioned control electrode, its source is the aforementioned first electrode, and its drain is the aforementioned second electrode. Alternatively, the drain is the aforementioned first electrode, and the source is the aforementioned second electrode. Assuming the switching transistor in this embodiment is an IGBT, its gate is the aforementioned control electrode, its collector is the aforementioned first electrode, and its emitter is the aforementioned second electrode. Alternatively, the emitter is the aforementioned first electrode, and the collector is the aforementioned second electrode. This embodiment does not limit the first electrode, the second electrode, or the specific type of the switching transistor.

[0061] It should be noted that the power conversion device may also include various other electronic devices to support the implementation of the function, such as filtering units, rectifier units, etc., which will not be described in detail in the embodiments of this application.

[0062] During the operation of power conversion equipment, the turn-off losses, voltage stress, and EMI generated when the first and second switching transistors are turned off significantly affect the overall efficiency and performance of the power conversion equipment. To facilitate understanding of the principles behind the turn-off losses, voltage stress, and EMI generated by the first and second switching transistors, the following description provides an example of the operating characteristics of the first switching transistor during the turn-off process. The operating characteristics of the second switching transistor during the turn-off process are similar to those of the first switching transistor, and will not be elaborated upon in the embodiments of this application.

[0063] For some feasible implementations, please refer to Figure 4 , Figure 4 This is another signal waveform diagram of the switching transistor provided in an embodiment of this application. After the controller receives a low-level pulse width modulation (PWM) signal from the first switching transistor, the controller begins to control the first switching transistor to turn off. The turn-off process of the first switching transistor can be divided into the following four stages:

[0064] In the first stage, from t0 to t1, the controller stops supplying drive current to the gate of the first switch, and the gate voltage Vg of the first switch begins to decrease from V0. During this stage, the first switch has not yet started to turn off, and the channel current Ic of the first switch remains unchanged. Simultaneously, the voltage Vq across the first switch also does not change significantly. At this time, the controller rapidly pulls down the gate voltage Vg of the first switch to accelerate the turn-off speed and reduce the losses caused by the increased internal resistance of the first switch during this period. When the gate voltage Vg of the first switch decreases from its maximum value V0 to V1, the turn-off process of the first switch enters the second stage.

[0065] In the second stage, from t1 to t2, the first switch enters the Miller plateau stage and begins to turn off. During this second stage, the smaller the drive current supplied by the controller to the first switch, the slower its turn-off speed and the smaller the rate of change of the voltage Vq across it, resulting in lower EMI and voltage stress. When the gate voltage Vg of the first switch decreases from V1 to V2, the turn-off process enters the third stage.

[0066] In the third stage, from t2 to t3, the first switch enters the current-off stage. The channel current Ic of the first switch begins to decrease, and as the channel current Ic decreases, the voltage Vq across the first switch also decreases. At this time, the smaller the drive current supplied by the controller to the first switch, the slower the turn-off speed of the first switch, and the smaller the rate of change of the channel current Ic, thus resulting in less voltage stress on the first switch. When the gate voltage Vg of the first switch decreases from V2 to V3, the turn-off of the first switch enters the fourth stage.

[0067] In the fourth stage, from t3 to t4, the first switching transistor enters the current cutoff stage, and its channel current Ic has decreased to a negligible level. At this time, the controller rapidly pulls down the gate voltage Vg of the first switching transistor to accelerate its turn-off speed. The gate voltage Vg of the first switching transistor continues to decrease until it reaches V4, at which point the turn-off process of the first switching transistor is complete.

[0068] Therefore, during the turn-off process of the first switch, the controller can balance the channel stress and turn-off loss of the first switch according to demand by adjusting the turn-off speed of the first switch. However, if the turn-off loss is minimized as much as possible, and a certain channel voltage stress is controlled, while considering short circuits in abnormal situations, Figure 4 The shutdown control method is not the optimal shutdown method.

[0069] Therefore, during the turn-off process of the first switch, the power conversion device provided in this application embodiment detects whether the current flowing through the first switch increases abnormally through the controller, and when it is determined that the current flowing through the first switch increases abnormally, the voltage stress and EMI generated by the first switch are controlled and reduced by adjusting the rate of change of the gate voltage of the first switch, while improving the turn-off efficiency of the first switch and reducing the turn-off loss of the first switch.

[0070] Specifically, when the controller receives the PWM signal from the first switching transistor switching from high to low, the turn-off time of the first switching transistor arrives. The controller controls the gate voltage of the first switching transistor to decrease at a first rate of change, so that the first switching transistor enters the turn-off process. During the process of the gate voltage of the first switching transistor decreasing at the first rate of change, the conductivity between the first and second electrodes of the first switching transistor gradually decreases, and the internal resistance of the first switching transistor gradually increases. At this time, if a short circuit fault occurs in the power conversion device or the load, causing an abnormal increase in the current flowing through the first switching transistor, the voltage difference between the first and second electrodes of the first switching transistor will increase rapidly as the internal resistance of the first switching transistor increases. Conversely, if the current flowing through the first switching transistor does not increase abnormally, the voltage difference between the first and second electrodes of the first switching transistor will only gradually increase as the internal resistance of the first switching transistor increases. Therefore, the controller can detect whether the voltage difference between the first and second electrodes of the first switching transistor increases rapidly during the process of controlling the gate voltage of the first switching transistor to decrease at the first rate of change, thereby determining whether the current flowing through the first switching transistor has increased abnormally.

[0071] In this embodiment, to detect whether the voltage difference between the first electrode and the second electrode of the first switch transistor increases rapidly, the controller, while controlling the gate voltage of the first switch transistor to decrease at a first rate of change, detects the voltage difference between the first electrode and the second electrode of the first switch transistor and the gate voltage of the first switch transistor. Specifically, the controller detects whether the gate voltage of the first switch transistor is greater than a second threshold when the voltage difference between the first electrode and the second electrode of the first switch transistor has increased to be equal to or greater than a first threshold. The second threshold value ranges from 6 to 7 volts, and the first threshold value can be calculated according to the following formula (1), which satisfies:

[0072]

[0073] Where Vbus is the DC bus voltage, N is a positive integer greater than or equal to 2, n is equal to 1 or 2, and n is less than N. The above-mentioned second threshold and first threshold are merely examples and do not constitute a limitation on the embodiments of this application.

[0074] It should be noted that when the controller detects that the voltage difference between the first and second electrodes of the first switching transistor has increased to be equal to or greater than a first threshold, while the gate voltage of the first switching transistor is still greater than a second threshold, it means that the voltage difference between the first and second electrodes of the first switching transistor is increasing rapidly, i.e., the current flowing through the first switching transistor is abnormally increasing. For an example, please refer to [link to example]. Figure 5 , Figure 5 This is a schematic diagram of the current of the first switching transistor provided in an embodiment of this application. Figure 5 As shown, when the magnitude (absolute value) of the current flowing through the first switching transistor is in the range of 800A to 2000A, it means that the current flowing through the first switching transistor has increased abnormally. Figure 5 The examples shown are merely illustrative and do not constitute a limitation on the embodiments of this application.

[0075] Furthermore, when the controller determines that the current flowing through the first switching transistor has abnormally increased, in order to promptly control the voltage stress and EMI generated by the first switching transistor, it can control the rate of change of the gate voltage of the first switching transistor to switch from a first rate of change to a second rate of change, where the absolute value of the second rate of change is less than the absolute value of the first rate of change. Specifically, the controller controls the rate of change of the gate voltage of the first switching transistor to switch from the first rate of change to the second rate of change with a smaller absolute value, meaning the speed at which the gate voltage of the first switching transistor decreases is slower. As can be seen from the above, during the turn-off process of the first switching transistor, the slower the rate of decrease of the gate voltage of the first switching transistor, the slower the turn-off speed of the first switching transistor. Therefore, when the controller determines that the current flowing through the first switching transistor has abnormally increased, by controlling the rate of change of the gate voltage of the first switching transistor to switch from the first rate of change to the second rate of change with a smaller absolute value, it can effectively control the voltage stress and EMI generated by the first switching transistor.

[0076] It should be noted that although the controller can slow down the rate of decrease of the gate voltage of the first switch by adjusting the rate of decrease of the gate voltage of the first switch to the second rate of decrease, thereby controlling the voltage stress and EMI generated by the first switch to decrease, the abnormal increase in the current flowing through the first switch and the excessively rapid decrease in the gate voltage of the first switch when it decreased at the first rate of decrease result in the generation of significant voltage stress and EMI when the gate voltage of the first switch decreases at the second rate of decrease.

[0077] Therefore, when the controller controls the gate voltage of the first switch to decrease at a second rate of change, and detects that the voltage difference between the first and second electrodes of the first switch is greater than or equal to a fourth threshold, the controller switches the gate voltage of the first switch from decreasing at the second rate of change to increasing. It should be noted that by increasing the gate voltage of the first switch, the controller can counteract the abnormal increase in the current of the first switch and the effects of the previously excessively rapid decrease in the gate voltage, thereby further controlling the voltage stress generated by the first switch and reducing EMI.

[0078] In some feasible implementations, the controller can determine the rate of change of the gate voltage of the first switching transistor before increasing it, based on the absolute value of the rate of change of the voltage difference between the first and second electrodes of the first switching transistor. Specifically, the larger the current flowing through the first switching transistor, the larger the rate of change of the voltage difference between the first and second electrodes, resulting in greater voltage stress and EMI generated by the first switching transistor. Therefore, when the controller detects a larger rate of change of the voltage difference between the first and second electrodes, it can control the gate voltage of the first switching transistor to increase at a larger rate, causing the gate voltage to rise faster, thereby effectively reducing voltage stress and EMI. Conversely, the controller can reduce the rate of change of the gate voltage, causing the gate voltage to rise more slowly, thereby reducing voltage stress and EMI while appropriately improving the turn-off efficiency of the first switching transistor.

[0079] In some feasible implementations, the controller can also determine the rate of change of the gate voltage of the first switching transistor based on the time it takes for the gate voltage of the first switching transistor to increase from the first voltage difference to the second voltage difference. A longer time indicates a smaller current flowing through the first switching transistor, allowing the controller to reduce the rate of change of the gate voltage to appropriately improve the turn-off efficiency of the first switching transistor. Conversely, the controller can control the first switching transistor to increase at a larger rate of change to minimize voltage stress and EMI generation.

[0080] Furthermore, during the increase of the gate voltage of the first switch, in order to reduce the voltage stress and EMI generated by the first switch while simultaneously improving its turn-off efficiency and reducing turn-off losses, the controller can control the gate voltage of the first switch to decrease when it detects that the voltage difference between the first and second electrodes of the first switch is greater than or equal to a fifth threshold. It should be noted that when the voltage difference between the first and second electrodes of the first switch is greater than or equal to the fifth threshold, the first switch enters a stage where EMI and voltage stress are not significantly generated. Figure 4 The fourth stage is shown. At this point, the controller's control of the first switch to quickly turn off will not cause significant voltage stress and EMI in the first switch. Therefore, by controlling the gate voltage of the first switch to decrease, the controller can accelerate the turn-off speed of the first switch to reduce turn-off losses, while ensuring that the voltage stress and EMI generated by the first switch remain relatively low. Specifically, after the controller switches the control of the gate voltage of the first switch from increasing to decreasing, the rate of decrease of the first switch voltage can be equal to the aforementioned first rate of change or other rates of change; this embodiment does not impose any limitations on this.

[0081] To facilitate understanding of the specific process by which the controller turns off the first switching transistor when the current abnormally increases, the following content combines... Figure 3 and Figure 6 To illustrate, Figure 6 This is a schematic diagram of a signal waveform of the first switching transistor provided in an embodiment of this application. Figure 6 The PWM signal shown is the pulse width modulation signal of the first switching transistor, Vg is the gate voltage of the first switching transistor, Ig is the drive current of the first switching transistor, and Vq is the voltage difference between the first electrode and the second electrode of the first switching transistor.

[0082] At time T0, the controller receives a PWM signal that switches to a low level, indicating the turn-off time of the first switch. At this time, the controller provides a drive current Isk1 to the gate of the first switch to control Vg to decrease rapidly at a first rate of change. The first switch then begins to turn off, causing Vq to increase from zero. During the decrease of Vg, the controller detects the gate voltage of the first switch and... Figure 3 The voltage at connection point SW and the negative terminal BUS- of the DC bus is used to detect the magnitudes of Vg and Vq. Alternatively, the controller can also obtain the voltage magnitudes of the gate, first electrode, and second electrode of the first switching transistor via an external detection device. This detection device is connected to the gate, first electrode, and second electrode of the first switching transistor and can send the detected voltage magnitudes of the gate, first electrode, and second electrode of the first switching transistor to the controller. The controller determines the magnitudes of Vg and Vq based on the received voltage magnitudes. The above are merely examples, and the specific implementation of the controller obtaining Vg and Vq in this application embodiment is not limited.

[0083] At time T1, the controller detects that Vg is greater than the second threshold Vskm, while Vq increases to equal the first threshold VL, indicating an abnormal increase in the current flowing through the first switch. To reduce voltage stress and EMI, the controller provides a drive current Isk2 to the gate of the first switch to control Vg to decrease at a second rate of change. The absolute value of the second rate of change is less than the absolute value of the first rate of change, meaning the rate of Vg decrease is slower, thereby reducing voltage stress and EMI generated by the first switch. Simultaneously, the controller detects the rate of change of Vq or the time it takes for Vq to increase from VL to VH to determine the magnitude of the rate of increase of Vg in subsequent stages.

[0084] At time T2, the controller detects that Vq has increased to equal the fourth threshold Vst. At this point, the controller provides a drive current Isp to the gate of the first switch to control Vg to increase at the rate of change determined in the above steps. As can be seen from the above, the controller's control of Vg increase can offset the abnormal increase in the current of the first switch and the negative effects of the previously excessively rapid decrease in gate voltage, thereby further reducing the voltage stress and EMI generated by the first switch. Furthermore, although Vg begins to rise, the first switch is still not fully turned off, so Vq will continue to increase.

[0085] When time T3 arrives, the controller detects that Vq has increased to equal the fifth threshold Ven. At this time, the controller provides a control drive current Isk3 to the gate of the first switch to control the gate voltage of the first switch to decrease, thereby improving the turn-off efficiency of the first switch and reducing the turn-off loss of the first switch.

[0086] At time T4, Vg decreases until the first switch is completely turned off. At this point, Vq equals the operating voltage Vbus of the DC bus.

[0087] In some feasible implementations, as described above, after the first switch turns off, as the gate voltage of the first switch decreases at a first rate of change, the internal resistance of the first switch gradually increases. At this time, if the current flowing through the first switch is within the normal range, i.e., the current does not increase abnormally, the voltage difference between the first and second electrodes of the first switch will not increase rapidly as the internal resistance gradually increases, thereby reducing the voltage stress and EMI generated by the first switch. In this case, the controller can adopt a different control method than when the current increases abnormally (i.e.,...). Figure 6 The control method shown controls the first switch to turn off, so as to further improve the turn-off speed and reduce the turn-off loss of the first switch while ensuring that the voltage stress and EMI generated by the first switch are small.

[0088] Specifically, to determine whether the current flowing through the first switching transistor is within the normal range, the controller, while controlling the gate voltage of the first switching transistor to decrease at a first rate of change, detects the voltage difference between the first and second electrodes of the first switching transistor and the gate voltage of the first switching transistor. When the controller detects that the gate voltage of the first switching transistor has decreased to be equal to or less than a third threshold, while the voltage difference between the first and second electrodes of the first switching transistor is still less than the first threshold, it means that the voltage difference between the first and second electrodes of the first switching transistor is increasing slowly, i.e., the current flowing through the first switching transistor is within the normal range. The third threshold is less than the second threshold; for example, the second threshold ranges from 6 to 7 volts, and the third threshold ranges from 4 to 5 volts.

[0089] Furthermore, when the current flowing through the first switching transistor is within the normal range, the controller switches the rate of decrease of the gate voltage of the first switching transistor from a first rate of change to a third rate of change, and the absolute value of the third rate of change is less than the absolute value of the first rate of change, thereby slowing down the rate of decrease of the gate voltage of the first switching transistor. As can be seen from the above, by controlling the rate of decrease of the gate voltage of the first switching transistor to switch from the first rate of change to a third rate of change with a smaller absolute value, the controller can effectively control the voltage stress generated by the first switching transistor and reduce EMI.

[0090] In some feasible implementations, when the current flowing through the first switch is within a normal range, if the current flowing through the first switch is within a normal, relatively small range when the gate voltage of the first switch decreases at a third rate of change, then the voltage stress and EMI generated by the first switch during turn-off are very small. For example, such as... Figure 5 As shown, when the current flowing through the first switching transistor is between 0A and 800A, it is within the normal range. Furthermore, when the current flowing through the first switching transistor is between 0A and 150A, it is within the normal lower range, and the current flowing through the first switching transistor is very small. In this case, the controller can maximize the turn-off efficiency and reduce turn-off losses by promptly controlling the rapid turn-off of the first switching transistor. Simultaneously, because the current flowing through the first switching transistor is very small, the voltage stress and EMI generated during rapid turn-off remain relatively low.

[0091] Specifically, during the process of the gate voltage of the first switch decreasing at a third rate of change, when the controller detects that the duration of the gate voltage decrease at the third rate of change is equal to or greater than a first time threshold, and the voltage difference between the first and second electrodes of the first switch is still less than the first threshold, it means that the current flowing through the first switch is within a normal, relatively small range. At this time, the controller promptly controls the rate of change of the gate voltage of the first switch to switch from the third rate of change to a fourth rate of change, and the absolute value of the fourth rate of change is greater than the third rate of change. This allows the controller to control the gate voltage of the first switch to decrease rapidly until the first switch is completely turned off. It can be understood that by immediately controlling the rate of change of the gate voltage of the first switch to a fourth rate of change with a larger absolute value when the controller detects that the current flowing through the first switch is within a normal, relatively small range, the controller can control the first switch to turn off rapidly, thereby maximizing the turn-off efficiency of the first switch and reducing turn-off losses. Simultaneously, because the current flowing through the first switch is very small, the first switch can still maintain low voltage stress and low EMI during rapid turn-off. For example, the range of the first time threshold mentioned above includes 10 nanoseconds to 30 nanoseconds.

[0092] To facilitate understanding of the specific process by which the controller turns off the first switching transistor when the current is within a normal, relatively small range, the following content combines... Figure 7 To illustrate, Figure 7 This is another signal waveform diagram of the first switching transistor provided in an embodiment of this application. Figure 7 The PWM signal shown is the pulse width modulation signal of the first switching transistor, Vg is the gate voltage of the first switching transistor, Ig is the drive current provided by the controller to the gate of the first switching transistor, and Vq is the voltage difference between the first electrode and the second electrode of the first switching transistor.

[0093] When time T0 arrives, the controller receives the PWM signal and switches to a low level, indicating that the first switch has turned off. At this time, the controller provides a drive current Isk1 to the gate of the first switch to control Vg to decrease rapidly at a first rate of change.

[0094] At time T1, the controller detects that Vg equals the third threshold Vsk1, while Vq is still less than the first threshold VL, indicating that the current flowing through the first switch is within the normal range. The controller provides a drive current Isk2 to the gate of the first switch to control Vg to decrease at a third rate of change. The absolute value of the third rate of change is less than the absolute value of the first rate of change, meaning that the rate of Vg decrease is slower, thereby reducing voltage stress and EMI generated by the first switch.

[0095] When time T2 arrives, if the controller detects that the duration for which Vg decreases at the third rate of change is greater than or equal to the first time threshold Tk, while Vq remains less than the first threshold VL, it indicates that the current flowing through the first switch is within a normal, relatively small range. At this time, in order to effectively improve the turn-off efficiency of the first switch and reduce turn-off losses, the controller provides a drive current Isk4 to the gate of the first switch to control Vg to decrease rapidly.

[0096] When time T3 arrives, Vg decreases until the first switch is completely turned off. At this time, Vq is equal to the operating voltage Vbus of the DC bus.

[0097] In some feasible implementations, when the current flowing through the first switch is within the normal range, if the current flowing through the first switch is greater than the aforementioned smaller normal range and within the normal light load range when the gate voltage of the first switch decreases at a third rate of change, then the voltage stress and EMI generated by the first switch during turn-off are relatively small. For example, such as... Figure 5 As shown, when the absolute value of the current flowing through the first switching transistor is between 200A and 400A, the current flowing through the first switching transistor is within the normal light load range, meaning the current flowing through the first switching transistor is relatively small. At this time, the controller can improve the turn-off efficiency and reduce turn-off losses by controlling the first switching transistor to turn off quickly. Simultaneously, because the current flowing through the first switching transistor is relatively small, the voltage stress and EMI generated during rapid turn-off can still be kept low.

[0098] Specifically, in some feasible implementations, during the process of the gate voltage of the first switch decreasing at a third rate of change, when the controller detects that the duration of the time for the gate voltage of the first switch to decrease at the third rate of change is equal to or greater than a first time threshold, and the voltage difference between the first electrode and the second electrode of the first switch has increased to be greater than or equal to the first threshold, it means that the current flowing through the first switch is greater than the aforementioned normal small range. At this time, the controller controls the gate voltage of the first switch to continue decreasing at the third rate of change. Further, when the gate voltage of the first switch decreases at the third rate of change, if the controller detects that the absolute value of the rate of change of the voltage difference between the first electrode and the second electrode of the first switch is less than or equal to the voltage difference rate of change threshold, it can determine that the current flowing through the first switch is within the normal light load range. The magnitude of the current flowing through the first switch is positively correlated with the magnitude of the rate of change of the voltage difference between the first electrode and the second electrode of the first switch.

[0099] Alternatively, in some feasible implementations, the magnitude of the current flowing through the first switch is negatively correlated with the time it takes for the voltage difference between the first and second electrodes of the first switch to increase from a first voltage difference to a second voltage difference. Therefore, if the gate voltage of the first switch continues to decrease at a third rate of change, when the controller detects that the time it takes for the voltage difference between the first and second electrodes of the first switch to increase from the first voltage difference to the second voltage difference is greater than or equal to a second time threshold, it can be determined that the current flowing through the first switch is within the normal light-load range. For example, the value of the second time threshold ranges from 10 nanoseconds to 30 nanoseconds.

[0100] Furthermore, after determining that the current flowing through the first switch is within the normal light-load range, the controller switches the rate of decrease of the gate voltage of the first switch from the third rate of decrease to the fifth rate of decrease, with the absolute value of the fifth rate of decrease being greater than that of the third rate of decrease. This allows the gate voltage of the first switch to decrease more rapidly until the first switch is completely turned off. It is understandable that by controlling the first switch to turn off more quickly, the controller can improve the turn-off efficiency of the first switch and reduce turn-off losses. Simultaneously, because the current flowing through the first switch is relatively small, the voltage stress and EMI generated during rapid turn-off remain relatively low.

[0101] To facilitate understanding of the specific process by which the controller turns off the first switching transistor when the current is within the normal light load range, the following content combines... Figure 8 To illustrate, Figure 8 This is another schematic diagram of a signal waveform for the first switching transistor provided in an embodiment of this application. Wherein, Figure 8 The PWM signal shown is the pulse width modulation signal of the first switching transistor, Vg is the gate voltage of the first switching transistor, Ig is the drive current of the first switching transistor, and Vq is the voltage difference between the first electrode and the second electrode of the first switching transistor.

[0102] When time T0 arrives, the controller receives the PWM signal and switches to a low level, indicating that the first switch has turned off. At this time, the controller provides a drive current Isk1 to the gate of the first switch to control the gate voltage Vg of the first switch to decrease rapidly at a first rate of change.

[0103] At time T1, the controller detects that Vg equals the third threshold Vsk1, while Vq is still less than the first threshold VL, indicating that the current flowing through the first switch is within the normal range. To reduce the voltage stress and EMI generated by the first switch, the controller provides a drive current Isk2 to the gate of the first switch to control Vg to decrease at a third rate of change. The absolute value of the third rate of change is less than the absolute value of the first rate of change, meaning that the rate of Vg decrease is slower, thereby reducing the voltage stress and EMI generated by the first switch.

[0104] When time T2 arrives, the controller detects that the duration for which Vg decreases at the third rate of change is equal to the first time threshold Tk, while Vq has increased to a level greater than the first threshold VL. This indicates that the current flowing through the first switch is greater than the normal minimum range. The controller then controls Vg to continue decreasing at the third rate of change.

[0105] When time T3 arrives, the controller detects that the time it takes for Vq to increase from the first voltage difference VL to the second voltage difference VH is greater than or equal to the second time threshold, or the absolute value of the rate of change of Vq is less than or equal to the voltage difference change rate threshold. This means that the current flowing through the first switch is within the normal light load range. To improve the turn-off efficiency of the first switch and reduce turn-off losses in a timely manner, the controller provides a drive current Isk3 to the gate of the first switch to control the gate voltage Vg of the first switch to decrease rapidly.

[0106] At time T4, Vg decreases until the first switch is completely turned off. At this point, Vq equals the operating voltage Vbus of the DC bus.

[0107] It should be noted that, with Figure 8 The difference lies in the specific process of the controller turning off the first switch when the current is within the normal light load range. Figure 7 In the specific process of the controller controlling the first switch to turn off when the current is within a normal, relatively small range, the controller can quickly determine whether the current of the first switch is small based on the voltage difference between the first and second electrodes of the first switch when the gate voltage of the first switch decreases at a third rate of change for a duration equal to a first time threshold. Therefore, when the current of the first switch is small, the controller promptly controls the gate voltage of the first switch to decrease rapidly, thereby maximizing the turn-off efficiency of the first switch and minimizing turn-off losses. In contrast, Figure 7 The specific procedure shown only applies when the current of the first switching transistor is within the normal light load range. When the current of the first switching transistor is within the normal lower range, Figure 8 In the specific process shown, the controller controls the gate voltage of the first switching transistor to decrease rapidly at a late time, resulting in insufficient turn-off efficiency of the first switching transistor.

[0108] In some feasible implementations, when the current flowing through the first switch is within the normal range, if the current flowing through the first switch exceeds the aforementioned normal light load range and falls within the normal heavy load range when the gate voltage of the first switch decreases at a third rate of change, then the voltage stress and EMI generated by the first switch during turn-off are relatively large. For example, such as... Figure 5 As shown, when the current flowing through the first switching transistor is between 400A and 600A, the current flowing through the first switching transistor is within the normal heavy load range, meaning the current flowing through the first switching transistor is relatively large. At this time, the controller reduces voltage stress and EMI by controlling the turn-off speed of the first switching transistor.

[0109] Specifically, in some feasible implementations, during the process of the gate voltage of the first switch decreasing at a third rate of change, when the controller detects that the duration of the time for the gate voltage of the first switch to decrease at the third rate of change is equal to or greater than a first time threshold, and the voltage difference between the first electrode and the second electrode of the first switch has increased to be greater than or equal to the first threshold, it means that the current flowing through the first switch is greater than the aforementioned normal minimum range. At this time, the controller controls the gate voltage of the first switch to continue decreasing at the third rate of change. Further, when the gate voltage of the first switch decreases at the third rate of change, if the controller detects that the absolute value of the rate of change of the voltage difference between the first electrode and the second electrode of the first switch is greater than the voltage difference rate of change threshold, it can determine that the current flowing through the first switch is within the normal heavy load range. The magnitude of the current flowing through the first switch is positively correlated with the magnitude of the rate of change of the voltage difference between the first electrode and the second electrode of the first switch.

[0110] Alternatively, in some feasible implementations, the magnitude of the current flowing through the first switch is negatively correlated with the time it takes for the voltage difference between the first and second electrodes of the first switch to increase from a first voltage difference to a second voltage difference. Therefore, if the gate voltage of the first switch continues to decrease at a third rate of change, and the controller detects that the time it takes for the voltage difference between the first and second electrodes of the first switch to increase from a first voltage difference to a second voltage difference is less than a second time threshold, it can be determined that the current flowing through the first switch is within the normal heavy-load range.

[0111] It should be noted that when the current flowing through the first switching transistor is within the normal heavy load range, although the controller can slow down the rate of decrease of the gate voltage of the first switching transistor by adjusting the gate voltage of the first switching transistor to decrease at the third rate of change, thereby controlling the voltage stress and EMI generated by the first switching transistor to decrease, the current flowing through the first switching transistor is large, and the gate voltage of the first switching transistor previously decreased too quickly when decreasing at the first rate of change, resulting in the gate voltage of the first switching transistor still generating large voltage stress and EMI when decreasing at the second rate of change.

[0112] Therefore, when the controller determines that the current flowing through the first switching transistor is within the normal heavy-load range and detects that the voltage difference between the first and second electrodes of the first switching transistor is greater than or equal to the fourth threshold, it controls the gate voltage of the first switching transistor to switch from decreasing at the third rate of change to increasing. It should be noted that by controlling the increase of the gate voltage of the first switching transistor, the controller can offset the effects of a large current in the first switching transistor and the previously excessively rapid decrease in gate voltage, thereby reducing voltage stress and EMI generation.

[0113] In some feasible implementations, the controller can determine the rate of change of the gate voltage of the first switching transistor by the absolute value of the rate of change of the voltage difference between the first and second electrodes of the first switching transistor before controlling the gate voltage of the first switching transistor to increase. Alternatively, the controller can also determine the rate of change of the gate voltage of the first switching transistor by the time it takes for the gate voltage of the first switching transistor to increase from the first voltage difference to the second voltage difference. For specific implementation details, please refer to the specific implementations corresponding to the abnormal increase of the current of the first switching transistor described above, which will not be repeated here.

[0114] Furthermore, during the process of increasing the gate voltage of the first switch, in order to reduce the voltage stress and EMI generated by the first switch while simultaneously improving the turn-off efficiency and reducing turn-off losses, the controller can control the gate voltage of the first switch to decrease when it detects that the voltage difference between the first electrode and the second electrode of the first switch is greater than or equal to a fifth threshold. This allows the gate voltage of the first switch to decrease rapidly until the first switch is completely turned off. For specific implementation details, please refer to the specific embodiments corresponding to the abnormal increase in the current of the first switch described above; these will not be repeated here.

[0115] To facilitate understanding of the specific process by which the controller turns off the first switching transistor when the current is within the normal heavy load range, the following content combines... Figure 9 To illustrate, Figure 9 This is another schematic diagram of a signal waveform for the first switching transistor provided in an embodiment of this application. Wherein, Figure 9The PWM signal shown is the pulse width modulation signal of the first switching transistor, Vg is the gate voltage of the first switching transistor, Ig is the drive current of the first switching transistor, and Vq is the voltage difference between the first electrode and the second electrode of the first switching transistor.

[0116] When time T0 arrives, the controller receives the PWM signal and switches to a low level, indicating that the first switch has turned off. At this time, the controller provides a drive current Isk1 to the gate of the first switch to control the gate voltage Vg of the first switch to decrease rapidly at a first rate of change.

[0117] At time T1, the controller detects that Vg equals the third threshold Vsk1, while Vq is still less than the first threshold VL, indicating that the current flowing through the first switch is within the normal range. To reduce the voltage stress and EMI generated by the first switch, the controller provides a drive current Isk2 to the gate of the first switch to control Vg to decrease at a third rate of change. The absolute value of the third rate of change is less than the absolute value of the first rate of change, meaning that the rate of Vg decrease is slower, thereby reducing the voltage stress and EMI generated by the first switch.

[0118] At time T2, the controller detects that the duration of Vg decreasing at the third rate of change is equal to the first time threshold Tk, while Vq has increased to a level greater than the first threshold VL. This indicates that the current flowing through the first switch is greater than the normal lower range. The controller then controls Vg to continue decreasing at the third rate of change. If, while Vg is decreasing at the third rate of change, the controller detects that the duration of Vq increasing from the first voltage difference VL to the second voltage difference VH is less than the second time threshold, or the absolute value of the rate of change of Vq is greater than the voltage difference rate of change threshold, it means that the current flowing through the first switch is within the normal heavy load range. Simultaneously, the controller determines the magnitude of the rate of change of Vg in subsequent stages based on the rate of change of Vq or the duration of Vq increasing from VL to VH.

[0119] At time T3, the controller detects that Vq has increased to equal the fourth threshold Vst. At this point, the controller provides a drive current Isp to the gate of the first switch to control Vg to increase at the rate of change determined in the above steps. As can be seen from the above, the controller's control of Vg increase can offset the negative effects of the large current of the first switch and the previously rapid decrease in gate voltage, thereby reducing the voltage stress and EMI generated by the first switch. Furthermore, although Vg begins to rise, the first switch is still not fully turned off, so Vq will continue to increase.

[0120] When time T4 arrives, the controller detects that Vq has increased to equal the fifth threshold Ven. At this time, the controller provides a control drive current Isk3 to the gate of the first switch to control the gate voltage of the first switch to decrease rapidly until it is completely turned off, thereby improving the turn-off efficiency of the first switch and reducing the turn-off loss of the first switch.

[0121] It should be noted that, with Figure 9 The difference lies in the specific process of the controller turning off the first switch when the current is within the normal heavy load range. Figure 6 In the illustrated process of the controller turning off the first switching transistor when the current abnormally increases, when the voltage difference between the first and second electrodes of the first switching transistor has increased to equal the first threshold, the controller can quickly determine whether the current of the first switching transistor has abnormally increased based on the magnitude of the gate voltage. Therefore, when the current of the first switching transistor abnormally increases, the controller can promptly control the gate voltage of the first switching transistor to mitigate the change, avoiding excessive voltage stress and EMI. In contrast, Figure 9 The specific procedure shown only applies when the current of the first switching transistor is within the normal heavy load range. When the current of the first switching transistor increases abnormally, Figure 9 In the specific process shown, the timing of the controller slowing down the rate of change of the gate voltage of the first switch is not timely enough, which may cause the first switch to generate large voltage stress and EMI.

[0122] It should be noted that the turn-off process of the second switch connected in series with the first switch in the power changing device can refer to the specific implementation method of the first switch described above, and will not be repeated here in the embodiments of this application.

[0123] Please see Figure 10 , Figure 10 This is a flowchart illustrating a control method for a power conversion device provided in this application. The control method for a power conversion device provided in this application is applicable to... Figures 3 to 9 The controller in the corresponding specific implementation. Specifically, the control method for the power conversion device may include the following steps:

[0124] S101. When the turn-off time of the first switch arrives, control the gate voltage of the first switch to decrease at a first rate of change.

[0125] It is understandable that when the first switch turns off, the controller controls the gate voltage of the first switch to decrease at a first rate of change, which can effectively reduce the voltage stress and EMI generated by the first switch.

[0126] For a detailed implementation of S101, please refer to the above. Figures 3 to 9 The implementation method executed by the controller is not described in detail in this application embodiment.

[0127] S102, when the voltage difference between the first electrode and the second electrode increases to be greater than or equal to the first threshold and the gate voltage is greater than the second threshold, the rate of change of the control gate voltage decrease is switched to the second rate of change, and after the rate of change of the control gate voltage decrease is switched to the second rate of change, the control gate voltage first increases and then decreases until the first switch is turned off; the absolute value of the second rate of change is less than the absolute value of the first rate of change.

[0128] Furthermore, when the controller detects that the voltage difference between the first electrode and the second electrode is greater than or equal to the first threshold, it can quickly determine whether the current of the first switching transistor has increased abnormally based on the magnitude of the gate voltage. Specifically, when the voltage difference is greater than or equal to the first threshold, if the gate voltage is still greater than the second threshold, it indicates that the current flowing through the first switching transistor has increased abnormally. At this time, the controller first controls the rate of change of the gate voltage to switch to the second rate of change to slow down the rate of change of the gate voltage, and then controls the gate voltage to increase to counteract the excessively rapid decrease in voltage difference caused by the abnormal increase in current, thereby timely controlling the voltage stress and EMI reduction of the first switching transistor and avoiding damage to the first switching transistor caused by the abnormal increase in current. Then, the controller controls the gate voltage to switch from increasing to decreasing until the first switching transistor is turned off, thereby improving the turn-off efficiency of the first switching transistor and reducing turn-off losses.

[0129] For a detailed implementation of S102, please refer to the above. Figures 3 to 9 The implementation method executed by the controller is not described in detail in this application embodiment.

[0130] S103. When the voltage difference is less than the first threshold and the gate voltage decreases to less than or equal to the third threshold, the rate of change of the gate voltage decrease is switched to the third rate of change. When the time length for which the gate voltage decreases at the third rate of change is greater than or equal to the first time threshold and the voltage difference is less than the first threshold, the rate of change of the gate voltage decrease is switched to the fourth rate of change until the first switch is turned off. The third threshold is less than the second threshold, the absolute value of the third rate of change is less than the absolute value of the first rate of change, and the absolute value of the third rate of change is less than the absolute value of the fourth rate of change.

[0131] Understandably, when the gate voltage decreases at a first rate of change, if the voltage difference is still less than the first threshold when the gate voltage decreases to be equal to or less than the third threshold, it indicates that the current of the first switch is within the normal range, i.e., the current has not increased abnormally. At this time, the controller first controls the rate of change of the gate voltage to switch to the third rate of change to control the voltage stress and EMI of the first switch to decrease. Then, when the controller detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to the first time threshold, if the voltage difference is still less than the first threshold, it indicates that the current flowing through the first switch is within a normal small range, i.e., the current is very small, and the voltage stress and EMI generated by the turn-off of the first switch will also be very small. At this time, the controller can accelerate the turn-off speed of the first switch by controlling the gate voltage to decrease rapidly at a fourth rate of change until the first switch is completely turned off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses.

[0132] For a detailed implementation of S103, please refer to the above. Figures 3 to 9 The implementation method executed by the controller is not described in detail in this application embodiment.

[0133] In an optional embodiment, the method further includes: when the time duration for which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change and the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, controlling the rate of change of the gate voltage to switch to a fifth rate of change; wherein the absolute value of the third rate of change is less than the absolute value of the fifth rate of change.

[0134] Understandably, when the gate voltage decreases at the third rate of change, if the power conversion device detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to the first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. At this time, the power conversion device controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, when the power conversion device detects that the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, it indicates that the current flowing through the first switch is within the normal light load range, i.e., the current flowing through the first switch is relatively small. Therefore, the voltage stress and EMI generated by the first switch turning off will also be relatively small. At this time, the power conversion device switches the rate of change of the gate voltage to the fifth rate of change to control the first switch to turn off quickly, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses, demonstrating strong applicability.

[0135] In an optional embodiment, the method further includes: when the time duration for which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change and the time duration for which the voltage difference increases from the first voltage difference to the second voltage difference is greater than or equal to a second time threshold, controlling the rate of change of the gate voltage to switch to a fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change; and the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0136] Understandably, when the gate voltage decreases at the third rate of change, if the power conversion device detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to the first time threshold, and if the voltage difference has already increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal small range. At this time, the power conversion device controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, when the power conversion device detects that the time for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to the second time threshold, it indicates that the current flowing through the first switch is within the normal light load range, i.e., the current flowing through the first switch is relatively small. Therefore, the voltage stress and EMI generated by the first switch turning off will also be relatively small. At this time, the power conversion device switches the rate of change of the gate voltage to the fifth rate of change to control the first switch to turn off quickly, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses, demonstrating strong applicability.

[0137] In an optional embodiment, the method further includes: when the time length during which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change, and the absolute value of the rate of change of the voltage difference is greater than a voltage difference rate of change threshold and the voltage difference is greater than or equal to a fourth threshold, controlling the gate voltage to first increase and then decrease until the first switch is turned off.

[0138] Understandably, when the gate voltage decreases at a third rate of change, if the power conversion device detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. At this time, the power conversion device controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, when the power conversion device detects that the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold, it indicates that the current flowing through the first switch is within the normal heavy load range, meaning the current flowing through the first switch is relatively large. Therefore, the voltage stress and EMI generated by the first switch turning off will also be relatively large. In this case, the power conversion device first controls the gate voltage to increase to offset the excessively rapid decrease in voltage difference caused by the large current, thereby controlling the voltage stress and EMI of the first switch to decrease. Then, the power conversion device controls the gate voltage to switch from increasing to decreasing until the first switch turns off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses.

[0139] In an optional embodiment, the method further includes: when the time length during which the gate voltage decreases at a third rate of change is greater than or equal to a first time threshold and the voltage difference is greater than or equal to the first threshold, controlling the rate of change of the gate voltage to remain at the third rate of change; when the gate voltage continues to decrease at the third rate of change, and the time length during which the voltage difference increases from the first voltage difference to the second voltage difference is less than a second time threshold and the voltage difference is greater than or equal to a fourth threshold, controlling the gate voltage to first increase and then decrease until the first switch is turned off; the first voltage difference and the second voltage difference are less than the DC bus voltage.

[0140] Understandably, when the gate voltage decreases at a third rate of change, if the power conversion device detects that the time for the gate voltage to decrease at the third rate of change is greater than or equal to a first time threshold, and if the voltage difference has already increased to be equal to or greater than the first threshold, it indicates that the current flowing through the first switch is greater than the normal minimum range. In this case, the power conversion device controls the gate voltage to continue decreasing at the third rate of change to reduce voltage stress and EMI generation. Furthermore, if the power conversion device detects that the time for the voltage difference to increase from the first voltage difference to the second voltage difference is less than a second time threshold, it indicates that the current flowing through the first switch is within the normal heavy load range, meaning the current flowing through the first switch is relatively large. Therefore, the voltage stress and EMI generated by the first switch turning off will also be relatively large. In this case, the power conversion device first controls the gate voltage to increase to offset the excessively rapid decrease in voltage difference caused by the large current, thereby controlling the voltage stress and EMI of the first switch to decrease. Then, the power conversion device controls the gate voltage to switch from increasing to decreasing until the first switch turns off, thereby improving the turn-off efficiency of the first switch and reducing turn-off losses.

[0141] In an alternative implementation, the first threshold satisfies:

[0142]

[0143] Where Vbus is the DC bus voltage, N is a positive integer greater than or equal to 2, n is equal to 1 or 2, and n is less than N.

[0144] It is understandable that the value of the first threshold is related to the DC bus voltage, and the specific value of the first threshold can be flexibly adjusted according to actual needs (N and n are adjustable), with a wide range of application scenarios.

[0145] In one alternative implementation, the second threshold ranges from 6 to 7 volts, and the third threshold ranges from 4 to 5 volts.

[0146] Understandably, when the first switching transistor decreases at a first rate of change, if the voltage difference is greater than or equal to a first threshold, and the power conversion device detects a gate voltage greater than 7 volts for the first switching transistor, the power conversion device can quickly determine that the current flowing through the first switching transistor has abnormally increased. Furthermore, when the first switching transistor decreases at a first rate of change, if the gate voltage is less than or equal to 5 volts and the voltage difference is less than the first threshold, the power conversion device can determine that the current flowing through the first switching transistor has not abnormally increased. This implementation method is simple and highly reliable.

[0147] In an optional implementation, the first time threshold ranges from 10 to 30 nanoseconds.

[0148] It is understandable that if the voltage difference is still less than the first threshold when the gate voltage decreases at the third rate of change for a duration greater than or equal to 15 nanoseconds, it indicates that the current flowing through the first switch is within a normal small range, that is, the current flowing through the first switch is very small.

[0149] In one optional implementation, the second time threshold is in the range of 15 nanoseconds.

[0150] Understandably, when the gate voltage decreases at a third rate of change, if the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to 15 nanoseconds, it indicates that the current flowing through the first switch is within the normal light load range, meaning the current flowing through the first switch is relatively small. Conversely, if the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is less than 15 nanoseconds, it indicates that the current flowing through the first switch is within the normal heavy load range, meaning the current flowing through the first switch is relatively large.

[0151] Based on the same concept, this application also provides a switch driver chip, which includes the controller in the aforementioned power conversion device. The switch driver chip can be connected to a first switch and a second switch, respectively, and the first and second switches can be turned on or off. Specific implementations of the above-described switch driver chip can be found in the above-described... Figures 3 to 9 The implementation method executed by the controller is not described in detail in this application embodiment.

[0152] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0153] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0154] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0155] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0156] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A power conversion device, characterized in that, The power conversion device includes a controller, a first switch and a second switch connected in series; the gate of the first switch is connected to the controller, the first electrode of the first switch is connected to the second switch, and the second electrode of the first switch is connected to the positive terminal of the DC bus or to the negative terminal of the DC bus. The controller is used for: When the turn-off time of the first switch arrives, the gate voltage of the first switch is controlled to decrease at a first rate of change. When the voltage difference between the first electrode and the second electrode increases to a level greater than or equal to a first threshold, and the gate voltage is greater than a second threshold, the rate of decrease of the gate voltage is controlled to switch to a second rate of decrease. After the rate of decrease of the gate voltage is controlled to switch to the second rate of decrease, the gate voltage is controlled to first increase and then decrease until the first switch is turned off; the absolute value of the second rate of decrease is less than the absolute value of the first rate of decrease; or, When the voltage difference is less than the first threshold and the gate voltage decreases to less than or equal to the third threshold, the rate of decrease of the gate voltage is controlled to switch to the third rate of decrease. When the time length during which the gate voltage decreases at the third rate of decrease is greater than or equal to the first time threshold and the voltage difference is less than the first threshold, the rate of decrease of the gate voltage is controlled to switch to the fourth rate of decrease until the first switch is turned off. The third threshold is less than the second threshold, the absolute value of the third rate of decrease is less than the absolute value of the first rate of decrease, and the absolute value of the third rate of decrease is less than the absolute value of the fourth rate of decrease.

2. The power conversion device according to claim 1, characterized in that, The controller is also used for: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage is maintained at the third rate of change and the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, the rate of change of the gate voltage is controlled to switch to the fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change.

3. The power conversion device according to claim 1, characterized in that, The controller is also used for: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage decreases at the third rate of change and the time for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to the second time threshold, the rate of decrease of the gate voltage is controlled to switch to the fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change; the first voltage difference and the second voltage difference are less than the DC bus voltage.

4. The power conversion device according to claim 1, characterized in that, The controller is also used for: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage is maintained at the third rate of change, and the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold, and the voltage difference is greater than or equal to the fourth threshold, the gate voltage is controlled to first increase and then decrease until the first switch is turned off.

5. The power conversion device according to claim 1, characterized in that, The controller is also used for: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage decreases at the third rate of change, and the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is less than the second time threshold, and the voltage difference is greater than or equal to the fourth threshold, the gate voltage is controlled to increase first and then decrease until the first switch is turned off; the first voltage difference and the second voltage difference are less than the DC bus voltage.

6. The power conversion device according to any one of claims 1 to 5, characterized in that, The first threshold satisfies: in, The DC bus voltage is N, which is a positive integer greater than or equal to 2, and n is equal to 1 or 2, and n is less than N.

7. The power conversion device according to any one of claims 1 to 5, characterized in that, The second threshold value ranges from 6 to 7 volts, and the third threshold value ranges from 4 to 5 volts.

8. The power conversion device according to any one of claims 1 to 5, characterized in that, The first time threshold ranges from 10 to 30 nanoseconds.

9. The power conversion device according to claim 3 or 5, characterized in that, The second time threshold ranges from 10 to 30 nanoseconds.

10. A control method for a power conversion device, applied to the power conversion device, the power conversion device comprising a first switching transistor and a second switching transistor connected in series; the gate of the first switching transistor is connected to a controller, the first electrode of the first switching transistor is connected to the second switching transistor, and the second electrode of the first switching transistor is connected to the positive terminal of a DC bus or to the negative terminal of the DC bus, characterized in that... The method includes: When the turn-off time of the first switch arrives, the gate voltage of the first switch is controlled to decrease at a first rate of change. When the voltage difference between the first electrode and the second electrode increases to a level greater than or equal to a first threshold, and the gate voltage is greater than a second threshold, the rate of decrease of the gate voltage is controlled to switch to a second rate of decrease. After the rate of decrease of the gate voltage is controlled to switch to the second rate of decrease, the gate voltage is controlled to first increase and then decrease until the first switch is turned off; the absolute value of the second rate of decrease is less than the absolute value of the first rate of decrease; or, When the voltage difference is less than the first threshold and the gate voltage decreases to less than or equal to the third threshold, the rate of decrease of the gate voltage is controlled to switch to the third rate of decrease. When the time length during which the gate voltage decreases at the third rate of decrease is greater than or equal to the first time threshold and the voltage difference is less than the first threshold, the rate of decrease of the gate voltage is controlled to switch to the fourth rate of decrease until the first switch is turned off. The third threshold is less than the second threshold, the absolute value of the third rate of decrease is less than the absolute value of the first rate of decrease, and the absolute value of the third rate of decrease is less than the absolute value of the fourth rate of decrease.

11. The method according to claim 10, characterized in that, The method further includes: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage is maintained at the third rate of change and the absolute value of the rate of change of the voltage difference is less than or equal to the voltage difference rate of change threshold, the rate of change of the gate voltage is controlled to switch to the fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change.

12. The method according to claim 10, characterized in that, The method further includes: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage decreases at the third rate of change and the time for the voltage difference to increase from the first voltage difference to the second voltage difference is greater than or equal to the second time threshold, the rate of decrease of the gate voltage is controlled to switch to the fifth rate of change; the absolute value of the third rate of change is less than the absolute value of the fifth rate of change; the first voltage difference and the second voltage difference are less than the DC bus voltage.

13. The method according to claim 10, characterized in that, The method further includes: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage is maintained at the third rate of change, and the absolute value of the rate of change of the voltage difference is greater than the voltage difference rate of change threshold, and the voltage difference is greater than or equal to the fourth threshold, the gate voltage is controlled to first increase and then decrease until the first switch is turned off.

14. The method according to claim 10, characterized in that, The method further includes: When the time length during which the gate voltage decreases at the third rate of change is greater than or equal to a first time threshold, and the voltage difference is greater than or equal to the first threshold, the rate of change of the gate voltage decrease is controlled to remain at the third rate of change. When the gate voltage decreases at the third rate of change, and the time it takes for the voltage difference to increase from the first voltage difference to the second voltage difference is less than the second time threshold, and the voltage difference is greater than or equal to the fourth threshold, the gate voltage is controlled to increase first and then decrease until the first switch is turned off; the first voltage difference and the second voltage difference are less than the DC bus voltage.

15. A switch driver chip, characterized in that, The switch driver chip includes the controller as described in any one of claims 1 to 9, and the switch driver chip is connected to the first switch transistor and the second switch transistor; The switch driver chip is used to drive the first switch to turn on or off, and to drive the second switch to turn on or off.

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