A converter circuit for converting a digital signal into ttfs encoded spikes

Abstract

This invention relates to the fields of signal conversion and neuromorphic processing, specifically to a converter circuit for converting digital signals into TTFS encoded spikes. The invention employs a fully integrated architecture synchronized with an on-chip clock. A counter unit provides the time reference, and delay units and dynamic delayers are constructed to generate hierarchical time encoding, achieving controllable clock cycle delay. A digital control switch is then used to achieve a linear timing mapping from digital input to the delay amount. Finally, a TTFS pulse generation module is combined to produce a single, equal-width TTFS spike output, ensuring high timing accuracy and robustness from digital input to TTFS spike output. This invention completely eliminates timing skew and errors caused by external transmission paths, ensuring signal accuracy. It effectively meets the needs of large-scale, high-time-sensitivity scenarios for real-time, high-precision TTFS encoding, providing technical support for the implementation of neuromorphic computing systems and significantly improving the overall performance and reliability of neuromorphic computing systems.

Description

Technical Field

[0001] This invention relates to the fields of signal conversion and neuromorphic processing, specifically to a digital signal conversion converter circuit based on first time pulse (TTFS) encoded spikes. Background Technology

[0002] With the rapid development of artificial intelligence and deep learning algorithms, as well as the in-depth research on biomimetic neural networks and neuromorphic computing, how to efficiently achieve real-time signal processing in neuromorphic systems has become a hot topic of concern in industry and academia. Compared with the traditional von Neumann architecture, neuromorphic computing, by mimicking the information processing methods of the human brain, achieves data processing through event-driven and sparse coding, demonstrating significant advantages in low power consumption, parallel processing, and high adaptability.

[0003] In recent years, neuromorphic systems based on spike information processing have attracted widespread attention. Among them, TTFS (Time-to-First-Spike) coding has become an ideal signal format for achieving efficient neural signal processing due to its sparse coding, low power consumption, and efficient information transmission. In TTFS coding, the signal value is represented by the trigger time of the first spike, and the time difference between spikes contains the transmitted information. The key to TTFS coding's low power consumption lies in its event-driven nature: information is represented only by the first occurrence of the spike, rather than a continuous data stream. This means that when there is no information update, the circuit can remain inactive, significantly reducing unnecessary circuit switching activities and thus lowering dynamic power consumption. In practical applications, how to achieve high-precision conversion from digital signals to TTFS-coded spikes has become one of the key factors affecting the performance of neuromorphic computing systems.

[0004] However, existing technologies still lack a fully integrated, high-precision, and robust solution for converting digital inputs to TTFS-encoded spike signals. High-precision conversion of TTFS encoding faces significant technical challenges and design complexity. This is because the precise value of information in TTFS encoding is entirely determined by the triggering time of the spike; timing skew will directly lead to deviations in the encoded value, thus affecting the accuracy and reliability of the entire system.

[0005] In existing implementations, TTFS encoded signals are often generated through external conversion circuits or modules located outside the chip. This approach introduces transmission delays and signal path inconsistencies, leading to deviations in the arrival times of different signals, causing timing skew, affecting the time relationships between signals, and ultimately reducing the overall timing accuracy and encoding precision of the system. Especially in large-scale neuromorphic computing systems with high real-time requirements, due to differences in connection delays and layout between modules, externally generated spikes are insufficient to meet the demands of high-precision timing control, further exacerbating the system performance bottleneck.

[0006] Therefore, the industry urgently needs a universal, high-precision, and robust solution that can directly convert digital data into TTFS encoded spikes with high precision inside the chip, in order to overcome the limitations of existing technologies and improve the overall performance and reliability of neuromorphic computing systems. Summary of the Invention

[0007] To address the aforementioned problems and shortcomings, and to resolve the difficulty of achieving high-precision and robust control in existing digital input to TTFS encoded spike signal conversion circuits under general, large-scale, and high-time-efficiency requirements, this invention provides a digital signal to TTFS encoded spike converter circuit. It is a fully integrated design that achieves high-precision timing control through an on-chip synchronous clock architecture.

[0008] A converter circuit for converting digital signals into TTFS encoded spikes includes a delay control module and a TTFS pulse generation module.

[0009] The delay control module generates precise delay pulses based on the digital input signal, which are then converted into n-bit binary digital signals. <n-1:0>It consists of n cascaded delay branches corresponding to n bits; each delay branch is composed of a dynamic delay unit and a digital control switch connected in parallel, used to realize the linear mapping from digital input value to delay amount, and generate the delay signal DELAY. TTFS The control terminal of the digital control switch in the k-th (1≤k≤n) delay branch is connected to the bit of the converted digital signal. <k-1>Connected.

[0010] The dynamic delay unit includes a first-stage delay unit and an extended cascade unit, used to realize the conversion of the n-bit binary digital signal into bits. <n-1:0>The 2 corresponding to the kth position in (k-1) CLK IN Precise delay of clock cycles.

[0011] The first-stage delay unit has one input terminal and one clock terminal, both connected to the input clock signal CLK. IN The delay unit, the output signal CLK of the first-stage delay unit DELAY Input clock CLK IN Delay by one cycle.

[0012] The extended cascaded unit consists of k-2 (k≥2) counter units and 1 delay unit cascaded sequentially, used to construct 2 (k-2) -1 CLK IN The clock cycle delay chain doubles the delay period. In the extended cascaded unit: the input of the first counter unit is connected to the output CLK of the first-stage delay unit. DELAY The clock terminal of the delay unit is connected to the input clock CLK. IN The input terminals of other counter units and delay units are connected to the DATA generated by the previous stage counter unit. OUT Signal, thereby achieving 2 n -1 CLK IN Precise delay of the cycle.

[0013] The delay unit includes a counter unit, a DFF (D flip-flop), and a two-input AND gate; the input terminal of the delay unit is SIG. DELAY This is the input terminal of its internal counter unit; the DFF input terminal is connected to a high level, and the clock terminal is connected to the DATA output of the counter unit. OUT The signal, output terminal, and clock terminal CLK of the delay unit. IN Perform logic AND generation CLK DELAY The generated CLK DELAY Pulse width and CLK IN To maintain consistency. The counter unit is the basic timing generation module of this invention, consisting of a T'FF (T' flip-flop) and a two-input AND gate; wherein the clock input of T'FF serves as the input SIG of the counter unit. CONT The inverting output terminal QN of T'FF is connected to SIG. CONT Perform logical AND to generate DATA OUT Signal.

[0014] The TTFS pulse generation module is used to generate pulses from the delayed signal DELAY. TTFS High-precision TTFS peaks are extracted using a dual DFF architecture.

[0015] Furthermore, the specific structure of the TTFS pulse generation module is as follows: the clock input of the first DFF is connected to the delay signal DELAY output by the delay control module. TTFS The clock input of the second DFF is connected to DELAY. TTFS The inverted signal is given, and the inputs of both DFFs are connected to a high level. The outputs of the two DFFs are ANDed through an AND gate to extract the AND signal with CLK. IN TTFS spikes with equal pulse widths arrive at times relative to the input clock CLK. IN The first pulse was delayed by 2 seconds. n (n is the bit of the digital signal being converted) <n-1:0>(number of bits) minus BIT <n-1:0>The corresponding decimal value of CLK IN The clock cycle is such that the extracted pulse corresponds exactly to a single pulse output that is converted from binary code to TTFS code.

[0016] Furthermore, the specific operation mode of the kth delay branch is as follows: when the converted digital signal BIT <n-1:0>China BIT <k-1>When = 1, the digital control switch in the corresponding k-th delay branch is turned on, and the dynamic delay unit of this stage is bypassed (i.e., no delay is introduced); when BIT <k-1>When = 0, the digital control switch in the corresponding k-th delay branch is turned off, and the dynamic delay unit in this delay branch is activated (i.e., a delay is introduced). Through this binary weighted combination control, the total delay cycle number of the delay control module can be expressed as: BIT <k-1>=b k b k The value can be 0 or 1.

[0017] Furthermore, when k=1, the dynamic delay unit only includes the first-level delay unit and does not include the extended cascade unit.

[0018] Furthermore, the converter circuit that converts the aforementioned digital signal into TTFS encoded spikes is applied to neuromorphic computing in a fully integrated design for neuromorphic computing systems.

[0019] In summary, this invention employs a fully integrated architecture synchronized with the on-chip clock. A counter unit provides the time base, and a delay unit and dynamic delayer generate hierarchical time encoding to achieve controllable clock cycle delay. A digital control switch further enables linear timing mapping from digital input to the delay amount. Finally, a TTFS pulse generation module generates a single, equal-width TTFS spike output, ensuring high timing accuracy and robustness from digital input to TTFS spike output. This invention completely eliminates timing skew and errors caused by external transmission paths, ensuring signal accuracy. It effectively meets the demands of large-scale, high-time-sensitivity scenarios for real-time, high-precision TTFS encoding, providing technical support for the implementation of neuromorphic computing systems and significantly improving the overall performance and reliability of neuromorphic computing systems. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the counter unit of the present invention;

[0021] Figure 2 This is a schematic diagram of the delay unit of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of the dynamic delay device of the present invention;

[0023] Figure 4 This is a schematic diagram of the delay control module of the present invention;

[0024] Figure 5 This is a schematic diagram of the TTFS pulse generation module of the present invention;

[0025] Figure 6 This is a timing diagram of the delay unit in the embodiment;

[0026] Figure 7 This is a timing diagram of a digital-to-TTFS encoded spike converter for an example. Detailed Implementation

[0027] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0028] A converter circuit for converting digital signals into TTFS-encoded spikes includes a delay control module and a TTFS pulse generation module. A counter unit provides a time base, and a delay unit and a dynamic delayer are constructed to generate hierarchical time encoding. The dynamic delayer is used to achieve controllable clock cycle delay. A digital control switch is then used to achieve a linear timing mapping from the digital input to the delay amount, ensuring high timing accuracy and robustness from the digital input to the TTFS spike output. Finally, the TTFS pulse generation module produces a single, equal-width TTFS spike output.

[0029] The counter unit of this invention is constructed based on T'FF, such as... Figure 1 As shown: Each counter unit consists of a T'FF and a two-input AND gate; the clock input of the T'FF serves as the input SIG of the counter unit. CONT The input terminal is connected to a low level, and the inverting output terminal QN is connected to SIG. CONT DATA is generated by performing a logical AND operation using a two-input AND gate. OUT Signal.

[0030] The delay unit of this invention includes a counter unit, a DFF, and a two-input AND gate, such as... Figure 2 As shown: SIG, the input terminal of the delay unit DELAY SIG is the input terminal of its internal counter unit. CONT The DFF input is connected to a high level, and the clock input is connected to the output DATA of the counter unit. OUT The output of the DFF is connected to the clock terminal CLK of the delay unit. IN Generate CLK by performing logical AND operations. DELAY CLK output by the delay unit DELAY With CLK IN The pulse widths are consistent.

[0031] The dynamic delay unit of this invention is constructed based on a counter unit and a delay unit, such as... Figure 3 As shown, it includes two parts: a first-stage delay unit and an extended cascaded unit; used to implement the conversion of the n-bit binary digital signal (BIT). <n-1:0>The 2 corresponding to the k-th position (1≤k≤n) (k-1) CLK IN Precise delay of clock cycles.

[0032] Both the input and clock terminals of the first-stage delay unit are connected to the input clock signal CLK. IN Used to transfer CLK IN Delay by one cycle.

[0033] In the extended cascaded unit, by connecting k-2 (k≥2) counter units in series, a 2 (k-2) A delay chain of -1 clock cycles is then used to double the cycle through a final-stage delay unit, ultimately reaching 2. (k-1) CLK IN Precise delay of the period. It is worth noting that when k=1, the dynamic delay unit only contains the first-stage delay unit and does not contain the extended cascade unit.

[0034] The delay control module of this invention consists of n cascaded delay branches, such as... Figure 4 As shown: Each delay branch consists of a dynamic delay unit and a digital control switch connected in parallel. The control terminal of the k-th digital control switch is connected to the bit of the converted digital signal. <k-1>Connected.

[0035] The specific working principle is as follows: when the converted digital signal BIT <n-1:0>China BIT <k-1>When = 1, the digital control switch in the corresponding k-th delay branch is turned on, and the dynamic delay unit of this stage is bypassed (i.e., no delay is introduced); when BIT <k-1>When the value is 0, the digital control switch in the corresponding k-th delay branch is turned on and off, and the dynamic delay unit at this stage is activated (i.e., a delay is introduced). Through this binary weighted combination method, the final generated delay signal DELAY is... TTFS The total number of delay cycles achieved can be expressed as Where b k The number input BIT represents the number being converted. <n-1:0>The k-th bit <k-1>The value is 0 or 1. This design achieves a linear mapping relationship between digital values ​​and delay quantities, ensuring the accuracy and controllability of the conversion.

[0036] The TTFS pulse generation module of this invention adopts a dual-DFF architecture, such as... Figure 5 As shown; the clock input of the first DFF is connected to the delay signal DELAY. TTFS The clock terminal of the second DFF is connected to DELAY. TTFS The inverted signal is connected to the high level at the data terminals of both DFFs, and their output terminals are ANDed by an AND gate.

[0037] like Figure 6 and Figure 7 As shown, the overall timing control of the present invention has strict synchronization characteristics. Figure 6 This is a timing diagram for the delay unit, showing the input signal SIG. DELAY via input clock CLK IN Processing to obtain CLK DELAY The process, CLK DELAY Frequency and input clock CLK IN Maintain consistency. Figure 7 For an input n-bit binary digital signal BIT <n-1:0>The timing of the transition to the TTFS encoded spike, since the number of cycles of the delay pulse is equal to 2. n Subtract the input bit of the converted number <n-1:0>The corresponding decimal value, therefore the final extracted pulse SPIKE TTFS This corresponds precisely to the single-pulse output of the binary encoding converted to TTFS encoding. Therefore, this design ensures the timing accuracy and signal integrity of the conversion process.

[0038] As can be seen from the above embodiments, the present invention adopts a fully synchronous timing architecture, which avoids the metastability problem in traditional asynchronous design and achieves high-precision conversion of digital signals to TTFS encoded spikes; at the same time, through the implementation method of chip integration, it minimizes signal transmission delay and timing skew, providing technical support for the realization of neuromorphic computing systems.

Claims

1. A converter circuit for converting digital signals into TTFS encoded spikes, characterized in that: Includes a delay control module and a TTFS pulse generation module; The delay control module generates precise delay pulses based on the digital input signal, which are then converted into n-bit binary digital signals. <n-1:0>It consists of n cascaded delay branches corresponding to n bits; each delay branch is composed of a dynamic delay unit and a digital control switch connected in parallel, used to realize the linear mapping from digital input value to delay amount, and generate the delay signal DELAY. TTFS The control terminal of the digital control switch in the k-th delay branch is connected to the bit of the converted digital signal. <k-1> Connected, 1≤k≤n;< / k-1> The dynamic delay unit includes a first-stage delay unit and an extended cascade unit, used to realize the conversion of the n-bit binary digital signal into bits. <n-1:0>The 2 corresponding to the kth position in (k-1) CLK IN Precise delay of clock cycles; The first-stage delay unit has one input terminal and one clock terminal, both connected to the input clock signal CLK. IN The delay unit, the output signal CLK of the first-stage delay unit DELAY Input clock CLK IN Delay by one cycle; The extended cascaded unit consists of k-2 counter units and 1 delay unit cascaded sequentially, where k ≥ 2, and is used to construct 2 (k-2) -1 CLK IN The clock cycle delay chain and delay cycle doubling; in the extended cascaded unit: the input of the first counter unit is connected to the output CLK of the first-stage delay unit. DELAY The clock terminal of the delay unit is connected to the input clock CLK. IN The input terminals of other counter units and delay units are connected to the DATA generated by the previous stage counter unit. OUT Signal, thereby achieving 2 n-1 CLK IN Precise delay of the cycle; The delay unit includes a counter unit, a DFF, and a two-input AND gate; the input terminal of the delay unit is SIG. DELAY This is the input terminal of its internal counter unit; the DFF input terminal is connected to a high level, and the clock terminal is connected to the DATA output of the counter unit. OUT The signal, output terminal, and clock terminal CLK of the delay unit. IN Perform logic AND generation CLK DELAY The generated CLK DELAY Pulse width and CLK IN Maintain consistency; The counter unit consists of a T'FF and a two-input AND gate; the clock input of the T'FF serves as the input SIG of the counter unit. CONT The inverting output terminal QN of T'FF is connected to SIG CONT Perform logical AND to generate DATA OUT Signal; The TTFS pulse generation module is used to generate pulses from the delayed signal DELAY. TTFS The TTFS peaks are extracted and implemented using a dual DFF architecture.

2. The converter circuit for converting digital signals into TTFS encoded spikes as described in claim 1, characterized in that, The specific working mode of the k-th delay branch is as follows: When the converted digital signal BIT <n-1:0>China BIT <k-1>When = 1, the digital control switch in the corresponding k-th delay branch is turned on, and the dynamic delay unit of this stage is bypassed; when BIT <k-1> When = 0, the digital control switch in the corresponding k-th delay branch is turned off, and the dynamic delay unit in this delay branch is activated; through this binary weighted combination control, the total delay cycle number of the delay control module is expressed as:< / k-1> BIT <k-1>=b k b k Input BIT for the converted numbers <n-1:0>The k-th bit <k-1> The value can be either 0 or 1.< / k-1> 3. The converter circuit for converting digital signals into TTFS encoded spikes as described in claim 1, characterized in that: When k=1, the dynamic delay unit only contains the first-level delay unit and does not contain the extended cascade unit.

4. The converter circuit for converting digital signals into TTFS encoded spikes as described in claim 1, characterized in that, The specific structure of the TTFS pulse generation module is as follows: the clock input of the first DFF is connected to the delay signal DELAY output by the delay control module. TTFS The clock input of the second DFF is connected to DELAY. TTFS The inverted signal is given, and the inputs of both DFFs are connected to a high level; the outputs of the two DFFs are ANDed through an AND gate to extract the AND signal with CLK. IN TTFS spikes with equal pulse widths.

5. The converter circuit for converting digital signals into TTFS encoded spikes as described in claim 1, characterized in that: The neuromorphic computing of the neuromorphic computing system is applied in a fully integrated design manner.

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