Advanced syntax control of loop filters

Abstract

A method and apparatus for video encoding, comprising: receiving a video sequence; encoding the video sequence at a sequence level, an image level, or a stripe level by using control flags for luminance mapping with chroma scaling (LMCS), wherein the sequence level, the image level, and the stripe level are levels ordered from high to low; signaling a first control flag indicating whether to enable the LMCS at a first level; and signaling a second control flag indicating whether to enable the LMCS at a second level in response to the first control flag indicating that the LMCS is enabled at the first level, wherein: when the value of the second control flag is equal to 1, the LMCS is enabled at the second level; when the value of the second control flag is equal to 0, the LMCS is disabled at the second level; and the second level is a level lower than the first level.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 001,448, filed March 29, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to video data processing, and more specifically, to high-level syntax control of loop filters. Background Technology

[0004] Video is a set of still images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and then decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, the most common being prediction, transform, quantization, entropy coding, and in-loop filtering. Standardization organizations have developed video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Universal Video Coding (VVC / H.266) standard, and the AVS standard, specifying particular video coding formats. As more and more advanced video coding techniques are adopted in video standards, the coding efficiency of new video coding standards is becoming increasingly higher. Summary of the Invention

[0005] This disclosure provides a video encoding method, comprising: receiving a video sequence; encoding the video sequence at a sequence level, an image level, or a stripe level by using a control flag for luminance mapping with chroma scaling (LMCS), wherein the sequence level, the image level, and the stripe level are levels ordered from high to low; signaling a first control flag indicating whether to enable the LMCS at a first level; and signaling a second control flag in response to the first control flag indicating that the LMCS is enabled at the first level, wherein: when the value of the second control flag is equal to 1, the LMCS is enabled at the second level; when the value of the second control flag is equal to 0, the LMCS is disabled at the second level; and the second level is a level lower than the first level.

[0006] This disclosure provides a video encoding method, comprising: receiving a video sequence; encoding the video sequence at a sequence level, an image level, or a stripe level by using control flags for an adaptive loop filter (ALF), wherein the sequence level, the image level, and the stripe level are levels ordered from high to low. A first control flag is signaled indicating whether the ALF is enabled at a first level; and in response to the first control flag indicating that the ALF is enabled at the first level, a second control flag is signaled indicating whether the ALF is enabled at a second level, wherein: when the value of the second control flag is equal to 1, the ALF is enabled at the second level; when the value of the second control flag is equal to 0, the ALF is disabled at the second level; and the second level is a level lower than the first level.

[0007] This disclosure provides a video encoding method, comprising: receiving a video sequence; encoding the video sequence at a sequence level, an image level, or a stripe level by using a control flag for Sample Adaptive Offset (SAO), wherein the sequence level, the image level, and the stripe level are ordered from high to low; signaling a first control flag, the first control flag indicating whether to enable the SAO at a first level; and signaling a second control flag, the second control flag indicating whether to enable the SAO at a second level, in response to the first control flag indicating that the SAO is enabled at the first level, wherein: when the value of the second control flag is equal to 1, the SAO for the luma component is enabled at the second level; when the value of the second control flag is equal to 0, the SAO for the luma component is disabled at the second level; and the second level is a level lower than the first level. Attached Figure Description

[0008] Embodiments and aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.

[0009] Figure 1 A schematic diagram of the structure of an exemplary video sequence according to some embodiments of the present disclosure is shown.

[0010] Figure 2A A schematic diagram illustrating an exemplary encoding process of a hybrid video encoding system according to some embodiments of the present disclosure is shown.

[0011] Figure 2B A schematic diagram of another exemplary encoding process of a hybrid video encoding system according to some embodiments of the present disclosure is shown.

[0012] Figure 3AA schematic diagram illustrating an exemplary decoding process of a hybrid video coding system according to some embodiments of the present disclosure is shown.

[0013] Figure 3B A schematic diagram of another exemplary decoding process of a hybrid video coding system according to some embodiments of the present disclosure is shown.

[0014] Figure 4 A block diagram of an exemplary apparatus for encoding or decoding video according to some embodiments of the present disclosure is shown.

[0015] Figure 5 Example pseudocode is shown, which includes a control variable that enables luminance mapping with chroma scaling at the sequence level.

[0016] Figure 6 Example pseudocode is shown, which includes a control variable used to enable luminance mapping with chroma scaling in the image header.

[0017] Figure 7 Example pseudocode is shown, which includes a control variable used to enable luminance mapping with chroma scaling in the strip header.

[0018] Figure 8A Example pseudocode is shown that includes adaptive loop filter syntax in the sequence parameter set.

[0019] Figure 8B Example pseudocode is shown that includes adaptive loop filter syntax in the image parameter set.

[0020] Figure 9 Example pseudocode for including adaptive loop filter syntax in the image header is shown.

[0021] Figure 10 Example pseudocode is shown that includes adaptive loop filter syntax in the strip header.

[0022] Figure 11 Example pseudocode is shown that includes sample adaptive offset syntax in the sequence parameter set.

[0023] Figure 12 Example pseudocode is shown that includes sample adaptive offset syntax in the image parameter set.

[0024] Figure 13 Example pseudocode for including sample adaptive offset syntax in the image header is shown.

[0025] Figure 14 Example pseudocode is shown that includes sample adaptive offset syntax in the strip header.

[0026] Figure 15Example pseudocode is shown that includes deblocking filter syntax in the image parameter set.

[0027] Figure 16 Example pseudocode for including deblocking filter syntax in the image header is shown.

[0028] Figure 17 Example pseudocode is shown that includes the deblocking filter syntax in the strip header.

[0029] Figure 18 Example semantics of a luminance mapping with chroma scaling, adaptive loop filtering, and sample adaptive offset are shown according to some embodiments of this disclosure.

[0030] Figure 19 Example pseudocode including a new set of image parameters for an adaptive loop filter, according to some embodiments of this disclosure, is shown.

[0031] Figure 20 Example pseudocode including a new image header syntax for adaptive loop filters is shown according to some embodiments of this disclosure.

[0032] Figure 21 Example pseudocode including a novel stripe header syntax for adaptive loop filters is shown according to some embodiments of this disclosure.

[0033] Figure 22A -C illustrates example semantics according to some embodiments of this disclosure, including new flags for image header syntax, stripe header syntax, and image parameter sets for adaptive loop filters.

[0034] Figure 23 Example pseudocode including a new set of image parameters for sample adaptive offset is shown according to some embodiments of this disclosure.

[0035] Figure 24 Example pseudocode including a novel image header syntax for sample adaptive offset is shown according to some embodiments of this disclosure.

[0036] Figure 25 Example pseudocode including a novel stripe header syntax for sample adaptive offset is shown according to some embodiments of this disclosure.

[0037] Figure 26 Example semantics according to some embodiments of this disclosure are shown, which include new flags for image parameter sets for image header syntax, strip header syntax, and sample adaptive offset.

[0038] Figure 27Example pseudocode is shown that includes a new sequence parameter set with a sequence parameter set disabling flag for a deblocking filter, according to some embodiments of this disclosure.

[0039] Figure 28 Example pseudocode is shown, according to some embodiments of this disclosure, including a new set of image parameters with a sequence parameter set disabling flag for a deblocking filter.

[0040] Figure 29 Example pseudocode is shown, according to some embodiments of this disclosure, including a new image header syntax with a set of disabling flags for the sequence parameter set used for deblocking filters.

[0041] Figure 30 Example pseudocode according to some embodiments of this disclosure is shown, which includes a new stripe header syntax with a sequence parameter set disable flag for deblocking filters.

[0042] Figure 31A and 31B Example semantics according to some embodiments of this disclosure are shown, including image header syntax, stripe header syntax, sequence parameter set, and new flags for image parameter set for deblocking filters.

[0043] Figure 32 This is a flowchart illustrating an exemplary process for determining a luminance map with chroma scaling (LMCS) for a video frame according to some embodiments of the present disclosure.

[0044] Figure 33 This is a flowchart describing an exemplary process for an adaptive loop filter (ALF) for video frames according to some embodiments of the present disclosure.

[0045] Figure 34 This is a flowchart depicting an exemplary process for determining a Sample Adaptive Offset (SAO) for a video frame according to some embodiments of the present disclosure.

[0046] Figure 35 This is a flowchart depicting an exemplary process for determining whether an adaptive loop filter (ALF) for a deblocking filter of a video frame is disabled, according to some embodiments of the present disclosure. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise stated, the same numerals in different drawings denote the same or similar elements. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of this disclosure as described in the appended claims. Specific aspects of this disclosure are described below in more detail. In the event of any conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0048] The Joint Video Experts Group (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) is currently developing the Universal Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, VVC aims to achieve the same subjective quality as HEVC / H.265 using half the bandwidth.

[0049] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET has been developing techniques other than HEVC using the Joint Exploratory Model (JEM) reference software. With the incorporation of coding techniques into JEM, JEM achieves higher coding performance than HEVC.

[0050] The VVC standard is a recent development and continues to include more coding techniques that provide better compression performance. VVC is based on a hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, and H.263.

[0051] Video is a set of still images (or “frames”) arranged in chronological order to store visual information. These images can be captured and stored in chronological order using video capture devices (e.g., cameras), and displayed in a time-series using video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display capability). Furthermore, in some applications, video capture devices can transmit captured video in real time to video playback devices (e.g., computers with monitors), such as for surveillance, conferencing, or live broadcasting.

[0052] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code embedded in a computer-readable medium, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, the H.26x series, etc. In some applications, a codec can decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard; in this case, the codec can be referred to as a "transcoder."

[0053] Video encoding processes identify and retain useful information that can be used to reconstruct the image, while ignoring unimportant reconstruction information. If ignoring unimportant information prevents complete reconstruction, such an encoding process can be called "lossy." Otherwise, it can be called "lossless." Most encoding processes are lossy, a trade-off to reduce required storage space and transmission bandwidth.

[0054] Useful information about an encoded image (referred to as the "current image") includes changes relative to a reference image (e.g., a previously encoded and reconstructed image). Such changes can include variations in pixel position, brightness, or color, with positional changes being the most important. The positional changes of a set of pixels representing an object can reflect the object's movement between the reference and current images.

[0055] An image encoded without referencing another image (i.e., it is its own reference image) is called an "I-image". An image encoded using a previous image as a reference image is called a "P-image", and an image encoded using both a previous image and a future image as reference images is called a "B-image" (the reference is "bidirectional").

[0056] This disclosure relates to methods and apparatus for processing video content consistent with the aforementioned video coding standards.

[0057] Figure 1The structure of an example video sequence 100 according to some embodiments of the present disclosure is shown. The video sequence 100 may be live video or video that has been captured and archived. The video 100 may be real-life video, computer-generated video (e.g., computer game video), or a combination of both (e.g., real video with augmented reality effects). The video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., a video file stored on a storage device), or a video feed interface (e.g., a video broadcast transceiver) receiving video from a video content provider.

[0058] like Figure 1 As shown, video sequence 100 may include a series of images arranged temporally along a timeline, including images 102, 104, 106, and 108. Images 102-106 are consecutive, with more images between images 106 and 108. Figure 1 In this diagram, image 102 is an I-image, and its reference image is image 102 itself. Image 104 is a P-image, and its reference image is image 102, as indicated by the arrow. Image 106 is a B-image, and its reference images are images 104 and 108, as indicated by the arrow. In some embodiments, the reference image of an image (e.g., image 104) may not immediately precede or follow the image. For example, the reference image of image 104 may be an image preceding image 102. It should be noted that the reference images of images 102-106 are merely examples, and this disclosure does not limit the scope to such cases. Figure 1 An example of the reference image shown.

[0059] Typically, due to the computational complexity of encoding and decoding tasks, video codecs do not encode or decode the entire image at once. Instead, they can segment the image into basic segments and encode or decode each segment sequentially. In this disclosure, such basic segments are referred to as basic processing units (“BPUs”). For example, Figure 1Structure 110 illustrates an example structure of an image (e.g., any of images 102-108) from video sequence 100. In structure 110, the image is divided into 4×4 basic processing units, whose boundaries are shown as dashed lines. In some embodiments, the basic processing unit may be referred to as a “macroblock” in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a “coding tree unit” (“CTU”) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing unit may have a variable size in the image, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing units for the image can be chosen based on a balance between coding efficiency and the level of detail to be maintained within the basic processing units. The CTU is the largest block unit and can contain up to 128×128 luma samples (plus corresponding chroma samples depending on the chroma format). The CTU can be further divided into coding units (CUs) using quadtrees, binary trees, ternary trees, or combinations thereof.

[0060] A basic processing unit can be a logical unit that may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, where the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on a basic processing unit may be performed repeatedly on each of its luminance and chrominance components.

[0061] Video encoding involves multiple operational stages, examples of which are as follows: Figure 2A-2B and Figures 3A-3BAs shown. For each stage, the size of the basic processing unit may still be too large for the processing, and therefore can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a "coding unit" ("CU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunit may have the same size as the basic processing unit or a smaller size. Similar to the basic processing unit, the basic processing subunit is also a logical unit that may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on the basic processing subunit may be repeated for each of its luminance and chrominance components. It should be noted that this division can be performed to further levels as needed for processing. It should also be noted that different schemes can be used to divide the basic processing units for different stages.

[0062] For example, in the pattern decision-making stage (examples of which are in...) Figure 2B As shown, the encoder can decide which prediction mode (e.g., intra-frame prediction or inter-frame prediction) to use for a basic processing unit, which may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing subunits (e.g., CUs in H.265 / HEVC or H.266 / VVC) and determine the prediction type for each individual basic processing subunit.

[0063] For another example, in the prediction phase (the example is in...) Figure 2A-2B As shown in the diagram, the encoder can perform prediction operations at the level of a basic processing subunit (e.g., a CU). However, in some cases, the basic processing subunit may still be too large to handle. The encoder can further divide the basic processing subunit into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC) at which prediction operations can be performed.

[0064] For another example, in the transformation phase (the example of which is in...) Figure 2A-2BAs shown in the diagram, the encoder can perform transformation operations on residual basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which level transformation operations can be performed. It is important to note that the partitioning scheme of the same basic processing subunit can differ between the prediction and transformation phases. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

[0065] exist Figure 1 In structure 110, the basic processing unit 112 is further divided into 3×3 basic processing sub-units, the boundaries of which are shown by dashed lines. Different basic processing units of the same image can be divided into basic processing sub-units in different schemes.

[0066] In some implementations, to provide parallel processing capabilities and fault tolerance for video encoding and decoding, an image can be divided into regions for processing, such that the encoding or decoding process for a given region of the image can be independent of information from any other region of the image. In other words, each region of the image can be processed independently. By doing so, the codec can process different regions of the image in parallel, thereby improving encoding efficiency. Furthermore, when data in one region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without depending on the corrupted or lost data, thus providing fault tolerance. In some video coding standards, images can be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: “slices” and “tiles.” It should also be noted that different images in the video sequence 100 may have different partitioning schemes for dividing the image into regions.

[0067] For example, in Figure 1 In the diagram, structure 110 is divided into three regions 114, 116, and 118, whose boundaries are shown as solid lines within structure 110. Region 114 comprises four basic processing units. Regions 116 and 118 each comprise six basic processing units. It should be noted that... Figure 1 The basic processing unit, basic processing subunit, and structural region of 110 are merely examples, and this disclosure does not limit its embodiments.

[0068] Figure 2A A schematic diagram of an exemplary encoding process 200A according to an embodiment of the present disclosure is shown. For example, the encoding process 200A may be performed by an encoder. Figure 2AAs shown, the encoder can encode the video sequence 202 into a video bitstream 228 according to process 200A. Similar to... Figure 1 Video sequence 100 and video sequence 202 may include a set of images arranged in chronological order (referred to as "raw images"). Similar to... Figure 1 In structure 110, each raw image of video sequence 202 can be divided into basic processing units, basic processing subunits, or regions by an encoder for processing. In some embodiments, the encoder can perform process 200A at the level of basic processing units for each raw image of video sequence 202. For example, the encoder can perform process 200A iteratively, wherein the encoder can encode basic processing units in one iteration of process 200A. In some embodiments, the encoder can perform process 200A in parallel for regions (e.g., regions 114-118) of each raw image of video sequence 202.

[0069] refer to Figure 2A The encoder feeds the basic processing unit (referred to as the "raw BPU") of the original image of video sequence 202 to prediction stage 204 to generate prediction data 206 and prediction BPU 208. The encoder can subtract the predicted BPU 208 from the raw BPU to generate residual BPU 210. The encoder can feed residual BPU 210 to transform stage 212 and quantization stage 214 to generate quantization transform coefficients 216. The encoder can feed prediction data 206 and quantization transform coefficients 216 to binary encoding stage 226 to generate video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 can be referred to as the "forward path". During process 200A, after quantization stage 214, the encoder can feed quantization transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPU 222. The encoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224, which is used in the prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A can be referred to as the "reconstruction path". The reconstruction path can be used to ensure that both the encoder and decoder use the same reference data for prediction.

[0070] The encoder can iteratively execute process 200A to encode each raw BPU (in the forward path) of the original image and generate a prediction reference 224 for encoding the next raw BPU (in the reconstruction path) of the original image. After encoding all raw BPUs of the original image, the encoder can continue to encode the next image in the video sequence 202.

[0071] Referring to process 200A, the encoder may receive a video sequence 202 generated by a video acquisition device (e.g., a camera). As used herein, the term "receive" can refer to any action that receives, inputs, acquires, retrieves, obtains, reads, accesses, or is used for inputting data in any manner.

[0072] In prediction phase 204, during the current iteration, the encoder can receive the original BPU and prediction reference 224, and perform prediction operations to generate prediction data 206 and prediction BPU 208. Prediction reference 224 can be generated from the reconstruction path of previous iterations of process 200A. The purpose of prediction phase 204 is to reduce information redundancy by extracting prediction data 206 from prediction data 206 and prediction reference 224 that can be used to reconstruct the original BPU into prediction BPU 208.

[0073] Ideally, the predicted BPU 208 should be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, the predicted BPU 208 is typically slightly different from the original BPU. To record these differences, the encoder can subtract the predicted BPU 208 from the original BPU to generate the residual BPU 210. For example, the encoder can subtract the value of the corresponding pixel in the predicted BPU 208 (e.g., grayscale or RGB value) from the pixel value of the original BPU. Each pixel in the residual BPU 210 can have a residual value as the result of this subtraction between the corresponding pixel in the original BPU and the predicted BPU 208. Compared to the original BPU, the predicted data 206 and the residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without a significant quality degradation. Thus, the original BPU is compressed.

[0074] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce its spatial redundancy by decomposing the residual BPU 210 into a set of two-dimensional “base patterns”. Each base pattern is associated with “transform coefficients”. The base patterns can have the same size (e.g., the size of the residual BPU 210), and each base pattern can represent the frequency (e.g., the frequency of brightness variation) component of the residual BPU 210. None of the base patterns can be reproduced from any combination (e.g., a linear combination) of any other base patterns. In other words, the decomposition can decompose the variation of the residual BPU 210 into the frequency domain. This decomposition is analogous to the discrete Fourier transform of a function, where the base patterns are analogous to the base functions of the discrete Fourier transform (e.g., trigonometric functions), and the transform coefficients are analogous to the coefficients associated with the base functions.

[0075] Different transform algorithms can use different base patterns. Various transform algorithms, such as discrete cosine transform, discrete sine transform, etc., can be used in transform stage 212. The transform at transform stage 212 is reversible. That is, the encoder can recover the residual BPU 210 through the inverse operation of the transform (called the "inverse transform"). For example, to recover the pixels of the residual BPU 210, the inverse transform can be to multiply the values ​​of the corresponding pixels of the base pattern by the corresponding correlation coefficients and sum the products to produce a weighted sum. For video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore have the same base pattern). Therefore, the encoder can only record the transform coefficients, from which the decoder can reconstruct the residual BPU 210 without receiving the base pattern from the encoder. Compared to the residual BPU 210, the transform coefficients can have fewer bits, but they can be used to reconstruct the residual BPU 210 without significant quality degradation. Therefore, the residual BPU 210 is further compressed.

[0076] The encoder can further compress the transform coefficients during the quantization stage 214. During the transform process, different fundamental patterns can represent different frequencies of change (e.g., brightness change frequencies). Because the human eye is generally better at recognizing low-frequency changes, the encoder can ignore information about high-frequency changes without causing significant quality degradation in decoding. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called the “quantization parameter”) and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of the high-frequency fundamental patterns can be converted to zero, and the transform coefficients of the low-frequency fundamental patterns can be converted to smaller integers. The encoder can ignore the zero-valued quantized transform coefficients 216, thus further compressing the transform coefficients. This quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (called “inverse quantization”).

[0077] Because the encoder ignores the remainder of the division during rounding, quantization stage 214 can be lossy. Typically, quantization stage 214 contributes the most to information loss in process 200A. The greater the information loss, the fewer bits are required for the quantization transform coefficients 216. To obtain different levels of information loss, the encoder can use different quantization parameter values ​​or any other parameter of the quantization process.

[0078] In the binary encoding stage 226, the encoder can encode the prediction data 206 and the quantization transform coefficients 216 using binary encoding techniques, such as entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantization transform coefficients 216, the encoder can encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the transform type at the transform stage 212, the parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. The encoder can use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 can be further packaged for network transmission.

[0079] Following the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder can perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In the inverse transform stage 220, the encoder can generate a reconstruction residual BPU 222 based on the reconstructed transform coefficients. The encoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224 that will be used in the next iteration of process 200A.

[0080] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, the stages of process 200A may be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be divided into multiple stages. For example, transform stage 212 and quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may be omitted. Figure 2A One or more stages in the process.

[0081] Figure 2B A schematic diagram of another example encoding process 200B according to an embodiment of the present disclosure is shown. Process 200B can be modified from process 200A. For example, process 200B can be used by an encoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 200A, the forward path of process 200B further includes a mode decision stage 230, and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B also additionally includes a loop filtering stage 232 and a buffer 234.

[0082] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-frame image prediction or "intra-prediction") uses pixels from one or more already encoded neighboring BPUs in the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of images. Temporal prediction (e.g., inter-image prediction or "inter-frame prediction") uses regions from one or more already encoded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include encoded images. Temporal prediction can reduce the inherent temporal redundancy of images.

[0083] In reference process 200B, during the forward path, the encoder performs prediction operations in spatial prediction phase 2042 and temporal prediction phase 2044. For example, in spatial prediction phase 2042, the encoder may perform intra-frame prediction. For the original BPU of the encoded image, prediction reference 224 may include one or more adjacent BPUs that have been encoded (in the forward path) and reconstructed (in the reconstruction path) in the same image. The encoder can generate the predicted BPU 208 by interpolating adjacent BPUs. Interpolation techniques may include, for example, linear interpolation or interpolation, polynomial interpolation or interpolation, etc. In some embodiments, the encoder may perform interpolation at the pixel level, for example, by interpolating to predict the value of the corresponding pixel for each pixel of BPU 208. The adjacent BPUs used for interpolation may be located in various directions relative to the original BPU, such as in the vertical direction (e.g., at the top of the original BPU), the horizontal direction (e.g., to the left of the original BPU), the diagonal direction (e.g., at the lower left, lower right, upper left, or upper right of the original BPU), or any direction defined in the video coding standard used. For intra-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the neighboring BPUs used, the size of the neighboring BPUs used, the interpolation parameters, the orientation of the neighboring BPUs used relative to the original BPU, etc.

[0084] In another example, during the temporal prediction phase 2044, the encoder can perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 can include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference images can be encoded and reconstructed on a BPU-by-BPU basis. For example, the encoder can add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs for the same image have been generated, the encoder can generate a reconstructed image as the reference image. The encoder can perform a "motion estimation" operation to search for matching regions within the range of the reference image (referred to as a "search window"). The position of the search window in the reference image can be determined based on the position of the original BPU in the current image. For example, the search window can be centered at a location in the reference image that has the same coordinates as the original BPU in the current image and can extend outward by a predetermined distance. When the encoder identifies a region in the search window that resembles the original BPU (e.g., by using a PEL recursive algorithm, a block matching algorithm, etc.), the encoder can determine such a region as a matching region. The matching region can have a different size than the original BPU (e.g., less than, equal to, greater than, or with a different shape). This is because the reference image and the current image are temporally separated on the timeline (e.g., as...). Figure 1 As shown in the image, the matching region can be considered to have "moved" to the original BPU's location over time. The encoder can record the direction and distance of this movement as a "motion vector." When using multiple reference images (e.g., such as...), Figure 1 In image 106, the encoder can search for matching regions and determine the associated motion vector for each reference image. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching regions of each matching reference image.

[0085] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0086] To generate the predicted BPU 208, the encoder can perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU 208 based on the predicted data 206 (e.g., motion vectors) and the predicted reference 224. For example, the encoder can move a matching region of the reference image according to the motion vectors, where the encoder can predict the original BPU of the current image. When using multiple reference images (e.g., such as...), Figure 1In image 106), the encoder can move the matching region of the reference image based on the individual motion vectors and average pixel values ​​of the matching region. In some embodiments, if the encoder has already assigned weights to the pixel values ​​of the matching regions of the respective matching reference images, the encoder can add the weighted sums of the pixel values ​​of the moved matching regions.

[0087] In some embodiments, inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same temporal direction relative to the current image. For example, Figure 1 Image 104 in the diagram is a one-way inter-frame prediction image, where the reference image (i.e., image 102) precedes image 104. Two-way inter-frame prediction can use one or more reference images in two temporal directions relative to the current image. For example, Figure 1 Image 106 in the image is a bidirectional inter-frame prediction image, in which the reference image (i.e., images 104 and 08) is relative to image 104 in two temporal directions.

[0088] Referring again to the forward path of process 200B, after spatial prediction 2042 and temporal prediction stages 2044, in the mode decision stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform a rate distortion optimization technique, whereby the encoder selects a prediction mode based on the bit rate of the candidate prediction modes and the distortion of the reconstructed reference image under the candidate prediction modes to minimize the value of the cost function. Based on the selected prediction mode, the encoder can generate the corresponding prediction BPU 208 and prediction data 206.

[0089] In the reconstruction path of process 200B, if intra-frame prediction mode has been selected in the forward path, the encoder can directly feed prediction reference 224 (e.g., the current BPU that has been encoded and reconstructed in the current image) to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224. If inter-frame prediction mode has been selected in the forward path, the encoder can feed prediction reference 224 (e.g., the current image where all BPUs have been encoded and reconstructed) to loop filter stage 232 after generating prediction reference 224. In this stage, the encoder can apply loop filters to prediction reference 224 to reduce or eliminate distortions introduced by inter-frame prediction (e.g., block artifacts). The encoder can apply various loop filter techniques at loop filter stage 232, such as deblocking, sample adaptive compensation, adaptive loop filtering, etc. The loop-filtered reference image can be stored in buffer 234 (or "decoded image buffer") for later use (e.g., as an inter-frame prediction reference image for future images of video sequence 202). The encoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the encoder can encode parameters of the loop filter (e.g., loop filter strength) as well as quantization transform coefficients 216, prediction data 206, and other information at binary encoding stage 226.

[0090] Figure 3A A schematic diagram of an exemplary decoding process 300A according to an embodiment of the present disclosure is shown. Process 300A may be corresponding to Figure 2A The compression process 200A in the video stream is followed by the decompression process. In some embodiments, process 300A can be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into video stream 304 according to process 300A. Video stream 304 can be very similar to video sequence 202. However, due to information loss during compression and decompression (e.g., Figure 2A-2B In the quantization stage 214), typically, video stream 304 differs from video sequence 202. Similar to... Figure 2A-2B In processes 200A and 200B, the decoder can perform process 300A at the basic processing unit (BPU) level for each image encoded in the video bitstream 228. For example, the decoder can perform process 300A iteratively, where the decoder can decode the basic processing unit in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel for a region (e.g., region 114-118) of each image encoded in the video bitstream 228.

[0091] like Figure 3AAs shown, the decoder can feed a portion of the video bitstream 228 associated with a basic processing unit (referred to as the "encoded BPU") of the encoded image to a binary decoding stage 302, where the decoder can decode this portion into prediction data 206 and quantization transform coefficients 216. The decoder can feed the quantization transform coefficients 216 to an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstruction residual BPU 222. The decoder can feed the prediction data 206 to a prediction stage 204 to generate a prediction BPU 208. The decoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 can be stored in a buffer (e.g., a decoded image buffer in computer memory). The decoder can feed the prediction reference 224 to the prediction stage 204 for performing a prediction operation in the next iteration of process 300A.

[0092] The decoder can iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for the next encoded BPU of the encoded image. After decoding all encoded BPUs of the encoded image, the decoder can output the image to video stream 304 for display and continue decoding the next encoded image in video bit stream 228.

[0093] In the binary decoding stage 302, the decoder can perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder can decode other information in the binary decoding stage 302, such as the prediction mode, parameters of the prediction operation, transform type, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted over a network in packets, the decoder can unpack it before feeding the video bitstream 228 to the binary decoding stage 302.

[0094] Figure 3B A schematic diagram of another example decoding process 300B according to an embodiment of the present disclosure is shown. Process 300B can be modified from process 300A. For example, process 300B can be used by a decoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 300A, process 300B additionally divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and additionally includes a loop filtering stage 232 and a buffer 234.

[0095] In process 300B, for the encoding basic processing unit (referred to as the "current BPU") of the decoded encoded image (referred to as the "current image"), the prediction data 206 decoded by the decoder from the binary decoding stage 302 can include various types of data depending on the prediction mode used by the encoder to encode the current BPU. For example, if the encoder uses intra-frame prediction to encode the current BPU, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate intra-frame prediction, parameters of the intra-frame prediction operation, etc. Parameters of the intra-frame prediction operation can include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, the sizes of neighboring BPUs, interpolation parameters, the orientation of neighboring BPUs relative to the original BPU, etc. For another example, if the current BPU is encoded by inter-frame prediction used by the encoder, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate inter-frame prediction, parameters of the inter-frame prediction operation, etc. The parameters of the inter-frame prediction operation may include, for example, the number of reference images associated with the current BPU, the weights associated with the reference images respectively, the positions (e.g., coordinates) of one or more matching regions in the corresponding reference images, and one or more motion vectors associated with the matching regions respectively.

[0096] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra-frame prediction) in the spatial prediction phase 2042 or temporal prediction (e.g., inter-frame prediction) in the temporal prediction phase 2044. The details of performing this spatial or temporal prediction are... Figure 2B As described herein, it will not be repeated below. After performing such spatial or temporal prediction, the decoder can generate a predicted BPU 208, which can be added to the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224, as shown below. Figure 3A As described in [the text].

[0097] In process 300B, the decoder can feed prediction reference 224 to either spatial prediction stage 2042 or temporal prediction stage 2044 for performing prediction operations in the next iteration of process 300B. For example, if intra-frame prediction is used to decode the current BPU in spatial prediction stage 2042, the decoder can feed prediction reference 224 directly to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224 (e.g., the decoded current BPU). If inter-frame prediction is used to decode the current BPU in temporal prediction stage 2044, the encoder can feed prediction reference 224 to loop filter stage 232 to reduce or eliminate distortion (e.g., block artifacts) after generating prediction reference 224 (e.g., a reference image where all BPUs are decoded). The decoder can, as follows: Figure 2BThe loop filter is applied to prediction reference 224 in the manner shown. The loop-filtered reference image can be stored in buffer 234 (e.g., a decoded image buffer in computer memory) for later use (e.g., as an inter-prediction reference image for future encoded images of video bitstream 228). The decoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the prediction data may further include parameters of the loop filter (e.g., loop filter strength). In some embodiments, the prediction data includes parameters of the loop filter when the prediction mode indicator of prediction data 206 indicates that inter-frame prediction is used to encode the current BPU.

[0098] Figure 4 This is a block diagram of an example apparatus 400 for encoding or decoding video according to embodiments of the present disclosure. Figure 4 As shown, device 400 may include processor 402. When processor 402 executes the instructions described herein, device 400 may become a dedicated machine for video encoding or decoding. Processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any number of central processing units (or “CPU”), graphics processing units (or “GPU”), neural processing units (“NPU”), microcontroller units (“MCU”), optical processors, programmable logic controllers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination thereof. In some embodiments, processor 402 may also be a group of processors grouped into individual logic components. For example, such as Figure 4 As shown, processor 402 may include multiple processors, including processor 402a, processor 402b and processor 402n.

[0099] The device 400 may also include a memory 404 configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, such as Figure 4As shown, the stored data may include program instructions (e.g., for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and data for processing (e.g., via bus 410) and execute the program instructions to perform operations or manipulations on the data for processing. Memory 404 may include a high-speed random access memory device or a non-volatile memory device. In some embodiments, memory 404 may include any combination of any number of random access memories (RAM), read-only memories (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash memory (CF cards), etc. Memory 404 may also be a group of memories grouped into single logical components. Figure 4 (Not shown in the image).

[0100] Bus 410 may be a communication device for transmitting data between components within device 400, such as an internal bus (e.g., CPU-memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Fast Port), or the like.

[0101] For ease of explanation and to avoid ambiguity, the processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. The data processing circuitry may be implemented entirely in hardware, or as a combination of software, hardware, or firmware. Furthermore, the data processing circuitry may be a single, separate module, or may be wholly or partially integrated into any other component of the device 400.

[0102] The device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, the network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, transceivers, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication (“NFC”) adapters, cellular network chips, etc.

[0103] In some embodiments, optionally, the device 400 may further include a peripheral interface 408 to provide connectivity to one or more peripheral devices. Figure 4 As shown, peripheral devices may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces coupled to video files), etc.

[0104] It should be noted that the video codec (e.g., the codec for executing processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instances that can be loaded into memory 404. As another example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0105] In VVC, a coding tool called Luminance Map with Chroma Scaling (“LMCS”) can be added as a new processing block before the loop filter. LMCS has two main components: 1) an intra-loop mapping of the luminance component based on an adaptive piecewise linear model; and 2) for the chrominance component, luminance-dependent chrominance residual scaling is applied. The intra-loop mapping of the luminance component adjusts the dynamic range of the input signal by reallocating codewords across the dynamic range to improve compression efficiency. Chroma residual scaling aims to compensate for the interaction between the luminance signal and its corresponding chrominance signal.

[0106] In VVC (e.g., VVC draft 8), LMCS can be controlled at the sequence level, image level, or stripe level. Figure 5 Example pseudocode is shown, including a control variable that enables luminance mapping with chroma scaling at the sequence level. (Example code follows) Figure 5 As shown, when sps_lmcs_enabled_flag equals 1, a luma mapping with chroma scaling is used in the coded layer video sequence (“CLVS”). When sps_lmcs_enabled_flag equals 0, a luma mapping with chroma scaling is not used in CLVS.

[0107] Figure 6 Example pseudocode is shown, which includes control variables for enabling luminance mapping with chroma scaling in the image header. (Example:) Figure 6 As shown, when ph_lmcs_enabled_flag equals 1, luma mapping with chroma scaling is enabled for all stripes associated with PH. When ph_lmcs_enabled_flag equals 0, luma mapping with chroma scaling can be disabled for one or more or all stripes associated with PH. When it does not exist, the value of ph_lmcs_enabled_flag is inferred to be equal to 0.

[0108] like Figure 6As shown, the chroma residual scaling process can be individually controlled using image-level flags (e.g., the `ph_chroma_residual_scale` flag). When `ph_chroma_residual_scale_flag` equals 1, chroma residual scaling is enabled for all stripes associated with PH. When `ph_chroma_residual_scale_flag` equals 0, chroma residual scaling for one or more or all stripes associated with PH can be disabled. If `ph_chroma_residual_scale_flag` does not exist, it is inferred to be equal to 0.

[0109] Figure 7 Example pseudocode is shown, including control variables for enabling luminance mapping with chroma scaling in the strip header. (See example pseudocode.) Figure 7 As shown, when slice_lmcs_enabled_flag equals 1, luma mapping with chroma scaling is enabled for the current slice. When slice_lmcs_enabled_flag equals 0, luma mapping with chroma scaling is not enabled for the current slice. If slice_lmcs_enabled_flag does not exist, it is inferred that it equals 0.

[0110] An adaptive loop filter (“ALF”) is an in-loop filter that can be applied to reconstruct samples to reduce sample distortion and thus improve coding efficiency. The filter coefficients are determined by the encoder and communicated via signals in the bitstream.

[0111] In VVC (e.g., VVC draft 8), ALF can be controlled at the sequence level and at one of the image or strip levels. ALF may not be applied at both the image and strip levels simultaneously. Figure 8A Example pseudocode is shown that includes adaptive loop filter syntax in the sequence parameter set. Figure 8B Example pseudocode is shown that includes adaptive loop filter syntax in the image parameter set. Figure 9 Example pseudocode for including adaptive loop filter syntax in the image header is shown. Figure 10 Example pseudocode is shown that includes adaptive loop filter syntax in the stripe header. Figure 8A As shown, the variable `sps_alf_enabled_flag` in the sequence parameter set (“SPS”) controls the ALF (Alf-Free Filter) of CLVS. When `sps_alf_enabled_flag` equals 1, ALF is enabled for CLVS. When `sps_alf_enabled_flag` equals 0, ALF is disabled for CLVS. Figure 8B , Figure 9 and Figure 10As shown, when ALF is enabled for CLVS, it can be further controlled at the image level via `ph_alf_enabled_flag` or at the slice level via `slice_alf_enabled_flag`. Whether this control is at the image or slice level is determined by the flag `alf_info_in_ph_flag`, which is signaled in the image parameter set (“PPS”). When `ph_alf_enabled_flag` equals 1, ALF coefficient information is signaled in the image header. When `slice_alf_enabled_flag` equals 1, ALF coefficient information is signaled in the slice header.

[0112] When sps_alf_enabled_flag equals 0, the adaptive loop filter is turned off (e.g., disabled). When sps_alf_enabled_flag equals 1, the adaptive loop filter is enabled.

[0113] When sps_ccalf_enabled_flag equals 0, the cross-component adaptive loop filter is disabled. When sps_ccalf_enabled_flag equals 1, the cross-component adaptive loop filter is enabled.

[0114] When alf_info_in_ph_flag equals 1, the ALF information exists in the PH syntax structure, but not in the strip header of the reference PPS, which does not contain a PH syntax structure. When alf_info_in_ph_flag equals 0, the ALF information does not exist in the PH syntax structure, but may exist in the strip header of the reference PPS that does not contain a PH syntax structure.

[0115] When ph_alf_enabled_flag equals 1, the adaptive loop filter is enabled for all stripes associated with PH, and the adaptive loop filter can be applied to the Y, Cb, or Cr color components in the stripe. When ph_alf_enabled_flag equals 0, the adaptive loop filter can be disabled for one or more or all stripes associated with PH. When it does not exist, ph_alf_enabled_flag is inferred to be equal to 0.

[0116] The variable ph_num_alf_aps_ids_luma specifies the number of ALF APS referenced by the stripe associated with PH.

[0117] The variable ph_alf_aps_id_luma[i] specifies the adaptation_parameter_set_id of the i-th ALF APS referenced by the luminance component of the strip associated with PH.

[0118] The variable alf_lum_filter_signal_flag of an APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_alf_aps_id_luma[i] should be equal to 1.

[0119] The TemporalId of an APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_alf_aps_id_luma[i] should be less than or equal to the TemporalId of the image associated with PH.

[0120] When ph_alf_chroma_idc equals 0, the adaptive loop filter is not applied to the Cb and Cr color components. When ph_alf_chroma_idc equals 1, the adaptive loop filter is applied to the Cb color component. When ph_alf_chroma_idc equals 2, the adaptive loop filter is applied to the Cr color component. When ph_alf_chroma_idc equals 3, the adaptive loop filter is applied to both the Cb and Cr color components. When ph_alf_chroma_idc does not exist, it is inferred to be equal to 0.

[0121] The variable ph_alf_aps_id_chroma specifies the adaptation_parameter_set_id of the ALF APS referenced by the chromaticity component of the band associated with PH.

[0122] The alf_chroma_filter_signal_flag value of an APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_alf_aps_id_chroma should be equal to 1.

[0123] The TemporalId of an APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_alf_aps_id_chroma should be less than or equal to the TemporalId of the image associated with PH.

[0124] When ph_cc_alf_cb_enabled_flag equals 1, the cross-component filter for the Cb color components is enabled for all stripes associated with PH, and the cross-component filter can be applied to the Cb color components in the stripes. When ph_cc_alf_cb_enabled_flag equals 0, the cross-component filter for the Cb color components can be disabled for one or more or all stripes associated with PH. When it does not exist, ph_cc_alf_cb_enabled_flag is inferred to be equal to 0.

[0125] The variable ph_cc_alf_cb_aps_id specifies the adaptation_parameter_set_id of the ALFAPS referenced by the Cb color component of the strip associated with PH.

[0126] The value of alf_cc_cb_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_cc_alf_cb_aps_id.

[0127] When ph_cc_alf_cr_enabled_flag equals 1, the cross-component filter for the Cr color component is enabled for all stripes associated with PH, and this cross-component filter can be applied to the Cr color component in the stripe. When ph_cc_alf_cr_enabled_flag equals 0, the cross-component filter for the Cr color component can be disabled for one or more or all stripes associated with PH. When it does not exist, ph_cc_alf_cr_enabled_flag is inferred to be equal to 0.

[0128] The variable ph_cc_alf_cr_aps_id specifies the adaptation_parameter_set_id of the ALFAPS referenced by the Cr color component of the band associated with PH.

[0129] The value of alf_cc_cr_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to ph_cc_alf_cr_aps_id.

[0130] When slice_alf_enabled_flag equals 1, the adaptive loop filter is enabled and can be applied to the Y, Cb, or Cr color components in the slice. When slice_alf_enabled_flag equals 0, the adaptive loop filter is disabled for all color components in the slice. If it does not exist, the value of slice_alf_enabled_flag is inferred to be equal to ph_alf_enabled_flag.

[0131] The variable slice_num_alf_aps_ids_luma specifies the number of ALF APS referenced by the slice. When slice_alf_enabled_flag equals 1 and slice_num_alf_aps_ids_luma does not exist, it is inferred that the value of slice_num_alf_aps_ids_luma is equal to the value of ph_num_alf_aps_ids_luma.

[0132] The variable slice_alf_aps_id_luma[i] specifies the adaptation_parameter_set_id of the i-th ALF APS referenced by the luminance component of the slice. The TemporalId of the APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_alf_aps_id_luma[i] should be less than or equal to the TemporalId of the encoded slice NAL cell. When slice_alf_enabled_flag equals 1 and slice_alf_aps_id_luma[i] does not exist, it is inferred that the value of slice_alf_aps_id_luma[i] is equal to the value of ph_alf_aps_id_luma[i].

[0133] The value of alf_luma_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_alf_aps_id_luma[i].

[0134] When slice_alf_chroma_idc equals 0, the adaptive loop filter is not applied to the Cb and Cr color components. When slice_alf_chroma_idc equals 1, the adaptive loop filter is applied to the Cb color component. When slice_alf_chroma_idc equals 2, the adaptive loop filter is applied to the Cr color component. When slice_alf_chroma_idc equals 3, the adaptive loop filter is applied to both the Cb and Cr color components. When slice_alf_chroma_idc does not exist, it is inferred to be equal to ph_alf_chroma_idc.

[0135] The variable `slice_alf_aps_id_chroma` specifies the `adaptation_parameter_set_id` of the ALF APS referenced by the chroma components of the slice. The `TemporalId` of the APS NAL unit with `aps_params_type` equal to `ALF_APS` and `adaptation_parameter_set_id` equal to `slice_alf_aps_id_chroma` should be less than or equal to the `TemporalId` of the encoded slice NAL unit. When `slice_alf_enabled_flag` equals 1 and `slice_alf_aps_id_chroma` does not exist, it is inferred that the value of `slice_alf_aps_id_chroma` is equal to the value of `ph_alf_aps_id_chroma`.

[0136] The value of alf_chroma_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_alf_aps_id_chroma.

[0137] When slice_cc_alf_cb_enabled_flag equals 0, the cross component filter is not applied to the Cb color component. When slice_cc_alf_cb_enabled_flag equals 1, the cross component filter is enabled and can be applied to the Cb color component. When slice_cc_alf_cb_enabled_flag does not exist, it is inferred to be equal to ph_cc_alf_cb_enabled_flag.

[0138] The variable slice_cc_alf_cb_aps_id specifies the adaptation_parameter_set_id referenced by the Cb color component of the slice.

[0139] The TemporalId of an APS NAL cell with aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_cc_alf_cb_aps_id should be less than or equal to the TemporalId of the encoded slice NAL cell. When slice_cc_alf_cb_enabled_flag equals 1 and slice_cc_alf_cb_aps_id does not exist, it is inferred that the value of slice_cc_alf_cb_aps_id is equal to the value of ph_cc_alf_cb_aps_id.

[0140] The value of alf_cc_cb_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_cc_alf_cb_aps_id.

[0141] When slice_cc_alf_cr_enabled_flag equals 0, the cross-component filter is not applied to the Cr color component. When slice_cc_alf_cb_enabled_flag equals 1, the cross-component adaptive loop filter is enabled and can be applied to the Cr color component. When slice_cc_alf_cr_enabled_flag does not exist, it is inferred to be equal to ph_cc_alf_cr_enabled_flag.

[0142] The variable `slice_cc_alf_cr_aps_id` specifies the `adaptation_parameter_set_id` referenced by the Cr color component of the slice. The TemporalId of the APS NAL unit with `aps_params_type` equal to `ALF_APS` and `adaptation_parameter_set_id` equal to `slice_cc_alf_cr_aps_id` should be less than or equal to the TemporalId of the encoded slice NAL unit. When `slice_cc_alf_cr_enabled_flag` equals 1 and `slice_cc_alf_cr_aps_id` does not exist, it is inferred that the value of `slice_cc_alf_cr_aps_id` is equal to the value of `ph_cc_alf_cr_aps_id`.

[0143] The value of alf_cc_cr_filter_signal_flag should be equal to 1 for an APS NAL cell that has aps_params_type equal to ALF_APS and adaptation_parameter_set_id equal to slice_cc_alf_cr_aps_id.

[0144] Sample Adaptive Offset (“SAO”) adds an offset to the reconstructed samples to reduce sample distortion. Two offset modes are supported in SAO: Edge Offset (“EO”) mode and Band Offset (“BO”) mode. For Edge Offset mode, samples in the coding tree unit (“CTU”) are first divided into 5 categories, with samples in 4 categories having corresponding offsets. Therefore, the encoder determines the values ​​of the 4 offsets, one offset per category. The classification method and the offset values ​​are signaled in the bitstream at the CTU level. For Band Offset mode, samples in the CTU are divided into 32 bands based on sample values, with samples in 4 bands having corresponding offsets. The 4 bands to be offset and their corresponding offsets are signaled in the bitstream.

[0145] In VVC (e.g., VVC draft 8), similar to ALF, SAO can be controlled at the sequence level, and either the image level or the stripe level. SAO may not be controllable at either the image level or the stripe level. Figure 11 Example pseudocode is shown that includes sample adaptive offset syntax in the sequence parameter set. Figure 12 Example pseudocode is shown that includes sample adaptive offset syntax in the image parameter set. Figure 13 Example pseudocode for including sample adaptive offset syntax in the image header is shown. Figure 14 Example pseudocode including sample adaptive offset syntax in the stripe header is shown. Figure 11In the SPS, the variable `sps_sao_enabled_flag` controls the SAO of CLVS. When `sps_sao_enabled_flag` equals 1, SAO is enabled for CLVS. When `sps_sao_enabled_flag` equals 0, SAO of CLVS is disabled.

[0146] like Figure 12 , Figure 13 and Figure 14 As shown, when SAO is enabled for CLVS, it can be further controlled at the image level via ph_sao_luma_enabled_flag / ph_sao_chroma_enabled_flag, or at the slice level via slice_sao_luma_flag / slice_sap_chroma_flag. The flag sao_info_in_ph_flag, which is signaled in PPS, determines whether SAO is controlled at the image or slice level.

[0147] When sps_sao_enabled_flag equals 1, the sample adaptive offset process is applied to the reconstructed image after the deblocking filtering process. When sps_sao_enabled_flag equals 0, the sample adaptive offset process is not applied to the reconstructed image after the deblocking filtering process.

[0148] When `sao_info_in_ph_flag` equals 1, the SAO filter information exists in the PH syntax structure, but not in the strip header of the reference PPS, which does not contain a PH syntax structure. When `sao_info_in_ph_flag` equals 0, the SAO filter information does not exist in the PH syntax structure, but may exist in the strip header of the reference PPS, which also does not contain a PH syntax structure.

[0149] When ph_sao_luma_enabled_flag equals 1, SAO is enabled for the luma component in all stripes associated with PH. When ph_sao_luma_enabled_flag equals 0, SAO for the luma component can be disabled for one or more or all stripes associated with PH. If ph_sao_luma_enabled_flag does not exist, it is inferred to be equal to 0.

[0150] When ph_sao_chroma_enabled_flag equals 1, SAO is enabled for the chroma components in all PH-related stripes. When ph_sao_chroma_enabled_flag equals 0, SAO for the chroma components can be disabled for one or more or all PH-related stripes. If ph_sao_chroma_enabled_flag does not exist, it is inferred to be equal to 0.

[0151] When slice_sao_luma_flag equals 1, SAO is enabled for the luma component in the current slice. When slice_sao_luma_flag equals 0, SAO is disabled for the luma component in the current slice. If slice_sao_luma_flag does not exist, it is inferred that it is equal to ph_sao_luma_enabled_flag.

[0152] When slice_sao_chroma_flag equals 1, SAO is enabled for the chroma components in the current slice. When slice_sao_chroma_flag equals 0, SAO is disabled for the chroma components in the current slice. If slice_sao_chroma_flag does not exist, it is inferred that it is equal to ph_sao_chroma_enabled_flag.

[0153] A deblocking filter (“DBF”) is a filter applied to the boundaries of blocks to reduce block artifacts. In VVC (e.g., VVC draft 8), the DBF disable flag and parameters are signaled in the PPS. Additionally, the override enable flag `deblocking_filter_override_enabled_flag` is signaled to indicate whether the DBF disable flag and parameters can be overridden at a lower level. If so, the flag `dbf_info_in_ph_flag` is signaled to indicate whether the DBF disable flag and parameters are overridden in the image header or stripe header.

[0154] Figure 15 Example pseudocode is shown that includes deblocking filter syntax in the image parameter set. Figure 16 Example pseudocode for including deblocking filter syntax in the image header is shown. Figure 17 Example pseudocode is shown that includes deblocking filter syntax in the stripe header. Figure 15 , Figure 16 and Figure 17As shown, if the DBF disable flag and parameters are overridden in the image header, the image-level DBF disable flag and parameters can be signaled in the image header. If the DBF disable flag and parameters are overridden in the strip header, the strip-level DBF disable flag and parameters can be sent in the strip header.

[0155] When `debocking_filter_control_present_flag` equals 1, the deblocking filter control syntax element exists in PPS. When `debocking_filter_control_present_flag` equals 0, the deblocking filter control syntax element does not exist in PPS.

[0156] When `deblocking_filter_override_enabled_flag` equals 1, either `ph_debocking_filter_override_flag` exists in the PH of the reference PPS, or `slice_deblocking_filter_override_flag` exists in the slice header of the reference PPS. When `deblocking_filter_override_enabled_flag` equals 0, either `ph_debocking_filter_override_flag` does not exist in the PH of the reference PPS, or `slice_deblocking_filter_override_flag` does not exist in the slice header of the reference PPS. If it does not exist, it is inferred that the value of `deblocking_filter_override_enabled_flag` is equal to 0.

[0157] When pps_debocking_filter_disabled_flag equals 1, the deblocking filter operation is not applied to the slices of the reference PPS, which does not contain slice_deblocking_filter_disabled_flag. When pps_debocking_filter_disabled_flag equals 0, the deblocking filter operation is applied to the slices of the reference PPS, which does not contain slice_deblocking_filter_disabled_flag. When it does not exist, the value of pps_deblocking_filter_disabled_flag is inferred to be equal to 0.

[0158] When ph_debocking_filter_override_flag equals 1, the deblocking parameter exists in PH. When ph_debocking_filter_override_flag equals 0, the deblocking parameter does not exist in PH. When it does not exist, the value of ph_debocking_filter_override_flag is inferred to be 0.

[0159] When ph_debocking_filter_disabled_flag equals 1, the deblocking filter operation is not applied to slices associated with pH. When ph_debocking_filter_disabled_flag equals 0, the deblocking filter operation is applied to slices associated with pH. When ph_debocking_filter_disabled_flag does not exist, it is inferred to be equal to pps_debocking_filter_disabled_flag.

[0160] When slice_deblocking_filter_override_flag equals 1, the deblocking parameters are present in the slice header. When slice_deblocking_filter_override_flag equals 0, the deblocking parameters are not present in the slice header. If they are not present, it is inferred that the value of slice_deblocking_filter_override_flag is equal to ph_debocking_filter_override_flag.

[0161] When `slice_deblocking_filter_disabled_flag` equals 1, the deblocking filter operation is not applied to the current slice. When `slice_deblocking_filter_disabled_flag` equals 0, the deblocking filter operation is applied to the current slice. If `slice_deblocking_filter_disabled_flag` does not exist, it is inferred that it is equal to `ph_debocking_filter_disabled_flag`.

[0162] The current VVC design has several problems. First, LMCS can be controlled at the CLVS level, image level, and stripe level. When an enable flag at a higher level enables LMCS, a lower level can disable it. In other words, an enable flag equal to 1 at a given level does not necessarily mean that LMCS must be enabled, as a lower-level enable flag may disable it. Similarly, when the SPS enable flag enables ALF and SAO, image-level or stripe-level enable flags may disable them. As a result, the current semantics are inaccurate.

[0163] Furthermore, when ph_lmcs_enabled_flag equals 1, ph_chroma_residual_scale_flag can still turn off (e.g., disable) chroma scaling for the current image. Therefore, ph_lmcs_enabled_flag equal to 1 does not necessarily mean that chroma scaling must be enabled. Thus, the current semantics are not accurate.

[0164] Another issue is syntactic consistency. There are some inconsistencies between the ALF / SAO and LMCS syntax. LMCS can be controlled at three levels: SPS, PH, and SH. When enabled at a higher level, it can be disabled at a lower level. When it is disabled at a higher level, it may not be enabled at a lower level. However, for ALF and SAO, they can only be controlled at two levels: SPS and either PH or SH. The PH-level or SH-level control for ALF and SAO is determined by flags in PPS. As a result, the control mechanisms differ between LMCS and ALF / SAO.

[0165] Furthermore, when ALF is controlled and enabled in PH, its parameter information is signaled in PH. When ALF is controlled and enabled in SH, its parameter information is signaled in SH. Therefore, for ALF, different stripes may have different ALF parameters when control is at the stripe level. Conversely, for LMCS, SH can only enable or disable (e.g., disable), but cannot signal parameter information when enabled. In other words, for all stripes in the same image (LMCS enabled), the LMCS parameters must be identical. This is another inconsistency between ALF and LMCS.

[0166] The third issue is the deblocking filter syntax. There is no SBS disable flag to disable DBF for the entire CLVS. Furthermore, the semantics of `pps_debocking_filter_disabled_flag` and `ph_debocking_filter_disabled_flag` are incorrect. In VVC (e.g., VVC draft 8), `pps_debocking_filter_disabled_flag` equal to 1 (or 0) specifies that the deblocking filter is not applied (or applied) for slices of a reference PPS in which `slice_deblocking_filter_disabled_flag` does not exist. However, `ph_debocking_filter_disabled_flag` can override `pps_debocking_filter_disabled_flag`, thus making the semantics of `pps_debocking_filter_disabled_flag` inaccurate. Additionally, according to VVC (e.g., VVC draft 8), `ph_debocking_filter_disabled_flag` equal to 1 (or 0) specifies that the deblocking filter is not applied (or applied) for slices associated with a PH. When `ph_debocking_filter_disabled_flag` does not exist, it is inferred to be equal to `pps_debocking_filter_disabled_flag`. However, if `slice_deblocking_filter_disabled_flag` overrides `pps_debocking_filter_disabled_flag`, then since `ph_debocking_filter_disabled_flag` does not exist, it is inferred to be equal to `pps_debocking_filter_disabled_flag`. However, because `pps_debocking_filter_disabled_flag` is overridden by `slice_deblocking_filter_disabled_flag`, the value of `pps_debocking_filter_disabled_flag` may not be applicable to that slice. Therefore, the semantics of `ph_debocking_filter_disabled_flag` are incorrect.

[0167] Embodiments of this disclosure provide a method for solving the above-mentioned problems. In some embodiments, the semantics can be modified based on the following considerations: the low-level enable flags of LMCS, ALF, and SAO can be turned off (e.g., disabled) when the high-level enable flags are enabled, and chroma scaling can be turned off when the LMCS flag is enabled. Figure 18 Example semantics of a luminance map with chroma scaling, adaptive loop filtering, and sample adaptive offset are shown according to some embodiments of this disclosure. Figure 18 In the text, changes to previous VVCs are shown in bold, and suggested deletion syntax is further shown with strikethrough.

[0168] In some embodiments, the semantics can be modified such that when ALF or SAO is enabled at a higher level, it can be disabled at a lower level. When ALF or SAO is disabled at a higher level, it may not be enabled at a lower level. Furthermore, for ALF, when controlled in the SH (Slice-Specific Layout), it can only be enabled or disabled, and slice-specific ALF parameters may not be signaled in the SH. As a result, all stripes in the image can share the same ALF parameters.

[0169] Figure 19 Example pseudocode including a new set of image parameters for an adaptive loop filter, according to some embodiments of this disclosure, is shown. Figure 20 Example pseudocode including a new image header syntax for adaptive loop filters is shown according to some embodiments of this disclosure. Figure 21 Example pseudocode, including a novel stripe header syntax for adaptive loop filters, is shown according to some embodiments of this disclosure. Figure 19 , Figure 20 and Figure 21 As shown, changes to the previous VVC are displayed in bold, and suggested deletion syntax is further shown with strikethrough. For example... Figure 19 , Figure 20 and Figure 21 As shown, PPS-level signal notifications are simplified by removing alf_info_in_ph_flag and cleaning up the syntax of ALF parameter signal notifications in the stripe header.

[0170] Figure 22 illustrates example semantics according to some embodiments of the present disclosure, including new markers for the image header syntax, stripe header syntax, and image parameter set for adaptive loop filters. In Figure 22, changes to previous VVCs are shown in bold, and proposed deletion syntax is further shown with strikethrough. It should be understood that the semantics shown in Figure 22 can be applied to... Figure 19 , Figure 20 and Figure 21 The pseudocode in the code.

[0171] Figure 23 Example pseudocode including a new set of image parameters for sample adaptive offset is shown according to some embodiments of this disclosure. Figure 24 Example pseudocode including a new image header syntax for sample adaptive offset is shown according to some embodiments of this disclosure. Figure 25 Example pseudocode, including a novel stripe header syntax for sample adaptive offset, is shown according to some embodiments of this disclosure. For example... Figure 23 , Figure 24 and Figure 25 As shown, changes to the previous VVC are displayed in bold, and suggested deletion syntax is further shown with strikethrough. For example... Figure 23 , Figure 24 and Figure 25 As shown, PPS-level signal notifications are simplified by removing sao_info_in_ph_flag.

[0172] Figure 26 Example semantics according to some embodiments of this disclosure are illustrated, including new flags for image header syntax, stripe header syntax, and image parameter sets for sample adaptive offset. For example... Figure 26 As shown, changes to the previous VVC are displayed in bold, and suggested deletion syntax is further shown with strikethrough. It should be understood that... Figure 26 The semantics shown can be applied to Figure 23 , Figure 24 or Figure 25 The pseudocode in the code.

[0173] In some embodiments, an SPS disable flag can be added to DBF.

[0174] In some embodiments, since pps_debocking_filter_disabled_flag can be overridden by ph_debocking_filter_disabled_flag or slice_deblocking_filter_disabled_flag, pps_debocking_filter_disabled_flag is only applicable when the overriding mechanism is disabled (e.g., neither ph_debocking_filter_disabled_flag nor slice_deblocking_filter_disabled_flag exists), and ph_debocking_filter_disabled_flag is only applicable when ph_debocking_filter_disabled_flag overrides ph_deblocking_filter_disabled_flag (e.g., ph_deblocking_filter_disabled_flag exists, but slice_deblocking_filter_disabled_flag does not exist).

[0175] Figure 27 Example pseudocode is shown that includes a new sequence parameter set with a sequence parameter set disabling flag for a deblocking filter, according to some embodiments of this disclosure. Figure 28 Example pseudocode is shown, according to some embodiments of this disclosure, including a new set of image parameters with a sequence parameter set disabling flag for a deblocking filter. Figure 29 Example pseudocode is shown, according to some embodiments of this disclosure, including a new image header syntax with a set of disabling flags for the sequence parameter set used for deblocking filters. Figure 30 Example pseudocode is shown below, illustrating some implementations of this disclosure, featuring a novel stripe header syntax with a sequence parameter set disabling flag for deblocking filters, such as... Figure 27 , Figure 28 and Figure 29 As shown, changes to the previous VVC are shown in bold, and suggested deletion syntax is further shown with strikethrough.

[0176] Figure 31A / B illustrates example semantics according to some embodiments of this disclosure, including image header syntax, stripe header syntax, sequence parameter sets, and new flags for image parameter sets for deblocking filters. For example Figure 26 As shown, changes to the previous VVC are displayed in bold, and suggested deletion syntax is further shown with strikethrough. It should be understood that... Figure 31A The semantics shown in / B can be applied to Figure 27 , Figure 28, Figure 29 or Figure 30 Chinese pseudocode.

[0177] Figure 32 This is a flow describing an exemplary process for determining a luminance map with chroma scaling (LMCS) according to this disclosure. Process 3200 may be performed by a codec (e.g., Figure 2A-2B encoder or Figures 3A-3B The codec is executed by a decoder (e.g., a device). For example, the codec can be implemented as a device (e.g., a decoder). Figure 4 One or more software or hardware components of the device 400, such as the device's processor (e.g., processor 402), are used to determine the LMCS. The method may include the following steps.

[0178] In step 3202, device 400 receives one or more video frames. As used herein, video can refer to a time series of “frames” (e.g., still images or pictures) used to acquire visual information. These images can be acquired and stored in chronological order using video acquisition devices (e.g., cameras), and such images in the time series can be displayed using video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display capability). Furthermore, in some applications, the video acquisition device can transmit the acquired video to a video playback device (e.g., a computer with a monitor) in real time, for example, for monitoring, conferencing, or live broadcasting.

[0179] In step 3204, the apparatus 400 determines control flags for video frames at the sequence level. In some embodiments, a video frame may comprise a sequence of images, and each image may comprise one or more stripes. The control flags for the sequence may be an indication of the state of all images in the sequence. In some embodiments, the control flags may be an indication of whether the video frame is encoded using a luma mapping with chroma scaling (LMCS). An example of the control flags for the sequence may be a first control flag. Figure 18 In the example shown, sps_lmcs_enabled_flag can be a sequence-level LMCS control flag. In some embodiments, sps_lmcs_enabled_flag can have a value of "1" or "0".

[0180] In step 3206, device 400 checks the value of a control flag for sequence-level LMCS to determine whether LMCS is enabled at the sequence level. If LMCS is not enabled at the sequence level, step 3206 is "No," and process 3200 proceeds to step 3222. When LMCS is not enabled at the sequence level, LMCS is also not enabled for all images and all stripes of the video frames in the sequence. In some embodiments, step 3206 is "No" when sps_lmcs_enabled_flag has a value of "0." If LMCS is enabled at the sequence level, step 3206 is "Yes," and process 3200 proceeds to step 3208. When LMCS is enabled at the sequence level, all images in the sequence can be enabled. In some embodiments, step 3206 is "Yes" when sps_lmcs_enabled_flag has a value of "1."

[0181] In step 3208, the apparatus 400 determines image-level control flags for images in a sequence of video frames. In some embodiments, the images of video frames within a sequence may include one or more stripes. The image control flags may be an indication of the state of all stripes in the image. In some embodiments, the control flags may be an indication of whether the image of the video frame utilizes Luminosity Mapping with Chroma Scaling (LMCS) encoding. An example of an image control flag may be a second control flag. Figure 18 In the example shown, ph_lmcs_enabled_flag can be a control flag for LMCS at the image level. In some embodiments, the control flag at the image level exists in the image header. In some embodiments, ph_lmcs_enabled_flag can have a value of "1" or "0".

[0182] In step 3210, device 400 checks the value of the control flag for LMCS at the image level to determine whether LMCS is enabled at the image level. If LMCS is not enabled at the image level, step 3210 is "No," and process 3200 proceeds to step 3212. When LMCS is not enabled at the image level, LMCS is also not enabled for all stripes of that image in the video frame. In some embodiments, step 3210 is "No" when ph_lmcs_enabled_flag has a value of "0." If LMCS is enabled at the image level, step 3210 is "Yes," and process 3200 proceeds to step 3214. When LMCS is enabled at the image level, all stripes in the image can be enabled. In some embodiments, step 3210 is "Yes" when ph_lmcs_enabled_flag has a value of "1."

[0183] In some additional or alternative embodiments, in response to determining that LMCS is enabled at the image level (step 3210 - Yes), device 400 may check the value of a third control flag indicating whether chroma scaling (CS) is enabled at the image level of a video frame. Figure 18 As shown, ph_chroma_residual_scale_flag can be an example of a third control flag. In some embodiments, CS is enabled when ph_chroma_residual_scale_flag equals 1, and CS is disabled when ph_chroma_residual_scale_flag equals 0.

[0184] In step 3212, device 400 checks whether the image is the last image in the sequence. If step 3212 is "no", device 400 proceeds to step 3208 to determine the control flag at the image location for the next image in the sequence of video frames. Regardless of whether step 3212 is "yes" or "no", process 3200 proceeds to step 3222.

[0185] In step 3214, as determined in step 3208, the apparatus 400 determines control flags at the stripe level for stripes in the image for the video frame. The stripe control flags may be indications of the state of a particular stripe in the image. In some embodiments, the control flags may be indications of whether stripes in the image of the video frame are encoded using a luminance mapping with chroma scaling (LMCS). The stripe control flags may be examples of a fourth control flag. Figure 18 In the example shown, slice_lmcs_enabled_flag can be a control flag for the LMCS at the slice level. In some embodiments, slice_lmcs_enabled_flag can have a value of "1" or "0".

[0186] In step 3216, device 400 checks the value of the control flag for LMCS at the slice level to determine whether LMCS is enabled at the slice level. If LMCS is not enabled at the slice level, step 3216 is "No", and process 3200 proceeds to step 3218. In some embodiments, step 3216 is "No" when slice_lmcs_enabled_flag has a value of "0". If LMCS is enabled at the slice level, step 3216 is "Yes", and process 3200 proceeds to step 3220. In some embodiments, step 3216 is "Yes" when slice_lmcs_enabled_flag has a value of "1".

[0187] In step 3218, device 400 checks whether the strip is the last strip in the image. If step 3218 is "no", device 400 proceeds to step 3214 to determine the control flag at the strip for the next strip in the image for the video frame. Regardless of whether step 3218 is "yes" or "no", process 3200 proceeds to step 3222.

[0188] In step 3220, the device 400 encodes slices, images, and / or sequences of video frames with luma mapping (LM) enabled and chroma scaling enabled. In some embodiments, in response to a second flag indicating that LMCS is enabled at the image level, luma mapping (LM) is enabled and CS can be enabled at the slice level when slice_lmcs_enabled_flag equals 1.

[0189] In step 3222, the device 400 encodes stripes, images, and / or sequences of video frames when luminance mapping and chroma scaling are not enabled.

[0190] Figure 33 This is a flowchart consistent with the description of this disclosure, illustrating an exemplary process for determining the encoding of a video frame using an adaptive loop filter (ALF). Process 3300 may be performed by device 400 and its sub-components, such as processor 3102.

[0191] In step 3302, device 400 receives one or more video frames.

[0192] In step 3304, the apparatus 400 determines control flags for video frames at the sequence level. In some embodiments, the control flags may be an indication of whether an adaptive loop filter (ALF) is used to encode the video frame. An example of the sequence control flags may be a first control flag. Figure 18 In the example shown, sps_alf_enabled_flag can be a control flag for ALF at the sequence level. In some embodiments, sps_alf_enabled_flag can have a value of "1" or "0". In some embodiments, if no value is specified or is missing for sps_alf_enabled_flag, its default value can be "0".

[0193] In step 3306, the device 400 checks the value of the sequence-level ALF control flag to determine whether ALF is enabled at the sequence level. If ALF is not enabled at the sequence level, step 3306 is "No," and process 3300 proceeds to step 3322. When ALF is not enabled at the sequence level, ALF is also not enabled for all images and all stripes of the video frame. In some embodiments, step 3306 is "No" when sps_alf_enabled_flag has a value of "0." If ALF is enabled at the sequence level, step 3306 is "Yes," and process 3300 proceeds to step 3308. When ALF is enabled at the sequence level, all images in the sequence can be enabled. In some embodiments, step 3306 is "Yes" when sps_alf_enabled_flag has a value of "1."

[0194] In step 3308, the apparatus 400 determines image-level control flags for images in the sequence of video frames. In some embodiments, the control flags may be an indication of whether to encode the images of the video frames using an adaptive loop filter (ALF). An example of an image control flag may be a second control flag. Figure 22A and Figure 22B `ph_alf_enabled_flag` can be a control flag used for ALF at the image level. In some embodiments, the image-level control flag is present in the image header. In some embodiments, `ph_alf_enabled_flag` can have a value of "1" or "0". In some embodiments, if `ph_alf_enabled_flag` is not specified or a value is missing, the default value can be "0".

[0195] In step 3310, the device 400 checks the value of the control flag for ALF at the image level to determine whether ALF is enabled at the image level. If ALF is not enabled at the image level, step 3310 is "No," and process 3300 proceeds to step 3312. When ALF is not enabled at the image level, ALF is also not enabled for all stripes of that image in the video frame. In some embodiments, step 3310 is "No" when ph_alf_enabled_flag has a value of "0." If ALF is enabled at the image level, step 3310 is "Yes," and process 3300 proceeds to step 3314. When ALF is enabled at the image level, all images in the sequence can be enabled. In some embodiments, step 3310 is "Yes" when ph_alf_enabled_flag has a value of "1."

[0196] In some additional or alternative embodiments, the second control flag may be a control flag for the image level or the strip level, depending on the third control flag signaled at the image parameter set (PPS).

[0197] In some additional or alternative embodiments, in response to determining that ALF is enabled at the image level (step 3310 - Yes), device 400 may check the value of a fourth control flag that indicates whether Cross Component Adaptive Loop Filter (CCALF) is enabled at the image level of the video frame for the Cb color component. Figure 22A In this context, ph_cc_alf_cb_enabled_flag can be an example of the fourth control flag.

[0198] In some additional or alternative embodiments, in response to determining that ALF is enabled at the image level (step 3310 - Yes), device 400 may check the value of a fifth control flag that indicates whether Cross Component Adaptive Loop Filter (CCALF) is enabled at the image level of the video frame for the Cr color component. Figure 22A In this context, ph_cc_alf_cr_enabled_flag can be an example of the fifth control flag.

[0199] In step 3312, device 400 checks whether the image is the last image in the sequence. If step 3312 is "no", device 400 proceeds to step 3308 to determine the image-level control flag for the next image in the video frame sequence. Regardless of whether step 3312 is "yes" or "no", process 3300 proceeds to step 3322.

[0200] In step 3314, as determined in step 3308, the apparatus 400 determines control flags at the stripe level for the stripes in the image for the video frame. The stripe control flags may be indications of the state of a particular stripe in the image. In some embodiments, the control flags may be indications of whether to encode the stripes of the image in the video frame using an adaptive loop filter (ALF). Examples of stripe control flags may be third control flags, such as 22A and... Figure 22A As shown, slice_alf_enabled_flag can be a control flag used by AFL at the slice level. In some embodiments, slice_alf_enabled_flag can have a value of "1" or "0". In some embodiments, if no value for slice_alf_enabled_flag is specified or is missing, its default value can be "0".

[0201] In step 3316, the device 400 checks the value of the control flag for ALF at the slice level to determine whether ALF is enabled at the slice level. If ALF is not enabled at the slice level, step 3310 is "No", and process 3300 proceeds to step 3318. In some embodiments, step 3316 is "No" when slice_alf_enabled_flag has a value of "0". If ALF is enabled at the image level, step 3316 is "Yes", and process 3300 proceeds to step 3320. In some embodiments, step 3316 is "Yes" when slice_alf_enabled_flag has a value of "1".

[0202] In step 3318, device 400 checks whether the strip is the last strip in the image. If step 3318 is "no", device 400 proceeds to step 3314 to determine the control flag at the strip in the image for the video frame. Regardless of whether step 3318 is "yes" or "no", process 3300 proceeds to step 3322.

[0203] In step 3320, the apparatus 400 uses an adaptive loop filter (ALF) to encode the stripes, images, and / or sequences of video frames. In some embodiments, when AFL is enabled, color components Y, Cb, or Cr are enabled.

[0204] In step 3322, the device 400 encodes the stripes, images, and / or sequences of video frames without enabling the adaptive loop filter (ALF).

[0205] Figure 34 This is a flowchart illustrating an exemplary process for determining how to encode a video frame using Sample Adaptive Offset (SAO) according to embodiments of the present disclosure. Process 3400 may be performed by apparatus 400 and its sub-components, such as processor 3102.

[0206] In step 3402, device 400 receives one or more video frames.

[0207] In step 3404, the apparatus 400 determines control flags for video frames at the sequence level. In some embodiments, the control flags may be an indication of whether sample adaptive offset (SAO) is used to encode the video frame. An example of the sequence control flags may be a first control flag. Figure 26 As described, sps_sao_enabled_flag can be a sequence-level ALF control flag. In some embodiments, sps_sao_enabled_flag can have a value of "1" or "0".

[0208] In step 3406, device 400 checks the value of a control flag for sequence-level SAO to determine whether SAO is enabled at the sequence level. If SAO is not enabled at the sequence level, step 3406 is "No," and process 3400 proceeds to step 3422. When SAO is not enabled at the sequence level, SAO is also not enabled for all images and all stripes of the video frame. In some embodiments, step 3406 is "No" when sps_sao_enabled_flag has a value of "0." If SAO is enabled at the sequence level, step 3406 is "Yes," and process 3400 proceeds to step 3408. When SAO is enabled at the sequence level, all images in the sequence can be enabled. In some embodiments, step 3406 is "Yes" when sps_sao_enabled_flag has a value of "1."

[0209] In step 3408, the apparatus 400 determines image-level control flags for the images in the sequence of video frames. The image control flags may be indications of the state of all stripes in the image. In some embodiments, the control flags may be indications of whether to encode the image of the video frame using Sample Adaptive Offset (SAO). An example of an image control flag may be a second control flag. Figure 26 As illustrated in the example description, one or both of ph_sao_luma_enabled_flag and ph_sao_chroma_enabled_flag can be image-level SAO control flags. In some embodiments, the image-level control flags are present in the image header. In some embodiments, ph_sao_luma_enabled_flag or ph_sao_chroma_enabled_flag can have a value of "1" or "0". In some embodiments, if ph_sao_luma_enabled_flag or ph_sao_chroma_enabled_flag is not specified or a value is missing, its default value can be "0". Those skilled in the art or of ordinary skill will now understand... Figure 34 The process 3400 shown can be applied to both the luminance component and the chrominance component of SAO.

[0210] In step 3410, the device 400 checks the value of a control flag for image-level SAO to determine whether image-level SAO is enabled. If SAO is not enabled at the image level, step 3410 is "No," and process 3400 proceeds to step 3412. When SAO is not enabled at the image level, SAO is also not enabled for all stripes of that image in the video frame. In some embodiments, step 3410 is "No" when ph_sao_luma_enabled_flag or ph_sao_chroma_enabled_flag has a value of "0." If SAO is enabled at the image level, step 3410 is "Yes," and process 3400 proceeds to step 3414. When SAO is enabled at the image level, all stripes in the image can be enabled. In some embodiments, step 3410 is "Yes" when ph_sao_luma_enabled_flag or ph_sao_chroma_enabled_flag has a value of "1."

[0211] In some additional or alternative embodiments, the second control flag may be a control flag for the image level or the strip level, depending on the third control flag signaled at the image parameter set (PPS).

[0212] In step 3412, device 400 checks whether the image is the last image in the sequence. If step 3412 is "no", device 400 proceeds to step 3408 to determine the control flag at the image location for the next image in the sequence of video frames. Regardless of whether step 3412 is "yes" or "no", process 3400 proceeds to step 3422.

[0213] In step 3414, as determined in step 3408, the apparatus 400 determines control flags at the stripe level for stripes in the image for the video frame. The stripe control flags may be indications of the state of a particular stripe in the image. In some embodiments, the control flags may be indications of whether to encode stripes in the image of the video frame using Sample Adaptive Offset (SAO). An example of a stripe control flag may be a third control flag. Figure 26In the example shown, slice_sao_luma_enabled_flag or slice_sao_chroma_enabled_flag can be control flags for the SAO at the stripe level. In some embodiments, slice_sao_luma_enabled_flag or slice_sao_chroma_enabled_flag can have a value of "1" or "0". In some embodiments, if slice_sao_luma_enabled_flag or slice_sao_chroma_enabled_flag is not specified or a value is missing, the default value can be "0".

[0214] In step 3416, device 400 checks the value of the control flag for SAO at the stripe level to determine whether SAO is enabled at the stripe level. If SAO is not enabled at the stripe level, step 3416 is "No", and process 3400 proceeds to step 3418. In some embodiments, step 3416 is "No" when slice_sao_luma_enabled_flag or slice_sao_chroma_enabled_flag has a value of "0". If SAO is enabled at the stripe level, step 3416 is "Yes", and process 3400 proceeds to step 3420. In some embodiments, step 3416 is "Yes" when slice_sao_luma_enabled_flag or slice_sao_chroma_enabled_flag has a value of "1".

[0215] In step 3418, device 400 checks whether the strip is the last strip in the image. If step 3418 is "no", device 400 proceeds to step 3414 to determine the control flag at the strip in the image of the next strip in the video frame. Regardless of whether step 3418 is "yes" or "no", process 3400 proceeds to step 3422.

[0216] In step 3420, the device 400 encodes the stripes, images, and / or sequences of video frames using Sample Adaptive Offset (SAO) (luminance or chrominance SAO, or based on the former two of the control flags).

[0217] In step 3422, the device 400 encodes the stripes, images, and / or sequences of video frames with Sample Adaptive Offset (SAO) (luminance or chrominance SAO, or based on the former two control flags) disabled.

[0218] Figure 35This is a flowchart consistent with embodiments of the present disclosure, illustrating an exemplary process for determining how to encode video frames while disabling a deblocking filter. Process 3500 may be performed by device 400 and its sub-components, such as processor 3102.

[0219] In step 3502, device 400 receives one or more video frames.

[0220] In step 3504, the apparatus 400 determines control flags for video frames at the sequence level. The sequence control flags may be indications of the state of all images in the sequence. In some embodiments, the control flags may be indications of whether the video frame is to be encoded with the deblocking filter disabled. The sequence control flags may be examples of disable flags used to disable the deblocking filter at the sequence level. In some embodiments, the sequence level may be a first level. Figure 3A In the example shown, `sps_deblocking_filter_disabled_flag` can be a control flag used for a sequence-level deblocking filter. In some embodiments, `sps_deblocking_filter_disabled_flag` can have a value of "1" or "0". In step 3504, the apparatus 400 further determines a sequence-level overlay flag for the deblocking filter used on the video frame. Figure 31A In the described example, `deblocking_filter_override_enabled_flag` can be an example of a sequence-level override flag. In some embodiments, `deblocking_filter_override_enabled_flag` can have a value of "1" or "0".

[0221] In step 3506, the device 400 checks the value of a control flag used to disable the deblocking filter at the sequence level to determine whether deblocking is disabled at the sequence level. If deblocking is not disabled at the sequence level, step 3506 is "No", and process 3500 proceeds to step 3512. When deblocking is disabled at the sequence level, process 3500 proceeds to step 3508. In some embodiments, step 3506 is "No" when sps_deblocking_filter_disabled_flag has a value of "0". In some embodiments, step 3406 is "Yes" when sps_deblocking_filter_disabled_flag has a value of "1".

[0222] In step 3508, the apparatus 400 checks the value of an override flag used to disable the deblocking filter at the sequence level. If an override flag exists for the sequence level, step 3508 is "yes," and process 3500 proceeds to step 3512. In some embodiments, step 3508 is "yes" when deblocking_filter_override_enabled_flag can have a value of "1." If no override flag exists for the sequence level, step 3508 is "no," and process 3500 proceeds to step 351. In some embodiments, step 3508 is "no" when deblocking_filter_override_enabled_flag has a value of "0."

[0223] In step 3510, when deblocking is disabled for the entire video frame sequence and there is no overlay flag, the deblocking filter is not used when encoding video frames for the sequence.

[0224] In step 3512, the apparatus 400 determines control flags for images in the sequence at the image level of video frames. The image control flags may be an indication of the state of all stripes in the image. In some embodiments, the control flags may be an indication of whether images of video frames in the sequence are to be encoded with a deblocking filter disabled. In some embodiments, the image level may be a second level. Examples of image control flags may be disable flags used to disable the deblocking filter at the image level. Figure 3B In the example shown, ph_deblocking_filter_disabled_flag can be a control flag used for image-level deblocking filters. In some embodiments, ph_deblocking_filter_disabled_flag can have a value of "1" or "0". In step 3512, the apparatus 400 further determines an image-level overlay flag for the deblocking filter used on the video frame. Figure 31B In the described example, ph_deblocking_filter_override_enabled_flag could be an example of an override flag at the image level. In some embodiments,

[0225] The ph_deblocking_filter_override_enabled_flag can have a value of "1" or "0".

[0226] In some additional or alternative embodiments, the first level may be a set of image levels, and a first control flag for the first level is signaled at the Image Parameter Set (PPS). In some additional or alternative embodiments, the second level is one of the image levels or strip levels, and a second control flag for the second level is signaled at the Image Header (PH) or Strip Header (SH).

[0227] In step 3516, the device 400 checks the value of a control flag used to disable the deblocking filter at the image level to determine whether deblocking is disabled at the image level. If deblocking is not disabled at the image level, step 3516 is "No", and process 3500 proceeds to step 3522. When deblocking is disabled at the image level, process 3500 proceeds to step 3518. In some embodiments, step 3516 is "No" when ph_deblocking_filter_disabled_flag has a value of "0". In some embodiments, step 3516 is "Yes" when ph_deblocking_filter_disabled_flag has a value of "1".

[0228] In step 3518, device 310 checks the value of an override flag used to disable the deblocking filter at the image level. If an override flag exists for the image level, step 3518 is "Yes," and process 3500 proceeds to step 3522. In some embodiments, step 3588 is "Yes" when ph_deblocking_filter_override_enabled_flag can have a value of "1." If no override flag exists for the sequence level, step 3588 is "No," and process 3500 proceeds to step 3520. In some embodiments, step 3518 is "No" when ph_deblocking_filter_override_enabled_flag has a value of "0."

[0229] In step 3520, when deblocking is disabled for the images of video frames in the sequence and there is no overlay flag, the deblocking filter is not applied to that particular image when the video frame is being encoded.

[0230] In step 3514, device 400 checks whether all images in the sequence have been processed. If step 3514 is "No", device 400 proceeds to step 3512 for the next image in the sequence.

[0231] In step 3522, as determined in step 3516, the device 400 determines control flags at the stripe level for stripes in the image of the video frame. The stripe control flags may be an indication of the state of a particular stripe in the image. In some embodiments, the control flags may be an indication of whether stripes in the image of the video frame are to be encoded with the deblocking filter disabled. An example of an image control flag is a disable flag used to disable the deblocking filter at the stripe level. Figure 31B In the example shown, `slice_deblocking_filter_disabled_flag` can be a control flag used for deblocking filters at the slice level. In some embodiments, `slice_deblocking_filter_disabled_flag` can have a value of "1" or "0". In step 3522, the apparatus 400 further determines a slice-level overlay flag for the deblocking filter used for the video frame. Figure 31B In the example shown, slice_deblocking_filter_override_enabled_flag can be an example of an override flag at the slice level. In some embodiments, slice_deblocking_filter_override_enabled_flag can have a value of "1" or "0".

[0232] In step 3526, device 400 checks the value of a control flag used to disable the deblocking filter at the slice level to determine whether deblocking is disabled at the slice level. If deblocking is not disabled at the slice level, step 3526 is "No", and process 3500 proceeds to step 3532. When deblocking is disabled at the slice level, process 3500 proceeds to step 3528. In some embodiments, step 3526 is "No" when slice_deblocking_filter_disabled_flag has a value of "0". In some embodiments, step 3526 is "Yes" when slice_deblocking_filter_disabled_flag has a value of "1".

[0233] In step 3528, the device checks the value of the override flag used to disable the deblocking filter at the slice level. If an override flag exists for the slice level, step 3528 is "Yes," and process 3500 proceeds to step 3532. In some embodiments, step 3528 is "Yes" when slice_deblocking_filter_override_enabled_flag has a value of "1." If no override flag exists for the slice level, step 3528 is "No," and process 3500 proceeds to step 3530. In some embodiments, step 3528 is "No" when slice_deblocking_filter_override_enabled_flag has a value of "0."

[0234] In step 3530, when deblocking is disabled for stripes of images in a video frame in the sequence and there is no overlay flag, the deblocking filter is not applied to the stripe when the video frame is being encoded.

[0235] In step 3524, device 400 checks whether all stripes of the image have been processed. If step 3524 is "no", device 400 proceeds to step 3522 again for the next strip in the image.

[0236] In step 3532, the apparatus 400 encodes the sequence, images, and / or stripes of video frames with a deblocking filter.

[0237] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and these instructions can be executed by means of a device (such as the disclosed encoder and decoder) to perform the methods described above. Common forms of non-transitory media include, for example, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, caches, registers, any other memory chips or cassettes, and their networking versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0238] The embodiments may be further described using the following terms:

[0239] 1. A video encoding method, comprising:

[0240] Receive video sequences;

[0241] The video sequence is encoded at the sequence level, image level, or stripe level by using control flags for Luminance Mapping with Chroma Scaling (LMCS), wherein the sequence level, image level, and stripe level are levels ordered from high to low.

[0242] The signal notifies a first control flag, which indicates whether the LMCS is enabled at the first level; and

[0243] In response to the first control flag indicating that the LMCS is enabled at the first level, a second control flag is signaled indicating whether the LMCS is enabled at the second level, wherein:

[0244] When the value of the second control flag is equal to 1, the LMCS is enabled at the second level;

[0245] When the value of the second control flag is equal to 0, the LMCS is disabled at the second level; and

[0246] The second level is lower than the first level.

[0247] 2. The video coding method according to Clause 1, wherein the first control flag is a control flag for the LMCS at the sequence level, and the second control flag is a control flag for the LMCS at the image level.

[0248] 3. The video encoding method according to Clause 2 further includes:

[0249] In response to the second control flag indicating that the LMCS is enabled at the second level, a third control flag is signaled indicating whether chroma scaling (CS) is enabled at the second level.

[0250] When the value of the third control flag is equal to 1, the CS is enabled at the second level; and

[0251] When the value of the third control flag is equal to 0, the CS is disabled at the second level.

[0252] 4. The video encoding method according to clause 1 or 2 further includes:

[0253] In response to the second flag indicating that the LMCS is enabled at the second level, a fourth control flag is signaled indicating whether the LMCS is applied at the third level, wherein:

[0254] When the value of the fourth control flag is equal to 1, Luminance Mapping (LM) is applied at the third level, and CS can be applied;

[0255] When the value of the fourth control flag is equal to 0, the LMCS is not applied at the third level; and

[0256] The third level is a level lower than the second level.

[0257] 5. The video encoding method according to Clause 4, wherein the third level is the strip level.

[0258] 6. The video encoding method according to Clause 4, wherein when the second control flag is not notified by a signal, the LMCS is not enabled for the image associated with the second control flag.

[0259] 7. The video coding method according to Clause 4 or 5, wherein when no signal is sent to the fourth control flag, the LMCS is not applied to the stripe associated with the fourth control flag.

[0260] 8. The video encoding method according to Clause 1, wherein when the first control flag is signaled, the lower-level LMCS is not enabled when the second control flag is not signaled.

[0261] 9. The video encoding method according to Clause 1 or 8, wherein when the first control flag is not signaled, the LMCS at the lower level is not enabled regardless of whether the second control flag is signaled.

[0262] 10. A video encoding method, comprising:

[0263] Receive video sequences;

[0264] The video sequence is encoded at the sequence level, image level, or strip level by using control flags for the adaptive loop filter (ALF), wherein the sequence level, image level, and strip level are levels ordered from high to low.

[0265] The signal notifies a first control flag, which indicates whether the ALF is enabled at the first level; and

[0266] In response to the first control flag indicating that the ALF is enabled at the first level, a second control flag is signaled indicating whether the ALF is enabled at the second level, wherein:

[0267] When the value of the second control flag is equal to 1, the ALF is enabled at the second level;

[0268] When the value of the second control flag is equal to 0, the ALF is disabled at the second level; and

[0269] The second level is a level lower than the first level.

[0270] 11. The video coding method according to Clause 10, further wherein the first control flag is a control flag for ALF at the sequence level, and, depending on a third control flag signaled in the Picture Parameter Set (PPS), the second control flag is a control flag for ALF at either the picture level or the strip level.

[0271] 12. The video encoding method according to clause 10 or 11 further includes:

[0272] In response to the second control flag indicating that the ALF is enabled at the second level, a fourth control flag is signaled indicating whether the Cross Component Adaptive Loop Filter (CCALF) for the Cb color component is enabled at the second level, wherein:

[0273] When the value of the fourth control flag is equal to 1, the CCALF for the Cb color component is enabled at the second level; and

[0274] When the value of the fourth control flag is equal to 0, the CCALF used for the Cb color component is disabled at the second level; and

[0275] In response to the second control flag indicating that the ALF is enabled at the second level, a fifth control flag is signaled indicating whether the Cross Component Adaptive Loop Filter (CCALF) for the Cr color component is enabled at the second level, wherein:

[0276] When the value of the fifth control flag is equal to 1, the CCALF for the Cr color component is enabled at the second level; and

[0277] When the value of the fifth control flag is equal to 0, CCALF for the Cr color component is disabled at the second level.

[0278] 13. The video encoding method according to Clause 10, wherein the lower-level ALF is not enabled when the first control flag is signaled but the second control flag is not signaled.

[0279] 14. The video encoding method according to Clause 10 or 11, wherein when the first control flag is not signaled, the ALF at the lower level is not enabled regardless of whether the second control flag is signaled.

[0280] 15. The video encoding method according to clauses 10 to 12, wherein when the parameters of the ALF are determined in the strip header of an image, all strips of the image will be identical to the parameters of the ALF.

[0281] 16. The video encoding method according to clauses 10 to 12, wherein ALF is not enabled for the image associated with the second control flag when the second control flag is not notified by a signal.

[0282] 17. The video encoding method according to clauses 10 to 12, wherein, when the fourth control flag or the fifth control flag is not signaled, CCALF is not enabled for the Cb or Cr component of the image associated with the second control flag.

[0283] 18. The video coding method according to clauses 10 to 12, wherein when the second control flag is not notified by a signal, ALF is not applied to the stripe associated with the second control flag.

[0284] 19. The video encoding method according to Clauses 10-12, wherein when AFL is enabled, the color components Y, Cb, or Cr are enabled.

[0285] 20. A video encoding method, comprising:

[0286] Receive video sequences;

[0287] The video sequence is encoded at the sequence level, image level, or strip level by using control flags for Sample Adaptive Offset (SAO), wherein the sequence level, image level, and strip level are ordered from high to low.

[0288] The signal notifies a first control flag, which indicates whether the SAO is enabled at the first level; and

[0289] In response to the first control flag indicating that the SAO is enabled at the first level, a second control flag is signaled indicating whether the SAO is enabled at the second level, wherein:

[0290] When the value of the second control flag is equal to 1, the SAO for the luminance component is enabled at the second level;

[0291] When the value of the second control flag is equal to 0, the SAO used for the luminance component is disabled at the second level; and

[0292] The second level is a level lower than the first level.

[0293] 21. The video encoding method according to Clause 20 further includes a third control flag signaled at the second control flag, wherein:

[0294] When the value of the third control flag is equal to 1, the SAO for the chromaticity component is enabled at the second level; and

[0295] When the value of the third control flag is equal to 0, the SAO used for the chromaticity component is disabled at the second level.

[0296] 22. The video coding method according to clause 20 or 21, wherein the first control flag is a control flag for SAO at the sequence level, and, depending on a third control flag signaled in the picture parameter set (PPS), the second control flag is a control flag for SAO at one of the picture level or the strip level.

[0297] 23. The video encoding method according to clause 20 or 21, wherein the SAO is disabled for the luminance component of the image associated with the second control flag when the second control flag is not notified by a signal.

[0298] 24. The video coding method according to clause 20 or 21, wherein, when the third control flag is not notified by a signal, the SAO is disabled for the chroma component of the image associated with the third control flag.

[0299] 25. The video encoding method according to Clause 20, wherein when the first control flag is signaled but the second control flag is not signaled, the SAO at the lower level is disabled.

[0300] 26. The video encoding method according to Clause 20 or 21, wherein the lower-level SAO is disabled regardless of whether the second control flag is signaled or not when the first control flag is not signaled.

[0301] 27. The video coding method according to clauses 19 to 26, wherein when the SAO is enabled, the SAO process is applied to the reconstructed image after the deblocking filter processing.

[0302] 28. A video encoding method, comprising:

[0303] Receive video sequences; and

[0304] The video sequence is encoded at the sequence level, picture set level, picture level, or strip level by using control flags for the deblocking filter, wherein:

[0305] When the value of the first control flag at the first level is equal to 1 and the value of the second control flag at the second level is not signaled, the deblocking filter is disabled at the first level; and when the value of the first control flag at the first level is equal to 0 and the value of the second control flag at the second level is not signaled, the deblocking filter is enabled at the first level.

[0306] The first level is a level higher than the second level.

[0307] 29. The video coding method according to Clause 28, wherein the first level is the picture set level and the first control flag is signaled in the picture parameter set (PPS); and the second level is one of the picture level or the strip level and the second control flag is signaled in one of the picture header (PH) or the strip header (SH).

[0308] 30. The video encoding method according to Clause 28 further includes: signaling a third flag in the PPS to indicate whether the signaling of the second control flag is at the image level or the strip level.

[0309] 31. The video coding method according to Clause 28 further includes encoding the video sequence at the sequence level, the set of images level, the image level, or the stripe level by using an overlay flag for a deblocking filter, wherein the overlay flag is used to indicate whether a lower-level control flag can be signaled to overlay a higher-level control flag.

[0310] 32. The video coding method according to Clause 28 further includes: encoding the video sequence at the sequence level, the set of images level, the image level, or the stripe level by using an overlay flag for a deblocking filter, wherein the overlay flag is used to indicate whether a lower-level control flag can be signaled to overlay a higher-level control flag, and

[0311] When a higher-level control flag that signals at the sequence level, image set level, image level, or strip level is equal to 1, and the lower-level control flag does not cover the higher-level control flag, the deblocking filter is not applied to the corresponding sequence, image set, image, or strip.

[0312] 33. A video decoding method, comprising:

[0313] Receive a bitstream containing a video sequence;

[0314] The video sequence is decoded at the sequence level, image level, or stripe level by using control flags for Luminance Mapping with Chroma Scaling (LMCS), wherein the sequence level, image level, and stripe level are ordered from high to low.

[0315] Determine whether the first control flag indicates that the LMCS is enabled at the first level; and

[0316] In response to determining that the first control flag indicates that the LMCS is enabled at the first level, it is determined whether a second control flag indicates that the LMCS is enabled at the second level, wherein:

[0317] When the value of the second control flag is equal to 1, the LMCS is enabled at the second level;

[0318] When the value of the second control flag is equal to 0, the LMCS is disabled at the second level; and

[0319] The second level is a level lower than the first level.

[0320] 34. The video decoding method according to Clause 33, wherein the first control flag is a sequence-level control flag for the LMCS, and the second control flag is an image-level control flag for the LMCS.

[0321] 35. The video decoding method according to Clause 34 further includes:

[0322] In response to determining that the second control flag indicates that the LMCS is enabled at the second level, a third control flag is determined to indicate whether chroma scaling (CS) is enabled at the second level, wherein:

[0323] When the value of the third control flag is equal to 1, the CS is enabled at the second level; and

[0324] When the value of the third control flag is equal to 0, the CS is disabled at the second level.

[0325] 36. The video decoding method according to clause 33 or 34 further includes:

[0326] In response to determining that the second flag indicates that the LMCS is enabled at the second level, a fourth control flag is determined to indicate whether the LMCS is applied at the third level, wherein:

[0327] When the value of the fourth control flag is equal to 1, Luminance Mapping (LM) is applied at the third level, and CS can be applied;

[0328] When the value of the fourth control flag is equal to 0, the LMCS is not applied at the third level; and

[0329] The third level is a level lower than the second level.

[0330] 37. The video decoding method according to Clause 36, wherein the third level is the strip level.

[0331] 38. The video decoding method according to Clause 36, wherein LMCS is not enabled for the image associated with the second control flag when the second control flag is not notified by a signal.

[0332] 39. The video decoding method according to clause 36 or 38, wherein when the fourth control flag is not notified by a signal, the LMCS is not applied to the stripe associated with the fourth control flag.

[0333] 40. The method according to Clause 33, wherein when the first control flag is signaled but the second control flag is not signaled, the LMCS at the lower level is not enabled.

[0334] 41. The video decoding method according to clause 33 or 40, wherein when the first control flag is not signaled, the LMCS at the lower level is not enabled regardless of whether the second control flag is signaled.

[0335] 42. A video decoding method, comprising:

[0336] Receive a bitstream containing a video sequence;

[0337] The video sequence is decoded at the sequence level, image level, or strip level by using control flags for the adaptive loop filter (ALF), wherein the sequence level, image level, and strip level are ordered from high to low.

[0338] Determine whether the first control flag indicates that the ALF is enabled at the first level; and

[0339] In response to determining that the first control flag indicates that the ALF is enabled at the first level, it is determined whether a second control flag indicates that the ALF is enabled at the second level, wherein:

[0340] When the value of the second control flag is equal to 1, the ALF is enabled at the second level;

[0341] When the value of the second control flag is equal to 0, the ALF is disabled at the second level; and

[0342] The second level is a level lower than the first level.

[0343] 43. The video decoding method according to Clause 42, further wherein the first control flag is a sequence-level control flag for ALF, and, depending on a third control flag signaled in the Picture Parameter Set (PPS), the second control flag is a control flag for ALF at either the picture level or the strip level.

[0344] 44. The video decoding method according to clause 42 or 43 further includes:

[0345] In response to determining that the second flag indicates that the ALF is enabled at the second level, it is determined whether a fourth control flag indicates that the Cross Component Adaptive Loop Filter (CCALF) for the Cb color component is enabled at the second level, wherein:

[0346] When the value of the fourth control flag is equal to 1, the CCALF for the Cb color component is enabled at the second level; and

[0347] When the value of the fourth control flag is equal to 0, the CCALF used for the Cb color component is disabled at the second level; and

[0348] In response to determining that the second flag indicates that the ALF is enabled at the second level, a fifth control flag is signaled indicating that the Cross Component Adaptive Loop Filter (CCALF) for the Cr color component is enabled at the second level, wherein:

[0349] When the value of the fifth control flag is equal to 1, the CCALF for the Cr color component is enabled at the second level; and

[0350] When the value of the fifth control flag is equal to 0, the CCALF used for the Cr color component is disabled at the second level.

[0351] 45. The video decoding method according to Clause 42, wherein the lower-level ALF is not enabled when the first control flag is present and when the second control flag is absent.

[0352] 46. ​​The video decoding method according to clause 42 or 43, wherein when the first control flag is absent, the ALF at the lower level is not enabled, regardless of the presence or absence of the second control flag.

[0353] 47. The video decoding method according to clauses 42 to 44, wherein when the parameters of the ALF are determined in the strip header of an image, all strips of the image will have the same parameters as the ALF.

[0354] 48. The video decoding method according to clauses 42 to 44, wherein when the second control flag is not present, ALF is not enabled for the image associated with the second control flag.

[0355] 49. The video decoding method according to clauses 42 to 44, wherein CCALF is not enabled for the Cb or Cr component of the image associated with the second control flag when the fourth control flag or the fifth control flag is not notified by a signal.

[0356] 50. The video decoding method according to clauses 42 to 44, wherein when the second control flag is not present, ALF is not enabled for the stripe associated with the second control flag.

[0357] 51. The video decoding method according to clauses 42 to 44, wherein when AFL is enabled, the color components Y, Cb, or Cr are enabled.

[0358] 52. A video decoding method, comprising:

[0359] Receive a bitstream containing a video sequence;

[0360] The video sequence is decoded at the sequence level, image level, or strip level by using control flags for Sample Adaptive Offset (SAO), wherein the sequence level, image level, and strip level are ordered from high to low.

[0361] Determine whether the first control flag indicates that the SAO is enabled at the first level; and

[0362] In response to determining that the first control flag indicates that SAO is enabled at the first level, it is determined whether a second control flag indicates that the SAO is enabled at the second level, wherein:

[0363] When the value of the second control flag is equal to 1, the SAO for the luminance component is enabled at the second level;

[0364] When the value of the second control flag is equal to 0, the SAO used for the luminance component is disabled at the second level; and

[0365] The second level is a level lower than the first level.

[0366] 53. The video decoding method according to Clause 52 further includes

[0367] Determine whether the third flag indicates that the SAO is enabled at the second level, wherein:

[0368] When the value of the third control flag is equal to 1, the SAO for the chromaticity component is enabled at the second level; and

[0369] When the value of the third control flag is equal to 0, the SAO used for the chromaticity component is disabled at the second level.

[0370] 54. The video decoding method according to clause 52 or 53, wherein the first control flag is a control flag for SAO at the sequence level, and, depending on a third flag signaled in the Picture Parameter Set (PPS), the second control flag is a control flag for SAO at one of the picture level or the strip level.

[0371] 55. The video encoding method according to clause 52 or 53, wherein, when the second control flag is absent, the SAO is disabled for the luminance component of the image associated with the second control flag.

[0372] 56. The video coding method according to clause 52 or 53, wherein, when the third control flag is absent, the SAO is disabled for the chroma components of the image associated with the third control flag.

[0373] 57. The video decoding method according to Clause 52, wherein when the first control flag is present, the SAO at the lower level is disabled when the second control flag is absent.

[0374] 58. The video decoding method according to clause 52 or 54, wherein when the first control flag is absent, the SAO at the lower level is disabled regardless of the presence or absence of the second control flag.

[0375] 59. The video decoding method according to clauses 52 to 58, wherein when the SAO is enabled, the SAO process is applied to the reconstructed image after the deblocking filter process.

[0376] 60. A video decoding method, comprising:

[0377] Receive a bitstream containing a video sequence; and

[0378] The video sequence is decoded at the sequence level, set level, image level, or strip level by using deblocking filter control flags, wherein:

[0379] When the value of the first control flag at the first level is equal to 1 and the second control flag at the second level does not exist, the deblocking filter is disabled at the first level.

[0380] The deblocking filter is enabled at the first level when the value of the first control flag at the first level is equal to 0 and the second control flag at the second level does not exist; and the first level is a level lower than the second level.

[0381] 61. The video decoding method according to Clause 60, wherein the first level is the image set level and the first control flag is signaled in the image parameter set (PPS); and the second level is one of the image level or the strip level and the second control flag is signaled in one of the image header (PH) or the strip header (SH).

[0382] 62. The video decoding method according to Clause 60 further includes: determining whether the second marker is signaled at the image level or at the strip level based on a third marker transmitted by a signal in the PPS.

[0383] 63. The video decoding method according to Clause 60 further includes decoding the video sequence at the sequence level, the image set level, the image level, or the stripe level by using an overlay flag for a deblocking filter, wherein the overlay flag is used to indicate whether a lower-level control flag is present for overlaying a higher-level control flag.

[0384] 64. The video decoding method according to clause 60 further includes: decoding the video sequence at the sequence level, the image set level, the image level, or the stripe level by using an overlay flag for a deblocking filter, wherein the overlay flag is used to indicate whether a lower-level control flag exists for overlaying a higher-level control flag, and

[0385] When a higher control flag exists at the sequence level, the image set level, the image level, or the strip level and is equal to 1, the deblocking filter is not applied to the corresponding sequence, image set, image, or strip if the lower-level control flag does not cover the higher control flag.

[0386] It should be noted that relational terms such as “first” and “second” in this document are used only to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” “containing,” and “comprising,” and other similar forms are equivalent in meaning and are open-ended, because one or more items following any of these words do not imply an exhaustive list of such one or more items, or that it is limited to only the listed one or more items.

[0387] As used herein, unless otherwise specified, the term "or" includes all possible combinations except where impractical. For example, if a database is declared to include A or B, then unless otherwise expressly stated or impractical, the database may include A, or B, or A and B. As a second example, if a database is declared to include A, B, or C, then unless otherwise expressly stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0388] It should be understood that the above embodiments can be implemented by hardware, software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. When executed by a processor, the software can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, software, or a combination of hardware and software. Those skilled in the art will also understand that the above-described multiple modules / units can be combined into one module / unit, and each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.

[0389] In the foregoing description, numerous specific details have been described with reference to embodiments, which may vary depending on implementation. Certain modifications and variations can be made to the described embodiments. Other embodiments will be apparent to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims. The sequence of steps shown in the accompanying drawings is for illustrative purposes only and is not intended to limit one to any particular sequence of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order while implementing the same method.

[0390] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A video encoder, comprising: a memory storing a set of instructions; as well as At least one processor, configured to execute the set of instructions to cause the video encoder to perform operations including: The bitstream is encoded based on control flags used for Luminance Mapping and Chroma Scaling (LMCS), specifically including: In the image header, a signal is provided for a first control flag for luminance mapping and chrominance scaling. The first control flag indicates whether luminance mapping and chrominance scaling are enabled in the current image. The value of the first control flag equal to 1 indicates that luminance mapping and chrominance scaling are enabled in the current image, and the value of the first control flag equal to 0 indicates that luminance mapping and chrominance scaling are not enabled in the current image. In response to the first control flag being equal to 1, a second control flag for chroma residual scaling is signaled in the image header. This second control flag indicates whether chroma residual scaling is enabled and whether it may be applied to the current image. A value of 1 for the second control flag indicates that chroma residual scaling is enabled and may be applied to the current image, while a value of 0 indicates that chroma residual scaling is not enabled and is not applied to the current image. The strip header signals a third control flag for luminance mapping and chroma scaling. The third control flag indicates whether luminance mapping is enabled and whether chroma residual scaling may be applied to the current strip. A value of 1 for the third control flag indicates that luminance mapping is applied and chroma scaling may be applied to the current strip. A value of 0 for the third control flag indicates that neither luminance mapping nor chroma scaling is applied to the current strip.

2. The video encoder according to claim 1, wherein The first control flag is an image-level LMCS control flag, the second control flag is an image-level LMCS control flag, and the third control flag is a strip-level LMCS control flag.

3. A video decoder, comprising: a memory storing a set of instructions; as well as At least one processor is configured to execute the set of instructions to cause the decoder to perform operations including: Receive bit stream; Decoding the bitstream based on the control flags in the bitstream used for Luminance Mapping and Chroma Scaling (LMCS) specifically includes: Decode a first control flag for luminance mapping and chrominance scaling from the image head. The first control flag indicates whether luminance mapping and chrominance scaling are enabled in the current image. The value of the first control flag equal to 1 indicates that luminance mapping and chrominance scaling are enabled in the current image, and the value of the first control flag equal to 0 indicates that luminance mapping and chrominance scaling are not enabled in the current image. In response to the first control flag being equal to 1, a second control flag for chroma residual scaling is decoded from the image header. The second control flag indicates whether chroma residual scaling is enabled and whether it may be applied to the current image. A value of 1 for the second control flag indicates that chroma residual scaling is enabled and may be applied to the current image, while a value of 0 indicates that chroma residual scaling is not enabled and is not applied to the current image. Decode a third control flag from the strip header for luminance mapping and chroma scaling. The third control flag indicates whether luminance mapping is enabled and whether chroma residual scaling may be applied to the current strip. A value of 1 for the third control flag indicates that luminance mapping is applied and chroma scaling may be applied to the current strip. A value of 0 for the third control flag indicates that neither luminance mapping nor chroma scaling is applied to the current strip.

4. The video decoder according to claim 3, wherein The first control flag is an image-level LMCS control flag, the second control flag is an image-level LMCS control flag, and the third control flag is a strip-level LMCS control flag.

5. A non-transitory computer-readable medium storing an instruction set and a video bitstream, the instruction set being executable by one or more processors to generate the video bitstream, the method comprising: The bitstream is encoded based on control flags used for Luminance Mapping and Chroma Scaling (LMCS), specifically including: In the image header, a signal is provided for a first control flag for luminance mapping and chrominance scaling. The first control flag indicates whether luminance mapping and chrominance scaling are enabled in the current image. The value of the first control flag equal to 1 indicates that luminance mapping and chrominance scaling are enabled in the current image, and the value of the first control flag equal to 0 indicates that luminance mapping and chrominance scaling are not enabled in the current image. In response to the first control flag being equal to 1, a second control flag for chroma residual scaling is signaled in the image header. This second control flag indicates whether chroma residual scaling is enabled and whether it may be applied to the current image. A value of 1 for the second control flag indicates that chroma residual scaling is enabled and may be applied to the current image, while a value of 0 indicates that chroma residual scaling is not enabled and is not applied to the current image. The strip header signals a third control flag for luminance mapping and chroma scaling. The third control flag indicates whether luminance mapping is enabled and whether chroma residual scaling may be applied to the current strip. A value of 1 for the third control flag indicates that luminance mapping is applied and chroma scaling may be applied to the current strip. A value of 0 for the third control flag indicates that neither luminance mapping nor chroma scaling is applied to the current strip.

6. The non-transitory computer-readable medium according to claim 5, wherein... The first control flag is an image-level LMCS control flag, the second control flag is an image-level LMCS control flag, and the third control flag is a strip-level LMCS control flag.

Images