Relay adjusting circuit of endoscope and endoscope

Abstract

According to the relay adjusting circuit of the endoscope and the endoscope, an input interface, a clock buffer, an input impedance adjusting module, an output matching adjusting module and an output interface are arranged, and the input end of the clock buffer is electrically connected with the input interface; the input impedance adjusting module is connected to the input end and the grounding end of the clock buffer in parallel, the output matching adjusting module is electrically connected with the output end of the clock buffer, and the output interface is electrically connected with the output matching adjusting module; wherein the clock buffer is used for receiving a first clock driving signal adjusted by the input impedance adjusting module, enhancing the driving capability of the adjusted first clock driving signal, obtaining a second clock driving signal and outputting the second clock driving signal; and the output matching adjustment module is used for adjusting the signal peak value of the second clock driving signal and outputting a third clock driving signal with recognizable high and low level properties so as to compensate signal attenuation formed by long-distance transmission and improve the accuracy of image acquisition.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of CMOS image sensor endoscopes, and in particular to a relay adjustment circuit of an endoscope and the endoscope. BACKGROUND

[0002] As an important medical diagnosis and treatment tool, one of the core performance indicators of an endoscope system is image display quality. In current long-line probe endoscope systems, the image signal transmission path is usually long, and needs to pass through two long-distance transmission lines of "probe image sensor - handle" and "main machine - handle". In the image signal transmission process, the integrity of the clock signal (XCLK) is crucial, which directly relates to the accuracy of image sensor data acquisition and the quality of the final display image.

[0003] To cope with the attenuation of the signal in long-line transmission, in the prior art, a resistance is added on the clock signal or image output signal line on the endoscope mainboard for signal adjustment to improve the image quality collected by the image sensor when receiving the clock signal. However, with the increasing number of endoscope manufacturers and the continuous expansion of their application scenarios, there are great differences in the design of the control mainboard on the market. More importantly, to adapt to different scene requirements, the length of the transmission line connecting the handle and the endoscope probe has multiple specifications from 1 meter to 4 meters. The clock signal will be significantly attenuated during long-distance transmission, and the longer the transmission line, the greater the signal attenuation, and the slower the edge will become, and the driving ability will decrease sharply. When the transmission line is too long, the resistance adjustment alone cannot compensate for the deterioration of the signal quality at the far end. The decline in the quality of the clock signal will lead to timing errors or unstable data acquisition of the image sensor, and finally the image on the display screen will appear blurred, jitter, striped noise, or even signal interruption, which seriously affects the accuracy and reliability of the diagnosis. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a relay adjustment circuit of an endoscope and the endoscope, which can effectively compensate for the attenuation of the clock signal caused by long-distance transmission, significantly improve the accuracy of image acquisition and the image quality of the display end, and enable the system to be widely compatible with transmission lines of different specifications from 1m to 4m, thereby enhancing the adaptability and flexibility of the product.

[0005] To achieve the above-mentioned purpose, a first aspect of the embodiments of the present application provides a relay adjustment circuit of an endoscope, comprising: an input interface, configured to connect a control mainboard of the endoscope and receive a first clock driving signal output by the control mainboard; a clock buffer, an input end of the clock buffer being electrically connected with the input interface; The input impedance adjusting module is connected in parallel to the input end and the ground end of the clock buffer; The output matching adjusting module is electrically connected with the output end of the clock buffer; The output interface is electrically connected with the output matching adjusting module; The input impedance adjusting module is configured to adjust the input impedance of the clock buffer so that the load capacity of the clock buffer matches the driving capacity of the first clock driving signal; The clock buffer is configured to receive the first clock driving signal transmitted from the input interface and adjusted by the input impedance adjusting module, and to enhance the driving capacity of the adjusted first clock driving signal to obtain a second clock driving signal and output the second clock driving signal; The output matching adjusting module is configured to adjust the signal peak-to-peak value of the second clock driving signal to output a third clock driving signal having identifiable high and low level properties; The output interface is configured to transmit the third clock driving signal to the image sensor of the endoscope.

[0006] Further, in some embodiments, the relay adjusting circuit further comprises: The first analog ground interface is electrically connected with the input impedance adjusting module and the ground end of the clock buffer, respectively, and is configured to connect the control mainboard of the endoscope to ground the clock buffer and the input impedance adjusting module; The second analog ground interface is electrically connected with the output matching adjusting module, and is configured to connect the control mainboard of the endoscope to ground the output matching adjusting module.

[0007] Further, in some embodiments, the input impedance adjusting module comprises a first resistor, one end of the first resistor is electrically connected with the input end of the clock buffer, and the other end of the first resistor is electrically connected between the ground end of the clock buffer and the first analog ground interface.

[0008] Further, in some embodiments, the first resistor has a value ranging from 1kΩ to 10kΩ.

[0009] Further, in some embodiments, the output matching adjusting module comprises a second resistor and a first capacitor; One end of the second resistor is electrically connected with the output end of the clock buffer, and the other end of the second resistor is electrically connected with the output interface; The first end of the first capacitor is electrically connected between the second resistor and the output end of the clock buffer, or the first end of the first capacitor is electrically connected between the second resistor and the output interface; The second end of the first capacitor is electrically connected with the second analog ground interface.

[0010] Further, in some embodiments, the second resistor has a resistance in a range from 10Ω to 1.5KΩ, and the first capacitor has a capacitance in a range from 10pf to 200pf.

[0011] Further, in some embodiments, the relay adjustment circuit further comprises: a third resistor, the third resistor being connected in series between the output matching adjustment module and the output interface, and the third resistor being configured to absorb the reflected signal corresponding to the image sensor transmitted through the output interface.

[0012] Further, in some embodiments, the clock buffer has a working voltage equal to the working voltage of the image sensor, and an input / output frequency of the clock buffer is greater than the frequency of the first clock driving signal.

[0013] Further, in some embodiments, the working voltage of the clock buffer is 3.3v.

[0014] To achieve the above object, a second aspect of the embodiments of the present application provides an endoscope, comprising: a handle, the handle comprising a control end interface circuit, a detection end interface circuit, and a relay adjustment circuit of the endoscope according to the first aspect, an input interface in the relay adjustment circuit being electrically connected to the control end interface circuit, and an output interface in the relay adjustment circuit being electrically connected to the detection end interface circuit; a control mainboard, the control mainboard being connected to the control end interface circuit through a transmission line, and the control mainboard being configured to transmit the first clock driving signal to the handle; a probe, the probe comprising an image sensor, and the image sensor being connected to the detection end interface circuit through a transmission line; the image sensor being configured to receive the third clock driving signal obtained after the signal is enhanced by the relay adjustment circuit, and perform image collection of the endoscope based on the third clock driving signal.

[0015] According to the relay adjustment circuit of the endoscope and the endoscope provided by the embodiment of the present application, the following beneficial effects are achieved: by integrating a dedicated clock buffer inside the handle of the endoscope, the mainboard clock signal that has been attenuated after long-distance transmission can be effectively reshaped and the driving capability can be enhanced, the core problems of signal edge delay and insufficient driving capability caused by the change of the length of the 1m to 4m transmission line are solved, and the waveform characteristics of the signal are ensured to be complete when the signal is transmitted to the remote probe; meanwhile, by introducing an input impedance adjustment module, the input impedance of the relay circuit can be accurately matched with the clock signal driving capability output by the mainboards of different manufacturers and different designs through a flexible parallel impedance network, the signal reflection is effectively suppressed, and the reception integrity and system compatibility of the front-end signal are improved; and by finely adjusting the amplitude (peak-to-peak value) of the enhanced clock signal through the output matching adjustment module, a clock signal with stable high and low levels and strictly meeting the identification requirements (such as 0.8V~2.0V) of the image sensor can be output, and the accuracy of the image data acquisition timing is fundamentally ensured; secondly, as an independent intermediate driving node located in the handle, the relay circuit greatly expands the adaptation capability of the endoscope system, the same host platform can be flexibly adapted to probes with different lengths, the overall design change cost and complexity caused by the upgrade of the cable specification are greatly reduced, and the adaptability and flexibility of the product are enhanced; finally, by completely improving the quality of the clock signal at the relay link, the stability of the data collected by the image sensor is directly improved, and finally a clear, stable, non-dragging and non-jittering high-quality image is presented at the display end, and the reliability and user experience of medical diagnosis or industrial detection are significantly enhanced.

[0016] Other features and advantages of the present application will be set forth in the following description, and in part will be apparent from the description. The aims and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the description and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present application and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0018] The present application will be further described below in combination with the drawings and embodiments; Figure 1 is an optional schematic diagram of the relay adjustment circuit of the endoscope provided by the embodiment of the present application; Figure 2 is a second optional schematic diagram of the relay adjustment circuit of the endoscope provided by the embodiment of the present application; Figure 3is a third alternative schematic diagram of a relay adjustment circuit of an endoscope provided by an embodiment of the present application; Figure 4 is a fourth alternative schematic diagram of a relay adjustment circuit of an endoscope provided by an embodiment of the present application; Figure 5 is a fifth alternative schematic diagram of a relay adjustment circuit of an endoscope provided by an embodiment of the present application; Figure 6 is an alternative schematic diagram of a control end interface circuit of an endoscope provided by an embodiment of the present application; Figure 7 is an alternative schematic diagram of a detection end interface circuit of an endoscope provided by an embodiment of the present application.

[0019] The figure mark: input interface 10, clock buffer 20, input impedance adjustment module 30, first resistance 31, output matching adjustment module 40, second resistance 41, first capacitor 42, output interface 50, first analog ground interface 60, second analog ground interface 70, control end interface circuit 80, detection end interface circuit 90. DETAILED DESCRIPTION

[0020] This part will describe the specific embodiments of the present application in detail, the preferred embodiments of the present application are shown in the drawings, the role of the drawings is to supplement the description of the text part with graphics, so that people can intuitively and visually understand each technical feature and the overall technical scheme of the present application, but it cannot be understood as a limitation on the protection scope of the present application.

[0021] In the description of the present application, if the first, second is used only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features, it should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0022] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be understood broadly, and those skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical scheme.

[0023] To address signal attenuation during long-distance transmission, current technology involves adding resistors to the clock or image output signal lines on the endoscope's mainboard for signal conditioning. This improves the image quality acquired by the image sensor upon receiving the clock signal. However, with the increasing number of endoscope manufacturers and the expanding application scenarios, there are significant differences in the design of control mainboards on the market. More importantly, to adapt to different scenario requirements, the transmission line length connecting the handle and the endoscope probe varies from 1 meter to 4 meters. Clock signals experience significant loss during long-distance transmission; the longer the transmission line, the greater the signal attenuation, resulting in sluggish edges and a sharp decrease in driving capability. When the transmission line is too long, resistor adjustment alone is insufficient to compensate for the signal quality degradation at the far end. Deterioration in clock signal quality can lead to sampling timing errors or unstable data acquisition by the image sensor, ultimately manifesting as blurry, jittery, striped noise, or even signal interruption in the image on the display screen, severely impacting the accuracy and reliability of diagnosis.

[0024] Based on this, the present application provides a relay adjustment circuit and endoscope for an endoscope, which can effectively compensate for the clock signal attenuation caused by long-distance transmission, significantly improve the accuracy of image acquisition and the image quality of the display end, and enable the system to be widely compatible with transmission lines of different specifications from 1m to 4m, thereby enhancing the adaptability and flexibility of the product.

[0025] Therefore, the embodiments of this application will be further described below with reference to the accompanying drawings.

[0026] Reference Figure 1 As shown, Figure 1 This is an optional schematic diagram of the relay adjustment circuit of an endoscope provided in the embodiments of this application. The relay adjustment circuit of the endoscope includes an input interface 10, a clock buffer 20, an input impedance adjustment module 30, an output matching adjustment module 40, and an output interface 50. The input terminal of the clock buffer 20 is electrically connected to the input interface 10. The input impedance adjustment module 30 is connected in parallel to the input terminal and the ground terminal of the clock buffer 20. The output matching adjustment module 40 is electrically connected to the output terminal of the clock buffer 20. The output interface 50 is electrically connected to the output matching adjustment module 40. The input interface 10 is used to connect to the control board of the endoscope and receive the first clock drive signal XCLK output by the control board. The input impedance adjustment module 30 is used to adjust the input impedance of the clock buffer 20 so that the load capacity of the clock buffer 20 matches the driving capacity of the first clock drive signal XCLK. The clock buffer 20 is configured to receive the first clock driving signal XCLK transmitted from the input interface 10 and adjusted by the input impedance adjustment module 30, and to drive the adjusted first clock driving signal XCLK to obtain a second clock driving signal and output the second clock driving signal; the output matching adjustment module 40 is configured to adjust a signal peak-to-peak value of the second clock driving signal to output a third clock driving signal S_XCLK having identifiable high and low level properties; and the output interface 50 is configured to transmit the third clock driving signal S_XCLK to an image sensor of the endoscope.

[0027] It should be noted that the working voltage of the clock buffer 20 is equal to the working voltage of the image sensor, and the input / output frequency of the clock buffer 20 is greater than the frequency of the first clock driving signal XCLK.

[0028] In a possible embodiment, the working voltage of the clock buffer 20 is 3.3v.

[0029] The clock buffer 20 is one of the main devices of the present application, and adding the clock buffer 20 at the handle of the endoscope has the following two advantages. On the one hand, since the control mainboards of endoscopes of various manufacturers on the market are designed differently, there is a certain difference in the high and low levels of the first clock driving signal XCLK output by the mainboard, and inserting the clock buffer 20 at the handle of the endoscope can make the output clock signal have fixed high and low levels and good falling and rising edges. On the other hand, when the clock line grows, the load capacitance of the line becomes larger, resulting in larger delay. If the clock buffer 20 is not inserted, the parasitic capacitance on the whole transmission line becomes larger, resulting in a larger delay of the signal. At this time, inserting the clock buffer 20 at the connecting plate of the handle can reduce the load capacitance of the circuit, thereby increasing the driving capability of the clock driving signal XCLK.

[0030] Notably, in the embodiments of the present application, by integrating a dedicated clock buffer 20 inside the handle of the endoscope, the mainboard clock signal that has been attenuated after long-distance transmission can be effectively reshaped and the driving capability can be enhanced, thus completely solving the core problems of signal edge delay and insufficient driving capability caused by the change in the length of the 1m to 4m transmission line, and ensuring that the signal maintains complete waveform characteristics when transmitted to the distal probe; at the same time, by introducing an input impedance adjustment module 30, the input impedance of the relay circuit can be precisely matched with the clock signal driving capability output by mainboards of different manufacturers and different designs through a flexible parallel impedance network, thus effectively suppressing signal reflection and improving the reception integrity and system compatibility of the front-end signal; and by fine-tuning the amplitude (peak-to-peak value) of the enhanced clock signal through an output matching adjustment module 40, a clock signal with stable high and low levels and strictly meeting the image sensor recognition requirements (such as 0.8V~2.0V) can be output, thus fundamentally ensuring the accuracy of the image data acquisition timing; secondly, as an independent intermediate driving node located in the handle, the relay circuit greatly expands the adaptation capability of the endoscope system, and the same host platform can flexibly adapt to probes of different lengths, thus greatly reducing the overall design change cost and complexity caused by the upgrade of cable specifications and enhancing the adaptability and flexibility of the product; finally, by completely improving the quality of the clock signal at the relay link, the stability of the data collected by the image sensor is directly improved, and finally a clear, stable, non-lagging, and non-jittering high-quality image is presented at the display end, thus significantly enhancing the reliability and user experience of medical diagnosis or industrial detection.

[0031] In a possible embodiment, the relay adjustment circuit further comprises a first analog ground interface 60 and a second analog ground interface 70, the first analog ground interface 60 is electrically connected with the input impedance adjustment module 30 and the ground end of the clock buffer 20 respectively, and the second analog ground interface 70 is electrically connected with the output matching adjustment module 40, the first analog ground interface 60 is used to connect the control mainboard of the endoscope to ground the clock buffer 20 and the input impedance adjustment module 30; and the second analog ground interface 70 is used to connect the control mainboard of the endoscope to ground the output matching adjustment module 40.

[0032] It should be noted that the embodiment of the present application realizes the physical separation of the input and output loop grounding paths by setting the independent first analog ground interface 60 and the second analog ground interface 70, and the innovative design forms a complete and isolated analog signal grounding system: the first analog ground interface 60 directly leads the ground end of the clock buffer 20 and the input impedance adjustment module 30 back to the control mainboard ground reference point, ensuring that the input stage signal is referenced to the mainboard ground plane, effectively avoiding the potential deviation and noise interference of the input signal due to the inconsistent grounding path; the second analog ground interface 70 provides an independent, low-impedance dedicated grounding return path for the output matching adjustment module 40, so that the enhanced clock signal can be amplitude-adjusted and output with a pure reference plane, completely blocking the coupling interference of the sensitive input ground loop in the return process of the output stage large current. This separated grounding architecture significantly improves the anti-common-mode noise capability and system stability of the entire relay drive circuit, ensuring that the rising / falling edge of the clock signal after long-distance transmission remains steep and clean, and the high and low level amplitude is accurately and stably within the image sensor recognition threshold of 0.8V~2.0V, thereby greatly improving the integrity and reliability of signal transmission. At the same time, the design enhances the compatibility and adaptability of the relay circuit to different mainboard designs and ground layout, providing a crucial foundation for the endoscopic system to adapt to 1-meter to 4-meter long-line probes of various specifications, ultimately presenting a non-jittering, non-distorted high-definition image on the display end.

[0033] Further, the input impedance adjustment module 30 includes a first resistor 31, one end of the first resistor 31 is electrically connected with the input end of the clock buffer 20, and the other end of the first resistor 31 is electrically connected between the ground end of the clock buffer 20 and the first analog ground interface 60. In a possible embodiment, the value of the first resistor 31 ranges from 1kΩ to 10kΩ.

[0034] It should be noted that the input impedance adjusting module 30 in the embodiment of the present application is directly connected between the input end of the clock buffer 20 and the first analog ground interface 60, thereby constructing an accurately controllable input impedance matching network. The design makes the impedance adjustment of the input loop no longer dependent on the common ground plane on the PCB, but directly traces back to the clean reference ground of the mainboard through the independent analog ground interface, effectively avoiding the noise interference and potential fluctuation introduced by the common ground impedance. The resistance value of the first resistor 31 can be accurately configured according to the driving capability of the clock signal of different mainboards, ensuring that the input impedance is optimally matched with the signal source, avoiding the aggravation of signal reflection due to excessively high impedance, and preventing excessive loading of the front-stage mainboard drive circuit due to excessively low impedance. This precise impedance matching not only significantly improves the signal-to-noise ratio and signal integrity of the clock signal input end, ensuring that the clock buffer 20 can receive an input signal with clear edges and stable levels, but also enhances the compatibility with mainboards designed by different manufacturers, making the relay circuit stable and adaptive to mainboards with various output characteristics, thereby laying a solid foundation for subsequent signal enhancement and transmission.

[0035] Further, with reference to Figure 1 or Figure 2 the, Figure 2 is a second alternative schematic diagram of the relay adjusting circuit of the endoscope provided by the embodiment of the present application. The output matching adjusting module 40 includes a second resistor 41 and a first capacitor 42. One end of the second resistor 41 is electrically connected to the output end of the clock buffer 20, and the other end of the second resistor 41 is electrically connected to the output interface 50. Figure 1 It can be known that the first end of the first capacitor 42 is electrically connected between the second resistor 41 and the output interface 50, and the second end of the first capacitor 42 is electrically connected to the second analog ground interface 70. From Figure 2 It can be known that the first end of the first capacitor 42 is electrically connected between the second resistor 41 and the output end of the clock buffer 20, and the second end of the first capacitor 42 is electrically connected to the second analog ground interface 70. Among them, the first capacitor 42 is arranged in front of the second resistor 41 and electrically connected to the output end of the clock buffer 20, which can make the output matching adjusting module 40 have a better effect of suppressing signal reflection.

[0036] It should be noted that, by adopting the cooperative design of the second resistor 41 and the first capacitor 42 in the output matching adjustment module 40, a high-efficiency and reliable signal conditioning and output network is constructed: the second resistor 41 is connected in series between the output end of the clock buffer 20 and the output interface 50, which not only plays a role of impedance matching and effectively suppresses signal reflection, but also protects the output stage circuit as a current-limiting resistor; the first capacitor 42 is connected in parallel between the output end of the clock buffer 20 and the second analog ground interface 70, and forms an RC filter network with the second resistor 41, which can effectively filter out high-frequency harmonic noise and power supply noise of the clock signal, and significantly purify the output signal waveform. This structure precisely controls the amplitude and driving capability of the output signal through the second resistor 41, and provides a pure high-frequency ground path through the first capacitor 42, and the two work together to ensure that the output third clock drive signal S_XCLK has steep rising / falling edges and stable peak-to-peak values. In particular, the ground end of the first capacitor 42 is directly connected to the independent second analog ground interface 70 instead of the common ground plane, which completely blocks the path of output stage noise coupling through the ground wire to interfere with the previous stage circuit, greatly improving the anti-interference ability of the system. This design enables the high and low levels of the output clock signal to be stably maintained within the ideal range of 0.8-2.0V, ensuring that image sensors at the end of transmission lines of different lengths (1-4 meters) can all receive complete and reliable clock signals, thereby significantly improving image acquisition quality and picture stability at the display end, while enhancing the adaptability and compatibility of the system to different line length probes.

[0037] It is worth noting that the second resistor 41 and the first capacitor 42 form an RC filter network, and when the second clock drive signal output by the clock buffer 20 buffer is matched through the RC filter network, the output third clock drive signal S_XCLK provides a high-quality clock signal for the image sensor of the endoscope. In this output matching adjustment module 40, appropriate values of the second resistor 41 and the first capacitor 42 need to be selected. If the value of the first capacitor 42 is too large, the peak-to-peak value of the output clock signal is small when the circuit reaches a steady state, and the image sensor cannot effectively collect data. The value of the first capacitor 42 should not be too small, and if the value of the first capacitor 42 is too small, the first capacitor 42 only has the function of slowing down the signal edge and cannot effectively adjust the peak-to-peak value of the clock signal, affecting the image effect of the collected image.

[0038] After comprehensive consideration, the value of the second resistor 41 is in the range of 10Ω-1.5KΩ, and the value of the first capacitor 42 is in the range of 10pf-200pf.

[0039] At the same time, the output matching adjustment module 40 of the present application embodiment can also consider the parasitic capacitance of the wire itself, as shown in Figure 3 Figure 3 ​is a third alternative schematic diagram of the relay adjustment circuit of the endoscope provided by the embodiments of the present application, the first capacitor 42 can be removed alone. Alternatively, referring to Figure 4 and Figure 5 as shown, Figure 4 is a fourth alternative schematic diagram of the relay adjustment circuit of the endoscope provided by the embodiments of the present application, Figure 5 is a fifth alternative schematic diagram of the relay adjustment circuit of the endoscope provided by the embodiments of the present application, the first resistor 31 can also be removed alone. Therefore, the circuits formed by changing the implementation manners of them without departing from the technical principles of the present application should also belong to the protection scope of the present application.

[0040] Further, the relay adjustment circuit described above further includes a third resistor, the third resistor is connected in series between the output matching adjustment module 40 and the output interface 50, and the third resistor is used for absorbing the reflection signal corresponding to the image sensor transmitted through the output interface 50.

[0041] It should be noted that the embodiments of the present application construct a high-efficiency reflection signal absorption network by connecting the third resistor in series between the output matching adjustment module 40 and the output interface 50. The resistor can effectively suppress and absorb the signal reflection wave generated by the impedance mismatch of the transmission line, prevent the reflection signal from forming a standing wave or causing signal overshoot / undershoot in the transmission channel, and significantly improve the signal integrity. The precise matching of the third resistor and the characteristic impedance of the transmission line enables the signal energy to be effectively transmitted to the far-end load rather than reflected back to the source end, ensuring the clarity and stability of the clock signal waveform. This design is particularly suitable for application scenarios of transmission lines of different lengths, can adaptively eliminate the impedance mismatch problem caused by the change of the line length, and greatly enhances the compatibility of the system to various probes. By suppressing the reflection interference, the structure ensures that the third clock drive signal S_XCLK transmitted to the image sensor has accurate and stable high-low level sequences, reduces the phenomena such as image jitter, ghosting or data acquisition errors caused by signal reflection, and significantly improves the stability and reliability of the image quality at the display end. At the same time, this scheme does not require complex active circuits, and realizes efficient signal conditioning with simple passive components, reducing the system cost and design complexity.

[0042] The second aspect of the embodiments of the present application further proposes an endoscope, which comprises a handle, a control mainboard and a probe, the control mainboard is connected with the control end interface circuit 80 through a transmission line, the control mainboard is used for transmitting a first clock drive signal to the handle, the probe internally includes an image sensor, the image sensor is connected with the detection end interface circuit 90 through a transmission line, and the image sensor is used for receiving a third clock drive signal obtained after signal enhancement by the relay adjustment circuit, and performing endoscope image acquisition based on the third clock drive signal.

[0043] wherein, referring to Figure 6 andFigure 7 As shown, Figure 6 is an optional schematic diagram of a control end interface circuit of an endoscope provided by an embodiment of the present application, Figure 7 is an optional schematic diagram of a detection end interface circuit of an endoscope provided by an embodiment of the present application, the handle internally includes a control end interface circuit 80, a detection end interface circuit 90, and the above-mentioned relay adjustment circuit of the endoscope, the input interface 10 in the relay adjustment circuit is electrically connected with the control end interface circuit 80, and the output interface 50 in the relay adjustment circuit is electrically connected with the detection end interface circuit 90.

[0044] It should be noted that the endoscope of the embodiment of the present application, by integrating a special relay adjustment circuit inside the handle of the endoscope, a complete signal enhancement and conditioning system is constructed, and the fundamental improvement of the transmission quality of the clock signal is realized. The relay circuit is ingeniously arranged at the key transmission node between the control mainboard and the probe image sensor, the input interface 10 thereof is connected with the control end interface circuit 80 to receive the first clock drive signal attenuated from the mainboard, and the output interface 50 thereof is connected with the detection end interface circuit 90 to output the third clock drive signal enhanced to the distal image sensor. Such an architecture enables the relay circuit to accurately compensate for the signal attenuation caused by different lengths of transmission lines (1-4 meters), greatly improves the signal driving capability through the clock buffer 20, and ensures that the signal still maintains the complete waveform characteristics even under the longest transmission distance. The input impedance adjustment module 30 realizes perfect matching with different mainboard output characteristics, and the output matching adjustment module 40 finely adjusts the signal amplitude through the RC network, so that the high and low voltage difference of the output clock signal is stabilized in the ideal identification range of 0.8-2.0V. In particular, the independent double-ground interface design completely eliminates the ground interference, and the third resistance in series effectively absorbs the reflected signal, further ensuring the integrity of the signal transmission. Finally, the scheme enables the image sensor to obtain stable, clean, and time-accurate clock signals, completely solves the problems of image jitter, blur, and stripe interference caused by long-line transmission, significantly improves the image quality at the display end, and at the same time enables the same endoscope system to be compatible with different specifications of probe transmission lines, greatly enhances the adaptability and application range of the product, and provides more reliable visual protection for medical diagnosis.

[0045] The embodiments described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0046] Those skilled in the art can understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and can include more or fewer steps than those shown in the figures, or combine certain steps or different steps.

[0047] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purposes of the embodiments.

[0048] Those skilled in the art can understand that all or some of the steps in the method disclosed above, the functional modules / units in the system and the device can be implemented as software, firmware, hardware or appropriate combinations thereof.

[0049] The terms "first", "second", "third", "fourth" and the like in the description of the application and in the claims of the foregoing drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so construed can be interchanged, such that the embodiments of the application described herein can be carried out in other than the order discussed herein without departing from the scope of the application. Further, the terms "comprise" and "comprising" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, product or apparatus that comprises a list of steps or units does not necessarily comprise only those steps or units but can include other not expressly listed steps or units. The terms "include" and "have" and variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, product or apparatus that includes a list of steps or units does not necessarily include only those steps or units but can include other not expressly listed steps or units.

[0050] It should be understood that in this application, "at least one" means one or more, and "multiple" means two or more. "And / or" is used to describe the relationship between associated objects, which means that there can be three relationships, for example, "A and / or B" can mean: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0051] In several embodiments provided in the present application, it should be understood that the disclosed system and method can be implemented in other manners. For example, the system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0052] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0053] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0054] If the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer accessible storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes multiple instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program storage media.

[0055] The preferred embodiments of the embodiments of the present application are described above with reference to the accompanying drawings, but this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the rights of the embodiments of the present application.

Claims

1. A relay adjustment circuit of an endoscope, characterized by, The handle is applied to the inside of an endoscope, comprising: an input interface for connecting a control mainboard of the endoscope and receiving a first clock driving signal output by the control mainboard; a clock buffer, an input end of the clock buffer being electrically connected with the input interface; an input impedance adjusting module connected in parallel to the input end and the ground end of the clock buffer; an output matching adjusting module electrically connected with an output end of the clock buffer; an output interface electrically connected with the output matching adjusting module; wherein the input impedance adjusting module is used to adjust the input impedance of the clock buffer so that the load capacity of the clock buffer matches the driving capacity of the first clock driving signal; the clock buffer is used to receive the first clock driving signal transmitted from the input interface and adjusted by the input impedance adjusting module, and to enhance the driving capacity of the adjusted first clock driving signal to obtain a second clock driving signal and output the same; the output matching adjusting module is used to adjust the signal peak-to-peak value of the second clock driving signal to output a third clock driving signal with identifiable high and low level properties; the output interface is used to transmit the third clock driving signal to an image sensor of the endoscope.

2. The relay conditioning circuit of claim 1, wherein, Further comprising: a first analog ground interface electrically connected with the input impedance adjusting module and the ground end of the clock buffer respectively, the first analog ground interface being used to connect the control mainboard of the endoscope to ground the clock buffer and the input impedance adjusting module; a second analog ground interface electrically connected with the output matching adjusting module, the second analog ground interface being used to connect the control mainboard of the endoscope to ground the output matching adjusting module.

3. The relay conditioning circuit of claim 2, wherein, The input impedance adjusting module comprises a first resistor, one end of the first resistor being electrically connected with the input end of the clock buffer, and the other end of the first resistor being electrically connected between the ground end of the clock buffer and the first analog ground interface.

4. The relay conditioning circuit of claim 3, wherein, The value range of the first resistor is 1kΩ~10kΩ.

5. The relay conditioning circuit of claim 2, wherein, The output matching adjusting module comprises a second resistor and a first capacitor; one end of the second resistor is electrically connected with the output end of the clock buffer, and the other end of the second resistor is electrically connected with the output interface; a first end of the first capacitor is electrically connected between the second resistor and the output end of the clock buffer, or a first end of the first capacitor is electrically connected between the second resistor and the output interface; a second end of the first capacitor is electrically connected with the second analog ground interface.

6. The relay conditioning circuit of claim 5, wherein, The value range of the second resistor is 10Ω~1.5KΩ, and the value range of the first capacitor is 10pf~200pf.

7. The relay conditioning circuit of claim 2, wherein, Further comprising: a third resistor connected in series between the output matching adjusting module and the output interface, the third resistor being used to absorb the corresponding reflected signal of the image sensor transmitted through the output interface.

8. The relay conditioning circuit of claim 1, wherein, The working voltage of the clock buffer is equal to the working voltage of the image sensor, and the input / output frequency of the clock buffer is greater than the frequency of the first clock driving signal.

9. The relay conditioning circuit of claim 8, wherein, The working voltage of the clock buffer is 3.3v.

10. An endoscope characterized by comprising: The endoscope comprises: a handle, the handle comprising a control end interface circuit, a detection end interface circuit, a relay adjustment circuit of the endoscope according to any one of claims 1 to 9, an input interface in the relay adjustment circuit being electrically connected to the control end interface circuit, and an output interface in the relay adjustment circuit being electrically connected to the detection end interface circuit; a control mainboard, the control mainboard being connected to the control end interface circuit through a transmission line, and the control mainboard being configured to transmit a first clock driving signal to the handle; a probe, the probe comprising an image sensor, and the image sensor being connected to the detection end interface circuit through a transmission line; the image sensor being configured to receive a third clock driving signal obtained after signal enhancement by the relay adjustment circuit, and perform endoscope image acquisition based on the third clock driving signal.

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