Manufacturing method of semiconductor device
By adding wet etching and secondary dielectric filling steps after chemical mechanical polishing of the metal gate, the problem of metal residue caused by interlayer dielectric filling voids is solved, the chip yield is improved and the short circuit risk is eliminated, which is suitable for semiconductor device manufacturing.
Patent Information
- Application Number
- CN202511066060.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-07
AI Technical Summary
In advanced semiconductor processes, metal residue caused by filling voids in the interlayer dielectric can lead to short-circuit defects, affecting chip electrical performance and production yield.
By adding a localized wet etching and secondary dielectric filling step after standard metal gate chemical mechanical polishing, metal residues are removed and the aspect ratio is reduced. A void-free dielectric layer is formed by chemical mechanical planarization grinding.
It effectively overcomes the problem of metal residue, eliminates the risk of short circuits, improves chip yield, and ensures that device performance is not affected, making it easy to integrate into existing process flows.
Smart Images
Figure CN120916475A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, and particularly relates to a manufacturing method of semiconductor device. BACKGROUND
[0002] With the continuous development of semiconductor technology, the feature size of integrated circuits continues to shrink in order to pursue higher performance, lower power consumption and lower manufacturing cost. In order to achieve this goal, semiconductor processes continue to evolve to more advanced and smaller feature size technology nodes. In this process of size reduction, in order to ensure the electrical performance of the device, the width of the transistor key structure is usually maintained, while the spacing between different structures is reduced.
[0003] However, this design brings new process challenges. Specifically, when forming isolation between structures such as gates, it is necessary to fill the interlayer dielectric (usually silicon oxide) in a very small spacing. Due to the reduction of the spacing, the aspect ratio of the area to be filled is significantly increased. When using methods such as chemical vapor deposition for interlayer dielectric deposition, the high aspect ratio makes it difficult for the dielectric material to perfectly fill the bottom and sidewall, so that defects such as voids or seams are easily formed in the interlayer dielectric.
[0004] In subsequent manufacturing processes, such as in the post-gate process, the surface of the interlayer dielectric containing voids is first planarized by chemical mechanical polishing, which may expose the voids inside the interlayer dielectric to the wafer surface. When the dummy gate is removed and the metal gate (such as aluminum) is deposited, the metal will not only fill the pre-designed gate trench, but also fill the voids exposed.
[0005] When the metal layer after deposition is subjected to metal gate chemical mechanical polishing to remove excess metal on the surface, the metal filled in the tiny voids is difficult to be effectively removed due to the protection of the surrounding dielectric, thereby forming metal residues. This unintended metal residue can act as a conductor and may form an electrical connection between adjacent conductive structures, resulting in a short circuit defect, which will seriously affect the electrical performance, reliability and final production yield of the chip.
[0006] Therefore, how to effectively overcome the problem of metal residues caused by voids in the interlayer dielectric filling in advanced process nodes is a technical problem that needs to be solved by those skilled in the art. SUMMARY
[0007] The technical problem to be solved by the present application is to provide a manufacturing method of semiconductor device which can overcome the problem of metal residues caused by voids in the interlayer dielectric filling in advanced semiconductor processes, to avoid device short circuit and improve production yield.
[0008] To achieve the above object and other related objects, the present application provides a method for manufacturing a semiconductor device, comprising:
[0009] Step one, providing a semiconductor structure, the semiconductor structure having a metal residue formed in a first interlayer dielectric;
[0010] Step two, wet etching the semiconductor structure to remove the metal residue and a portion of the first interlayer dielectric, thereby forming a recess on the semiconductor structure;
[0011] Step three, depositing a second interlayer dielectric in the recess to fill the recess; and
[0012] Step four, planarizing the second interlayer dielectric.
[0013] Preferably, in step one, the metal residue is formed due to a void formed in the first interlayer dielectric being filled with metal during metal gate deposition and failing to be removed in subsequent metal gate chemical mechanical polishing.
[0014] Preferably, in step two, by removing a portion of the first interlayer dielectric, the aspect ratio of subsequent deposition process is reduced.
[0015] Preferably, the material of the first interlayer dielectric comprises silicon oxide.
[0016] Preferably, the material of the second interlayer dielectric comprises silicon oxide.
[0017] Preferably, the material of the metal residue is aluminum or aluminum alloy.
[0018] Preferably, in step four, the method of polishing is chemical mechanical planarization.
[0019] As described above, the method for manufacturing a semiconductor device of the present application has the following beneficial effects:
[0020] The method for manufacturing a semiconductor device of the present application, by adding a local wet etching and a secondary dielectric filling step after standard metal gate chemical mechanical polishing, is simple to implement and easy to integrate into existing process flow. This method not only effectively overcomes the problem of filling voids caused by device pitch shrinkage, but also fundamentally eliminates metal residues caused by voids, eliminates potential short circuit risk, and significantly improves chip yield. In addition, this method only makes local adjustments to the current layer process, does not negatively affect the previous and subsequent processes, and ensures that the device performance is not affected. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1A flow chart of a semiconductor device manufacturing method according to an embodiment of the present application is shown in FIG. 1.
[0022] Figure 2 A cross-sectional view of a semiconductor structure before a wet etching step according to a manufacturing method of an embodiment of the present application is shown in FIG. 2.
[0023] Figure 3 A cross-sectional view of a semiconductor structure after a wet etching step according to a manufacturing method of an embodiment of the present application is shown in FIG. 3. Figure 2
[0024] A cross-sectional view of a semiconductor structure after a second ILD is deposited on the structure according to a manufacturing method of an embodiment of the present application is shown in FIG. 4. Figure 4 Figure 3 A cross-sectional view of a semiconductor structure after a planarization step according to a manufacturing method of an embodiment of the present application is shown in FIG. 5.
[0025] Figure 5 A cross-sectional view of a final structure after a planarization step according to a manufacturing method of an embodiment of the present application is shown in FIG. 6. Figure 4 DETAILED DESCRIPTION
[0026] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is to be understood that the terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting, since the scope of the present application will be limited only by the appended claims.
[0027] Referring to FIG. 1, Figure 1 the present application provides a semiconductor device manufacturing method, comprising at least:
[0028] Step 1, referring to FIG. 2, Figure 2 a semiconductor structure is provided, which has metal residues 103 formed in a first ILD 101;
[0029] In some embodiments, the semiconductor structure can be a wafer structure that has undergone partial front-end-of-line (FEOL) processing. Specifically, the semiconductor structure can include a substrate (e.g., a silicon substrate) and a plurality of transistors formed on the substrate. The transistors are electrically isolated by shallow trench isolation (STI) structures. When the semiconductor structure is provided, dummy gates of the transistors have been removed, and deposition of metal gates 102 and a first chemical mechanical polishing (CMP) have been completed. Thus, a plurality of metal gate 102 structures are formed on channel regions of the transistors. A key feature of the semiconductor structure is that there are metal residues 103 in the first ILD 101 between two adjacent metal gate 102 structures.
[0030] In some embodiments, the metal residue 103 is formed due to a void formed in the first ILD 101 being filled with metal during the deposition of the metal gate 102 and failing to be removed during the subsequent chemical mechanical polishing of the metal gate 102. In advanced process nodes, the aspect ratio of in-pitch fill has become prevalent due to the scaling down of feature size, and is one of the key factors affecting chip yield.
[0031] In some embodiments, the material of the metal residue 103 is aluminum or aluminum alloy. It is noted that the metal here can also be other known materials.
[0032] In some embodiments, the material of the first ILD 101 includes silicon oxide, or low-k material such as carbon-doped silicon oxide (also known as organosilicate glass), fluorinated silicate glass, etc. for reducing parasitic capacitance.
[0033] In step two, the semiconductor structure is subjected to wet etching to remove the metal residue 103 and a portion of the first ILD 101, thereby forming a recess in the semiconductor structure, forming a structure as shown in FIG. 2B. Figure 3 The wet etching step can precisely remove the thin layer of ILD that carries the metal residue 103, so that the encapsulated metal residue 103 loses support and is removed together, thereby eliminating the residue that causes the risk of short circuit from the root.
[0034] In some embodiments, the etching solution used in the wet etching can be a solution containing hydrofluoric acid. By precisely controlling the etching time or solution concentration, the removal depth of the first ILD 101 can be controlled to ensure that the metal residue 103 is completely removed while not causing excessive damage to adjacent structures.
[0035] In some embodiments, in step two, by removing a portion of the first ILD 101, not only is the defect removed, but the aspect ratio of the subsequent deposition process is also actively reduced, creating a favorable process window for subsequent high-quality void-free filling, significantly improving the stability of the process.
[0036] In step three, a second ILD 104 is deposited in the recess to fill the recess, forming a structure as shown in FIG. 2C. Figure 4 and
[0037] In some embodiments, the material of the second ILD 104 includes silicon oxide, or low-k material such as carbon-doped silicon oxide, fluorinated silicate glass, etc. Using the same or similar material as the first ILD 101 can ensure good interface bonding properties and consistent electrical and physical properties, thereby ensuring the long-term reliability of the device.
[0038] In some embodiments, the method of depositing the second interlayer dielectric 104 can employ plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD), which have excellent filling capability. In other embodiments, to achieve even better seamless filling, flowable chemical vapor deposition (Flowable CVD) can be employed, which deposits a dielectric film layer with a certain flowability before solidification, and is able to completely fill into the bottom and corners of the recess, and then solidify into a dense dielectric layer through heat treatment or plasma treatment. Since the recess formed in step two has a lower aspect ratio, the deposition in this step is able to achieve high-quality filling without voids and seams, and completely solves the problem of metal residue 103 caused by original void defects.
[0039] Step four, planarization grinding of the second interlayer dielectric 104, to form a structure as shown in Figure 5 , usually the grinding stops at the surface of the metal gate 102.
[0040] In some embodiments, in step four, the method of grinding is chemical mechanical planarization grinding. Employing chemical mechanical planarization grinding is able to achieve global planarization effect, and restore the wafer surface to be flat, providing an ideal substrate for subsequent interconnection line and other process steps.
[0041] In summary, the semiconductor device manufacturing method proposed in the present application, by adding a local wet etching and a secondary dielectric filling step after the standard metal gate chemical mechanical polishing, the implementation method is simple and easy to integrate into the existing process flow. This method not only effectively overcomes the problem of filling voids caused by device pitch shrinkage, but also fundamentally eliminates the metal residue caused by voids, eliminates the potential risk of short circuit, and significantly improves the yield of chips. In addition, this method only makes local adjustments to the layer process, does not have a negative impact on the previous and subsequent processes, and can ensure that the device performance is not affected.
[0042] It should be noted that the diagrams provided in the present embodiment only illustrate the basic concept of the present application in a schematic manner, and only show the components related to the present application in the diagrams, rather than the number, shape and size of the components when actually implemented. The actual implementation of each component can be arbitrarily changed in terms of type, number and proportion, and the layout pattern of the components can also be more complex.
[0043] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.
Claims
1. A method of manufacturing a semiconductor device, characterized by, At least comprising: Step one, providing a semiconductor structure having a metal residue formed in a first interlayer dielectric; Step two, wet etching the semiconductor structure to remove the metal residue and a portion of the first interlayer dielectric to form a recess on the semiconductor structure; Step three, depositing a second interlayer dielectric in the recess to fill the recess; and Step four, planarizing the second interlayer dielectric.
2. The method of manufacturing a semiconductor device according to claim 1, wherein: In step one, the metal residue is formed due to a void formed in the first interlayer dielectric being filled with metal during metal gate deposition and failing to be removed during subsequent metal gate chemical mechanical polishing.
3. The method of manufacturing a semiconductor device according to claim 1, wherein: In step two, by removing a portion of the first interlayer dielectric, aspect ratio of subsequent deposition process is reduced.
4. The method of manufacturing a semiconductor device according to claim 1, wherein: Material of the first interlayer dielectric includes silicon oxide.
5. The method of manufacturing a semiconductor device according to Claim 1, wherein: Material of the second interlayer dielectric includes silicon oxide.
6. The method of manufacturing a semiconductor device according to Claim 1, wherein: Material of the metal residue is aluminum or aluminum alloy.
7. The method of manufacturing a semiconductor device according to Claim 1, wherein: In step four, the method of polishing is chemical mechanical planarization polishing.