Method for manufacturing an x-ray sensor panel, x-ray sensor panel and x-ray detector

Abstract

The application discloses a preparation method of an X-ray sensor panel, an X-ray sensor panel and an X-ray detector, and relates to the technical field of semiconductors.The preparation method comprises the following steps: forming a first conductive layer on a substrate, so as to use the first conductive layer as a thin film transistor gate of the X-ray sensor panel; the substrate comprises a panel image detection area and a metal cross-line area; forming a gate insulating layer on the first conductive layer; forming a semiconductor layer on the gate insulating layer, and the semiconductor layer is distributed in the panel image detection area and the metal cross-line area; the material of the semiconductor layer is amorphous silicon or indium gallium zinc oxide; forming a second conductive layer on the semiconductor layer, so as to use the second conductive layer as a thin film transistor source and a thin film crystal of the X-ray sensor panel.In the scheme, the semiconductor layer for enhancing the insulation performance is added between the gate insulating layer and the second conductive layer in the metal cross-line area, so that the voltage resistance performance of the metal cross-line area can be improved, the static damage can be reduced, and the overall reliability of the related device can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for fabricating an X-ray sensor panel, the X-ray sensor panel, and an X-ray detector. Background Technology

[0002] X-ray detectors are widely used in medical diagnosis, security inspection, and industrial non-destructive testing. The core component of an X-ray detector is the X-ray sensor panel, which typically includes a photoelectric conversion layer and a thin-film transistor (TFT) array. During actual detection, X-rays are converted into electrical charges by the photoelectric conversion layer and temporarily stored by the storage capacitors of the corresponding pixels of the TFTs. At this time, the TFTs are in an off state to maintain the signal. Then, under the control of peripheral circuitry, the TFTs turn on, transferring the temporarily stored charges to the signal processing module for processing, converting them into digital information, and finally integrating them to form an image reflecting the intensity of the X-rays. In this process, the TFTs act as key switches, forming a complete signal conversion and output chain together with various functional modules.

[0003] In the fabrication of X-ray detectors, preventing electrostatic damage is a crucial issue. Specifically, for thin-film transistors in X-ray sensor panels, the conductive layers in their GDL (Gate Data Line) regions are prone to breakdown and short circuits under high voltage differentials generated by electrostatic discharge. This causes the insulating layer to lose its insulating ability, creating a strong current path. This instantaneous high current, accompanied by a violent energy release, can cause physical damage to the related devices.

[0004] To address the aforementioned electrostatic damage issues, a novel method for fabricating X-ray sensor panels is urgently needed to improve the withstand voltage performance of the GDL region and enhance the overall reliability of related devices and equipment. Summary of the Invention

[0005] The purpose of this application is to provide a method for fabricating an X-ray sensor panel, which aims to solve the technical problem that the current X-ray sensor panel has weak withstand voltage performance in the GDL region and is prone to breakdown and short circuit under high voltage difference conditions generated by static electricity, thereby causing damage to related devices.

[0006] To achieve the above objectives, the X-ray sensor panel fabrication method proposed in this application includes the following steps: A first conductive layer is formed on a substrate to serve as the gate of a thin-film transistor in the X-ray sensor panel; the substrate includes a panel image detection area and a metal crossover area. A gate insulating layer is formed on the first conductive layer; A semiconductor layer is formed on the gate insulating layer, and the semiconductor layer is distributed in the panel image detection area and the metal cross-line area; the material of the semiconductor layer is amorphous silicon or indium gallium zinc oxide. A second conductive layer is formed on the semiconductor layer to serve as the source and drain of the thin-film transistor in the X-ray sensor panel.

[0007] In one embodiment, the step of forming a first conductive layer on the substrate includes: A gate molybdenum layer is deposited on the substrate by a first magnetron sputtering operation; A first gate copper layer is deposited on the gate molybdenum layer by a second magnetron sputtering operation; A second gate copper layer is deposited on the first gate copper layer by a third magnetron sputtering operation.

[0008] In one embodiment, the first magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; The second magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; The third magnetron sputtering operation uses argon as the sputtering gas.

[0009] In one embodiment, the thickness of the gate molybdenum layer is 450~550 Å, and the sputtering power of the first magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0010] In one embodiment, the thickness of the first gate copper layer is 2900~3100 Å, and the sputtering power of the second magnetron sputtering operation is 28~32kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0011] In one embodiment, the thickness of the second gate copper layer is 2900~3100 Å, and the sputtering power of the third magnetron sputtering operation is 23~27kW, and the argon flow rate is 190~210 sccm.

[0012] In one embodiment, prior to the step of forming a gate insulating layer on the first conductive layer, the method includes: The first conductive layer is subjected to hydrogen plasma treatment to remove impurities from its surface.

[0013] In one embodiment, the step of forming a gate insulating layer on the first conductive layer includes: Using silane and ammonia as reactants and nitrogen as a carrier gas, a first insulator layer and a second insulator layer are sequentially deposited on the first conductive layer via plasma-enhanced chemical vapor deposition; the second insulator layer is located between the first insulator layer and the semiconductor layer.

[0014] In one embodiment, the radio frequency power of the plasma-enhanced chemical vapor deposition operation is 19-23 kW, the silane flow rate is 5400-5600 sccm, the ammonia flow rate is 34000-36000 sccm, and the nitrogen flow rate is 89000-91000 sccm.

[0015] In one embodiment, the first insulator layer is made of silicon nitride, and the second insulator layer is made of silicon oxide.

[0016] In one embodiment, the thickness of the first insulator layer is 3400~3600 Å.

[0017] In one embodiment, the thickness of the second insulator layer is 1000~1200 Å.

[0018] In one embodiment, the step of forming a second conductive layer on the semiconductor layer includes: Source and drain molybdenum layers are deposited on the semiconductor layer by a fourth magnetron sputtering operation; the fourth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; A source / drain copper layer is deposited on the source / drain molybdenum layer by a fifth magnetron sputtering operation; the fifth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas.

[0019] In one embodiment, the thickness of the source and drain molybdenum layers is 450~550 Å, and the sputtering power of the fourth magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0020] In one embodiment, the thickness of the source and drain copper layers is 2900~3100 Å, and the sputtering power of the fifth magnetron sputtering operation is 28~32kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0021] This application also proposes an X-ray sensor panel, which is manufactured using the X-ray sensor panel fabrication method described above.

[0022] This application also proposes an X-ray detector, which includes an X-ray sensor panel as described above.

[0023] Compared with the prior art, the beneficial effects of this application are: The proposed method for fabricating an X-ray sensor panel introduces a semiconductor layer into the metal cross-line region of the X-ray sensor panel. This semiconductor layer is disposed between the gate insulating layer and the second conductive layer. This increases the distance between the first and second conductive layers, reducing the risk of breakdown and short circuits. Furthermore, the semiconductor layer protects the gate insulating layer in the metal cross-line region from the etching process in the image detection area of ​​the panel, preventing accidental etching that could thin or damage the gate insulating layer and thus avoiding a decrease in its insulation performance due to thinning. Based on this approach, the combined effect of the gate insulating layer and the semiconductor layer in the metal cross-line region enhances its insulation performance and improves its withstand voltage under high differential pressure conditions. This effectively avoids breakdown and short circuits caused by electrostatic discharge, improves the operational reliability of the X-ray sensor panel, and extends the service life of related devices. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of the metal cross-line region of an X-ray sensor panel in the prior art; Figure 2 This is a schematic diagram of the overall cross-sectional structure of an X-ray sensor panel in the prior art; Figure 3 This is a schematic flowchart of an embodiment of the method for fabricating an X-ray sensor panel according to this application; Figure 4 This is a schematic cross-sectional view of the metal cross-line region in one embodiment of the X-ray sensor panel of this application; Figure 5 This is a schematic cross-sectional view of an embodiment of the X-ray sensor panel of this application; Figure 6 A schematic cross-sectional view of the first conductive layer of an X-ray sensor panel when a two-segment corner phenomenon occurs. Figure 7 A cross-sectional structural diagram of the second conductive layer of an X-ray sensor panel when a chamfer appears. Figure 8This is a schematic cross-sectional view of the metal cross-line region in another embodiment of the X-ray sensor panel of this application.

[0026] Explanation of icon numbers: 1. Substrate; 11. Panel image detection area; 12. Metal crossover area; 2. First conductive layer; 21. Gate molybdenum layer; 22. First gate copper layer; 23. Second gate copper layer; 3. Gate insulating layer; 31. First insulator layer; 32. Second insulator layer; 4. Semiconductor layer; 5. Second conductive layer; 51. Source / drain molybdenum layer; 52. Source / drain copper layer; 6. N-type doped layer.

[0027] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0030] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0031] X-ray detectors are widely used in medical diagnosis, security inspection, and industrial non-destructive testing. The core component of an X-ray detector is the X-ray sensor panel, which typically includes a photoelectric conversion layer and a thin-film transistor (TFT) array. During actual detection, X-rays are converted into electrical charges by the photoelectric conversion layer and temporarily stored by the storage capacitors of the corresponding pixels of the TFTs. At this time, the TFTs are in an off state to maintain the signal. Then, under the control of peripheral circuitry, the TFTs turn on, transferring the temporarily stored charges to the signal processing module for processing, converting them into digital information, and finally integrating them to form an image reflecting the intensity of the X-rays. In this process, the TFTs act as key switches, forming a complete signal conversion and output chain together with various functional modules.

[0032] In the fabrication of X-ray detectors, preventing electrostatic damage is a crucial issue. Specifically, for thin-film transistors in X-ray sensor panels, the conductive layers in their GDL (Gate Data Line) regions are prone to breakdown and short circuits under high voltage differentials generated by electrostatic discharge. This causes the insulating layer to lose its insulating ability, creating a strong current path. This instantaneous high current, accompanied by a violent energy release, can cause physical damage to the related devices.

[0033] To address the aforementioned issues, this application provides a method for fabricating an X-ray sensor panel. By adding a semiconductor layer between the metal cross-lines in the GDL region to enhance insulation performance, the withstand voltage performance of the GDL region is improved, electrostatic damage is reduced, thereby enhancing the overall reliability of related devices and equipment.

[0034] Please see Figures 3 to 5 The present application scheme is shown in conjunction with references. Figure 1 and Figure 2 The prior art shown in this application, and the method for fabricating an X-ray sensor panel provided by this application, includes the following steps: A first conductive layer 2 is formed on a substrate 1 to serve as the gate of a thin-film transistor in an X-ray sensor panel; the substrate 1 includes a panel image detection area 11 and a metal cross-line area 12. A gate insulating layer 3 is formed on the first conductive layer 2; A semiconductor layer 4 is formed on the gate insulating layer 3. The semiconductor layer 4 is distributed in the panel image detection area 11 and the metal crossover area 12. The material of the semiconductor layer 4 is amorphous silicon or indium gallium zinc oxide. A second conductive layer 5 is formed on the semiconductor layer 4 to utilize the second conductive layer 5 as the source and drain of the thin-film transistor in the X-ray sensor panel.

[0035] In this embodiment, a first conductive layer 2 is first formed on the substrate 1. This first conductive layer 2 will serve as the gate of the thin-film transistor in subsequent processes. The substrate 1 is typically made of glass or a flexible material, which has good mechanical strength and thermal stability, and can withstand subsequent high-temperature processing. The surface of the substrate 1 is divided into two regions: a panel image detection area 11 (Active Area, abbreviated as AA area) and a metal crossover area 12 (Gate Data Line, abbreviated as GDL area). The panel image detection area 11 is the area where the pixel array is located and is used for image signal acquisition; the metal crossover area 12 is used to lay out gate lines and data lines to realize signal transmission and driving.

[0036] Before forming the first conductive layer 2 on the substrate 1, the surface of the substrate 1 usually needs to be cleaned to remove impurities such as dust, oil, and organic matter, ensuring the adhesion and film quality of subsequent film layers. The cleaning process can be ultrasonic cleaning, plasma cleaning, chemical cleaning, etc., and the specific method can be determined according to the material of the substrate 1 and the process requirements.

[0037] To improve conductivity and reliability, the first conductive layer 2 is typically made of a metallic material, such as molybdenum (Mo), copper (Cu), or aluminum (Al). The material of the first conductive layer 2 can be a single metal layer or a composite metal layer, such as a molybdenum layer, a copper layer, an aluminum layer, or a combination thereof. The first conductive layer 2 can be formed using physical vapor deposition (PVD) processes, such as magnetron sputtering, thermal evaporation, or electron beam evaporation, or using chemical vapor deposition (CVD) processes, such as plasma-enhanced chemical vapor deposition (PECVD). By controlling the deposition process parameters, the film thickness and quality can be precisely controlled.

[0038] After the first conductive layer 2 is formed, it can be patterned to form the desired gate pattern. The patterning process typically includes photolithography and etching steps; specifically, firstly, photoresist is coated on the surface of the first conductive layer 2, and the pattern on the mask is transferred to the photoresist through exposure and development processes; then, wet etching or dry etching processes are used to remove the corresponding areas on the first conductive layer 2 that are not protected by the photoresist to form the preset gate pattern; finally, the remaining photoresist is removed to complete the patterning process.

[0039] After the patterning of the first conductive layer 2 is completed, a gate insulating layer 3 should be formed on the side of the first conductive layer 2 facing away from the substrate 1. The function of the gate insulating layer 3 is to isolate the gate from the subsequently formed semiconductor layer 4 and the second conductive layer 5 to prevent short circuits. The material of the gate insulating layer 3 is usually a material with good insulating properties, such as silicon nitride (SiNx) or silicon oxide (SiO2). In this embodiment, the material of the gate insulating layer 3 can be a single insulating material layer or a composite insulating material layer. The gate insulating layer 3 can be formed by chemical vapor deposition (CVD) processes, such as plasma-enhanced chemical vapor deposition (PECVD). By controlling the deposition process parameters, the film thickness and quality can be precisely controlled, thereby obtaining a gate insulating layer 3 with high density and good insulating properties.

[0040] After the gate insulating layer 3 is formed, it can be patterned to form the required insulating layer pattern, so as to accurately define the formation areas of the semiconductor layer 4 and the second conductive layer 5 (source / drain) in subsequent processes, ensuring the normal functioning of the device. The patterning process of the gate insulating layer 3 typically includes photolithography and etching steps; specifically, firstly, photoresist is coated on the surface of the gate insulating layer 3, and the pattern on the mask is transferred to the photoresist through exposure and development processes; then, wet etching or dry etching processes are used to remove the corresponding areas on the gate insulating layer 3 that are not protected by photoresist to form the preset insulating layer pattern; finally, the remaining photoresist is removed to complete the patterning process.

[0041] After patterning the gate insulating layer 3, a semiconductor layer 4 needs to be formed on the side of the gate insulating layer 3 facing away from the first conductive layer 2. The semiconductor layer 4 is made of amorphous silicon (a-Si) or indium gallium zinc oxide (IGZO). Amorphous silicon has good electrical properties and stability, making it suitable for traditional thin-film transistor devices; indium gallium zinc oxide has high electron mobility and low leakage current characteristics, making it suitable for high-performance thin-film transistor devices. The method for forming the semiconductor layer 4 can be selected according to the material type. When amorphous silicon is used for the semiconductor layer 4, plasma-enhanced chemical vapor deposition (PECVD) is preferred; when indium gallium zinc oxide is used, solution processing or sputtering is preferred.

[0042] After the semiconductor layer 4 is fabricated, a second conductive layer 5 needs to be formed on the side of the semiconductor layer 4 facing away from the gate insulating layer 3 to serve as the source and drain of the thin-film transistor. To improve conductivity and reliability, the second conductive layer 5 is typically made of a metallic material, such as molybdenum (Mo), copper (Cu), or aluminum (Al). In this embodiment, the material of the second conductive layer 5 can be a single metal layer or a composite metal layer, such as a molybdenum layer, a copper layer, an aluminum layer, or a combination thereof. The second conductive layer 5 can be formed using physical vapor deposition (PVD) processes, such as magnetron sputtering, thermal evaporation, or electron beam evaporation, or using chemical vapor deposition (CVD) processes, such as plasma-enhanced chemical vapor deposition (PECVD). By controlling the deposition process parameters, the film thickness and quality can be precisely controlled.

[0043] After the second conductive layer 5 is formed, it can be patterned to form the desired source and drain patterns. The patterning process typically includes photolithography and etching steps; specifically, firstly, photoresist is coated on the surface of the second conductive layer 5, and the pattern on the mask is transferred to the photoresist through exposure and development processes; then, wet etching or dry etching processes are used to remove the corresponding areas on the second conductive layer 5 that are not protected by the photoresist to form the preset source and drain patterns; finally, the remaining photoresist is removed to complete the patterning process.

[0044] It should be noted that, compared to Figure 1 and Figure 2 In the prior art shown, the semiconductor layer is only disposed in the panel image detection area. In this embodiment, the semiconductor layer 4 is distributed in the panel image detection area 11 and the metal crossover area 12. In the panel image detection area 11, the main function of the semiconductor layer 4 is to form a conductive channel to realize the switching function of the thin film transistor. However, in the metal crossover area 12, the function of the semiconductor layer 4 is different. Specifically, the metal crossover area 12 is usually used to lay gate lines and data lines. Under the high voltage difference generated by static electricity, the first conductive layer 2 and the second conductive layer 5 in this area are prone to breakdown and short circuit, that is, the gate insulating layer 3 is broken down, causing the first conductive layer 2 and the second conductive layer 5 to be electrically connected and resulting in a short circuit problem. To address this issue, a semiconductor layer 4 is also provided in the metal crossover region 12 in this embodiment. On one hand, the semiconductor layer 4 in the metal crossover region 12 increases the distance between the first conductive layer 2 and the second conductive layer 5, thereby reducing the risk of breakdown and short circuit. On the other hand, the semiconductor layer 4 in the metal crossover region 12 can also protect the gate insulating layer 3 of the metal crossover region 12, preventing the gate insulating layer 3 of the metal crossover region 12 from being affected by the etching process in the panel image detection area 11, and avoiding the gate insulating layer 3 of the metal crossover region 12 from being over-etched and thinned, thereby avoiding the decrease in its insulation performance due to the thinning of the gate insulating layer 3.

[0045] Specifically, during the fabrication of the X-ray sensor panel, the panel image detection area 11 needs to undergo an etching operation to form the source and drain of the thin-film transistor in the second conductive layer 5. However, this etching process not only etches the material of the panel image detection area 11, but may also adversely affect the metal crossover area 12 adjacent to the panel image detection area 11, causing the gate insulating layer 3 of the metal crossover area 12 to be accidentally etched at the same time. If the gate insulating layer 3 of the metal crossover area 12 is over-etched, it will become thinner or even damaged, resulting in a decrease in the insulation capacity of the gate insulating layer 3, which is prone to breakdown and short circuit under the high voltage difference generated by static electricity. To this end, this embodiment introduces a semiconductor layer 4 in the metal crossover area 12. The semiconductor layer 4 covers the gate insulating layer 3 of the metal crossover area 12, which can effectively block the accidental etching of the gate insulating layer 3 of the metal crossover area 12 caused by the etching operation of the panel image detection area 11, and prevent the gate insulating layer 3 from being over-etched and becoming thinner or damaged. Thus, through the combined action of the gate insulating layer 3 and the semiconductor layer 4 of the metal crossover region 12, the insulation performance of the metal crossover region 12 can be enhanced, and the withstand voltage of the metal crossover region 12 under high voltage difference conditions can be improved, thereby effectively avoiding the breakdown and short circuit problem caused by electrostatic discharge.

[0046] Therefore, this embodiment introduces a semiconductor layer 4 into the metal cross-line region 12 of the X-ray sensor panel. The semiconductor layer 4 is disposed between the gate insulating layer 3 and the second conductive layer 5. This increases the distance between the first conductive layer 2 and the second conductive layer 5, reducing the risk of breakdown and short circuit. Furthermore, the semiconductor layer 4 protects the gate insulating layer 3 of the metal cross-line region 12 from the etching process in the panel image detection area 11, preventing accidental etching that could thin or damage the gate insulating layer 3 and thus avoiding a decrease in its insulation performance due to thinning. Based on this solution, the combined effect of the gate insulating layer 3 and the semiconductor layer 4 in the metal cross-line region 12 enhances its insulation performance and improves its withstand voltage under high voltage differential conditions. This effectively avoids breakdown and short circuit problems caused by electrostatic discharge, improves the operational reliability of the X-ray sensor panel, and extends the service life of related devices.

[0047] like Figure 4 and Figure 5 As shown, an N-type doped layer 6 is also disposed between the semiconductor layer 4 and the second conductive layer 5. The N-type doped layer 6 is used to reduce the contact resistance between the semiconductor layer 4 and the second conductive layer 5, so that a good ohmic contact is formed between the semiconductor layer 4 and the second conductive layer 5.

[0048] In one embodiment, refer to Figure 3 and Figure 8The step of forming a first conductive layer 2 on substrate 1 includes: A gate molybdenum layer 21 is deposited on substrate 1 by a first magnetron sputtering operation; A first gate copper layer 22 is deposited on the gate molybdenum layer 21 by a second magnetron sputtering operation; The second gate copper layer 23 is formed by depositing on the first gate copper layer 22 through a third magnetron sputtering operation.

[0049] Specifically, magnetron sputtering is a physical vapor deposition (PVD) technique. Its basic principle is to ionize an inert gas in a vacuum environment under the influence of an electric field to form plasma. Ions in the plasma are accelerated by the electric field and bombard the target surface, causing target atoms or molecules to be sputtered and deposited on the substrate 1 to form a thin film. Magnetron sputtering introduces a magnetic field onto the target surface, which can effectively improve plasma density and sputtering efficiency, reduce deposition temperature, and improve the uniformity and density of the film. In this embodiment, the first, second, and third magnetron sputtering operations can be performed in a vacuum chamber with a pressure of 10~50 mTorr.

[0050] In this embodiment, the gate molybdenum layer 21 (Mo), as the bottom layer of the first conductive layer 2, is in direct contact with the substrate 1. Its main function is to provide good adhesion and barrier properties. Molybdenum has a high melting point and good chemical stability, which can effectively prevent copper atoms in the subsequent copper layer from diffusing into the substrate 1, thereby avoiding device performance degradation caused by copper diffusion. In addition, the molybdenum layer can maintain structural stability during high-temperature processes, ensuring the deposition quality of subsequent film layers.

[0051] After the gate molybdenum layer 21 is fabricated, a first gate copper layer 22 (Cu) needs to be deposited on the side of the gate molybdenum layer 21 facing away from the substrate 1. Copper has excellent conductivity, which can significantly reduce gate resistance and improve signal transmission speed. However, the adhesion between copper and the substrate 1 is poor. If the copper layer is deposited directly on the substrate 1, it is easy to cause film peeling or poor adhesion. Therefore, a gate molybdenum layer 21 needs to be introduced below the first gate copper layer 22 as a transition layer, which can effectively improve the adhesion and stability of the first gate copper layer 22.

[0052] After the first gate copper layer 22 is fabricated, a second gate copper layer 23 (Cu) needs to be deposited on the side of the first gate copper layer 22 facing away from the gate molybdenum layer 21. The introduction of the second gate copper layer 23 can further reduce the gate resistance and improve the conductivity. At the same time, by forming two copper layers (i.e., the first gate copper layer 22 and the second gate copper layer 23) through segmented deposition, the film structure can be optimized, the internal stress of the film layer can be reduced, and the density and uniformity of the film layer can be improved. In addition, segmented deposition can also better control the film thickness and avoid film defects caused by excessive thickness in a single deposition.

[0053] Specifically, since the first conductive layer 2 adopts a molybdenum / copper composite structure, during the subsequent wet etching of the first conductive layer 2 to form a preset gate pattern, the etching rates of molybdenum and copper in the same etchant are different. The etching rate of molybdenum is higher than that of copper, and wet etching is isotropic. This easily leads to the lateral etching degree of the lower gate molybdenum layer 21 being greater than that of the upper copper layer, thus forming a pattern on the first conductive layer 2 as shown in the image. Figure 6 The two-segment angle phenomenon shown can lead to an excessively steep upper portion of the first conductive layer 2, resulting in tip discharge and causing a short circuit between the first conductive layer 2 and the second conductive layer 5. To address this issue, this embodiment employs the segmented coating process described above during the deposition of the first conductive layer 2. Specifically, during the formation of the first gate copper layer 22 and the second gate copper layer 23, the coating quality of the upper second gate copper layer 23 can be reduced by adjusting the coating process parameters. This enhances the lateral etching capability of the etchant on the sidewalls of the second gate copper layer 23, making the lateral etching degree of the sidewalls of the first conductive layer 2 more consistent at various heights. This effectively improves the two-segment angle phenomenon and avoids short circuits caused by tip discharge.

[0054] In one embodiment, refer to Figure 3 and Figure 8 The first magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas. The second magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; The third magnetron sputtering operation uses argon as the sputtering gas.

[0055] In magnetron sputtering, the gases typically used are divided into two categories: sputtering gases and reactive gases. Sputtering gases are generally inert gases, such as argon (Ar), whose main function is to generate plasma and provide ions to bombard the target material, thereby achieving the sputtering and deposition of target atoms. Reactive gases are gases that can chemically react with the sputtered target atoms, such as nitrogen (N2) and oxygen (O2). The introduction of reactive gases can react with target atoms to form compound films, such as nitrides and oxides, thereby improving the properties of the film, such as increasing the film's density, hardness, adhesion, and corrosion resistance.

[0056] Specifically, in the first and second magnetron sputtering operations, argon gas, as the sputtering gas, provides a stable plasma environment, enabling target atoms (i.e., molybdenum and copper) to be effectively sputtered and deposited on the surface of substrate 1 to form a gate molybdenum layer 21 and a first gate copper layer 22. Simultaneously, an appropriate amount of nitrogen gas is introduced as a reactant gas in both operations, reacting with the sputtered metal atoms to form metal nitrides. The formation of these metal nitrides refines the grain size of the film, making the film structure more compact and uniform. This improves the hardness, toughness, and adhesion of the gate molybdenum layer 21 and the first gate copper layer 22, optimizes the stress state of the film, reduces defects and porosity, and enhances its density and stability.

[0057] In the third magnetron sputtering operation, only argon gas is used as the sputtering gas, and nitrogen gas is not introduced. This is because the third magnetron sputtering operation is used to deposit the second gate copper layer 23, which is located on top of the first conductive layer 2. During the operation of the thin-film transistor, the second gate copper layer 23 serves as the gate electrode, requiring a voltage to be applied to control the formation of the conductive channel. In other words, the conductivity of the second gate copper layer 23 directly affects the transmission efficiency and response speed of the gate signal. Therefore, it is necessary to prioritize ensuring the conductivity of the second gate copper layer 23. While introducing nitrogen gas can increase the density of the film, it also forms copper nitride, leading to an increase in film resistivity and thus adversely affecting conductivity. Therefore, nitrogen gas is not introduced in the third magnetron sputtering operation to ensure that the conductivity of the second gate copper layer 23 is not negatively affected.

[0058] In this embodiment, by supplying nitrogen gas in the first and second magnetron sputtering operations, the density of the gate molybdenum layer 21 and the first gate copper layer 22 can be increased. This increased density slows down the lateral etching rate of the etchant on the lower gate molybdenum layer 21 and the first gate copper layer 22, making the lateral etching degree of the sidewall of the first conductive layer 2 more consistent at each height position. This avoids the two-segment corner phenomenon caused by the etchant's lateral etching degree on the lower side of the first conductive layer 2 being significantly greater than that on the upper side, thus effectively avoiding short circuit problems caused by tip discharge.

[0059] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the gate molybdenum layer 21 is 450~550 Å, and the sputtering power of the first magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0060] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the first gate copper layer 22 is 2900~3100 Å, and the sputtering power of the second magnetron sputtering operation is 28~32kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0061] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the second gate copper layer 23 is 2900~3100 Å, and the sputtering power of the third magnetron sputtering operation is 23~27kW, and the argon flow rate is 190~210 sccm.

[0062] Specifically, in the first magnetron sputtering operation, the thickness range of the gate molybdenum layer 21 is set to 450~550 Å, preferably 500 Å. This thickness range fully considers the blocking performance, adhesion performance, and consumable cost of the molybdenum layer. If the thickness is too thin, the blocking effect may be insufficient, and it may not be able to effectively prevent the diffusion of copper atoms. If the thickness is too thick, it may increase the stress of the film layer, affect the adhesion of subsequent film layers, and also lead to an increase in the amount of molybdenum target material used, resulting in increased costs. The sputtering power range of the first magnetron sputtering operation is 28~32kW, preferably 30kW. If the sputtering power is too low, the target atom sputtering rate will be low, the film deposition rate will be too slow, the film density will be low, and it will be easier to etch. If the sputtering power is too high, the sputtered atom energy will be too high, and the atom migration ability on the film surface will be too strong, resulting in a loose film structure, increased defects, and decreased uniformity. The argon flow rate ranges from 240 to 260 sccm, preferably 250 sccm; the nitrogen flow rate ranges from 90 to 110 sccm, preferably 100 sccm. The gas flow rate affects the density and properties of the plasma, which in turn affects the sputtering effect and the film quality. When the gas flow rate is too high, the gas will dilute the plasma, thereby reducing the sputtering rate and the film deposition rate. When the flow rate is too low, the plasma density is insufficient, and the number of ions bombarding the target will decrease, which is not conducive to the uniform deposition of the film.

[0063] In the second magnetron sputtering operation, the thickness of the first gate copper layer 22 is set to be in the range of 2900~3100 Å, preferably 3000 Å. This thickness range ensures that the first gate copper layer 22 has sufficient conductivity, while avoiding increased film stress, decreased adhesion, and increased target cost due to excessive film thickness. The sputtering power of the second magnetron sputtering operation is in the range of 28~32 kW, preferably 30 kW; the argon flow rate is in the range of 240~260 sccm, preferably 250 sccm; and the nitrogen flow rate is in the range of 90~110 sccm, preferably 100 sccm. Similar to the first magnetron sputtering operation, the above parameters are set to obtain a dense, uniform, and well-adhered first gate copper layer 22.

[0064] In the third magnetron sputtering operation, the thickness of the second gate copper layer 23 is set to 2900~3100 Å, preferably 3000 Å. This thickness range is similar to that of the first gate copper layer 22, which can balance the conductivity and structural stability of the second gate copper layer 23, while avoiding excessive etching solution usage due to excessive film thickness. The sputtering power range of the third magnetron sputtering operation is 23~27 kW, preferably 25 kW. This sputtering power range is lower than that of the first and second magnetron sputtering operations. This can appropriately reduce the density of the second gate copper layer 23, increase the etching rate of the etching solution on the second gate copper layer 23 located above the first conductive layer 2, and make the lateral etching degree of the sidewall of the first conductive layer 2 more consistent at various height positions, so as to improve the two-corner phenomenon and avoid short circuit problems caused by tip discharge. At the same time, the lower density can reduce the etching difficulty, making it easier to etch the preset gate pattern on the second gate copper layer 23. The argon flow rate for the third magnetron sputtering operation is in the range of 190~210 sccm, preferably 200 sccm, so as to balance the deposition rate and film quality of the second gate copper layer 23.

[0065] As can be seen, by rationally setting the range of parameters involved in the magnetron sputtering operation, the above embodiments can obtain a first conductive layer 2 that meets the preset requirements in terms of conductivity, density, adhesion, and uniformity, while taking into account the deposition rate and consumable cost.

[0066] In one embodiment, refer to Figure 3 and Figure 8 Prior to the step of forming the gate insulating layer 3 on the first conductive layer 2, the method includes: The first conductive layer 2 is subjected to hydrogen plasma treatment to remove impurities from the surface of the first conductive layer 2.

[0067] Referring to the foregoing embodiments, during the etching process of the source and drain of the panel image detection area 11, the gate insulating layer 3 of the metal cross-line area 12 is also affected by etching, resulting in the thinning of the gate insulating layer 3 and a decrease in its insulation capability. Based on this problem, in this embodiment, before forming the gate insulating layer 3 on the first conductive layer 2, the first conductive layer 2 is treated with hydrogen plasma (H2Plasma). The high-energy particles in the plasma can impact and remove minute foreign matter, organic residues, and some oxides from the surface of the first conductive layer 2, while also activating the surface of the first conductive layer 2. This can subsequently improve the adhesion and film quality of the gate insulating layer 3 on the first conductive layer 2, reduce interface defects, prevent film peeling, and thus indirectly improve the insulation performance of the gate insulating layer 3, reducing the probability of breakdown and short circuit problems.

[0068] In one embodiment, refer to Figure 3 and Figure 8The step of forming a gate insulating layer 3 on the first conductive layer 2 includes: Using silane and ammonia as reactants and nitrogen as a carrier gas, a first insulator layer 31 and a second insulator layer 32 are sequentially deposited on the first conductive layer 2 via plasma-enhanced chemical vapor deposition. The second insulator layer 32 is located between the first insulator layer 31 and the semiconductor layer 4.

[0069] In one embodiment, refer to Figure 3 and Figure 8 The radio frequency power of plasma-enhanced chemical vapor deposition operation is 19~23kW, the silane flow rate is 5400~5600 sccm, the ammonia flow rate is 34000~36000 sccm, and the nitrogen flow rate is 89000~91000 sccm.

[0070] In one embodiment, refer to Figure 1 The first insulator layer 31 is made of silicon nitride, and the second insulator layer 32 is made of silicon oxide.

[0071] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the first insulator layer 31 is 3400~3600 Å.

[0072] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the second insulator layer 32 is 1000~1200 Å.

[0073] This embodiment employs plasma-enhanced chemical vapor deposition (PECVD) with silane (SiH4) and ammonia (NH3) as reactants and nitrogen (N2) as carrier gas. A first insulator layer 31 and a second insulator layer 32 are sequentially deposited on the first conductive layer 2. This process can improve the insulation performance and withstand voltage of the gate insulating layer 3.

[0074] Specifically, silicon nitride has stronger density and barrier properties, making it suitable as the material for the first insulator layer 31 near the first conductive layer 2. It can effectively block the diffusion of metal ions and prevent breakdown and short circuits. Silicon oxide has better interface properties, making it suitable as the material for the second insulator layer 32 near the semiconductor layer 4. It can reduce interface defects and improve device stability. By setting the gate insulating layer 3 as the above-mentioned double-layer structure, the overall density and interface stability of the gate insulating layer 3 can be effectively improved.

[0075] In plasma-enhanced chemical vapor deposition (PECVD), parameters such as radio frequency (RF) power and gas flow rate have a significant impact on film quality. Insufficient RF power leads to incomplete decomposition of reactant gases, slow film deposition rates, and insufficient density. Higher RF power provides more energy, making reactant gas molecules more readily decompose and react, thus increasing the amount of film-forming material reaching the surface of the corresponding material layer and accelerating film growth. However, excessively high RF power may cause overly vigorous reactions, resulting in excessively rapid film growth and problems such as loose film structure and increased defects. Appropriate control of gas flow rate helps stabilize the plasma environment and ensure uniform film deposition.

[0076] Based on the above considerations, in a preferred embodiment, the radio frequency power of the plasma-enhanced chemical vapor deposition operation is 21 kW, the silane flow rate is 5500 sccm, the ammonia flow rate is 35000 sccm, and the nitrogen flow rate is 90000 sccm. The thickness range of the first insulator layer 31 is preferably 3500 Å, and the thickness range of the second insulator layer 32 is preferably 1100 Å. By optimizing the above parameters, the deposition time of the gate insulating layer 3 can be extended, the deposition rate can be slowed down, and the density and thickness of the gate insulating layer 3 can be improved, thereby improving the insulation performance and protection capability of the gate insulating layer 3.

[0077] In one embodiment, refer to Figure 3 and Figure 8 The step of forming a second conductive layer 5 on semiconductor layer 4 includes: Source and drain molybdenum layers 51 are deposited on semiconductor layer 4 by a fourth magnetron sputtering operation; the fourth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas. A source / drain copper layer 52 is deposited on the source / drain molybdenum layer 51 by a fifth magnetron sputtering operation; the fifth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas.

[0078] In this embodiment, the source / drain molybdenum layer 51 (Mo), serving as the bottom layer of the second conductive layer 5, directly contacts the semiconductor layer 4. Its main function is to provide good adhesion and barrier properties. Molybdenum has a high melting point and good chemical stability, effectively preventing copper atoms from diffusing into the gate insulating layer 3 in subsequent copper layers, thereby avoiding device performance degradation due to copper diffusion. Furthermore, the molybdenum layer maintains structural stability during high-temperature processing, ensuring the deposition quality of subsequent film layers.

[0079] After the source / drain molybdenum layer 51 is fabricated, a source / drain copper layer 52 (Cu) needs to be deposited on the side of the source / drain molybdenum layer 51 facing away from the semiconductor layer 4. Copper has excellent conductivity, which can significantly reduce the resistance of the source and drain electrodes and improve the signal transmission speed. However, the adhesion between copper and the semiconductor layer 4 is poor. If the copper layer is deposited directly on the semiconductor layer 4, it is easy to cause film peeling or poor adhesion. Therefore, a source / drain molybdenum layer 51 needs to be introduced below the source / drain copper layer 52 as a transition layer, which can effectively improve the adhesion and stability of the source / drain copper layer 52.

[0080] Specifically, since the second conductive layer 5 adopts a molybdenum / copper composite structure, during the subsequent wet etching of the second conductive layer 5 to form the preset source and drain patterns, the etching rates of molybdenum and copper in the same etching solution differ. The etching rate of molybdenum is higher than that of copper, and wet etching is isotropic. This easily leads to a greater lateral etching degree of the lower source / drain molybdenum layer 51 than that of the upper source / drain copper layer 52, resulting in the formation of patterns such as... Figure 7 The undercut phenomenon shown may weaken the blocking performance of the source-drain molybdenum layer 51, making it easier for copper atoms in the source-drain copper layer 52 to diffuse to the gate insulating layer 3 below. This can easily cause a short circuit under high voltage difference generated by static electricity.

[0081] To address the aforementioned issues, based on the scheme of this embodiment, in the fourth and fifth magnetron sputtering operations, argon gas is used as the sputtering gas to provide a stable plasma environment, enabling target atoms (i.e., molybdenum and copper) to be effectively sputtered and deposited on the surface of semiconductor layer 4 to form source / drain molybdenum layer 51 and source / drain copper layer 52. Simultaneously, an appropriate amount of nitrogen gas is introduced as a reactive gas in the fourth and fifth magnetron sputtering operations, which can react with the sputtered metal atoms to form metal nitrides. The formation of these metal nitrides can refine the grain size of the film layer, making the film structure more compact and uniform, thereby improving the hardness, toughness, adhesion, and other properties of the source / drain molybdenum layer 51, optimizing the stress state of the film layer, reducing defects and porosity, and improving its density and stability. With the increased density of the source and drain molybdenum layer 51, the resistance of the source and drain molybdenum layer 51 to the etching solution can be enhanced, thereby slowing down the lateral etching rate of the etch solution on the sidewalls of the source and drain molybdenum layer 51. This makes the lateral etching degree of the sidewalls of the second conductive layer 5 more consistent at various height positions, which can effectively improve the chamfering phenomenon, enhance the blocking ability of the source and drain molybdenum layer 51, and avoid short circuit problems caused by excessive diffusion of copper atoms.

[0082] In one embodiment, refer to Figure 3 and Figure 8The thickness of the source and drain molybdenum layer 51 is 450~550 Å, and the sputtering power of the fourth magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0083] In one embodiment, refer to Figure 3 and Figure 8 The thickness of the source and drain copper layer 52 is 2900~3100 Å, and the sputtering power of the fifth magnetron sputtering operation is 28~32kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm.

[0084] Specifically, in the fourth magnetron sputtering operation, the thickness range of the source and drain molybdenum layers 51 is set to 450~550 Å, preferably 500 Å. This thickness range fully considers the blocking performance, adhesion performance, and consumable cost of the molybdenum layer. If the thickness is too thin, the blocking effect may be insufficient, and it may not be able to effectively prevent the diffusion of copper atoms. If the thickness is too thick, it may increase the stress of the film layer, affect the adhesion of subsequent film layers, and also lead to an increase in the amount of molybdenum target material used, resulting in increased costs. The sputtering power range of the fourth magnetron sputtering operation is 28~32kW, preferably 30kW. If the sputtering power is too low, the target atom sputtering rate will be low, the film deposition rate will be too slow, the film density will be low, and it will be easier to etch. If the sputtering power is too high, the sputtered atom energy will be too high, and the atom migration ability on the film surface will be too strong, resulting in a loose film structure, increased defects, and decreased uniformity. The argon flow rate ranges from 240 to 260 sccm, preferably 250 sccm; the nitrogen flow rate ranges from 90 to 110 sccm, preferably 100 sccm. The gas flow rate affects the density and properties of the plasma, which in turn affects the sputtering effect and the film quality. When the gas flow rate is too high, the gas will dilute the plasma, thereby reducing the sputtering rate and the film deposition rate. When the flow rate is too low, the plasma density is insufficient, and the number of ions bombarding the target will decrease, which is not conducive to the uniform deposition of the film.

[0085] In the fifth magnetron sputtering operation, the thickness of the source / drain copper layer 52 is set to a range of 2900–3100 Å, preferably 3000 Å. This thickness range ensures that the source / drain copper layer 52 has sufficient conductivity, while avoiding increased film stress, decreased adhesion, and increased target cost due to excessive film thickness. The sputtering power range of the fifth magnetron sputtering operation is 28–32 kW, preferably 30 kW; the argon flow rate range is 240–260 sccm, preferably 250 sccm; and the nitrogen flow rate range is 90–110 sccm, preferably 100 sccm. Similar to the fourth magnetron sputtering operation, the above parameters are set to obtain a source / drain copper layer 52 with uniformity, good adhesion, and good conductivity.

[0086] The above embodiments, by rationally setting the range of parameters involved in the magnetron sputtering operation, can obtain a second conductive layer 5 that meets preset requirements in terms of conductivity, density, adhesion, and uniformity while taking into account deposition rate and consumable cost. Specifically, the density of the source / drain molybdenum layer 51 is improved based on the above parameter settings, thus enhancing its resistance to etching solution and slowing down the lateral etching rate of the sidewalls of the source / drain molybdenum layer 51. This effectively improves the chamfering phenomenon and avoids short circuits caused by excessive diffusion of copper atoms. Furthermore, based on the above parameter settings, the thickness of the source / drain molybdenum layer 51 is increased compared to existing solutions. This further enhances the blocking ability of the source / drain molybdenum layer 51 and effectively shields the sharp electric field formed at the source and drain, preventing short circuits caused by sharp discharge.

[0087] This application also provides an X-ray sensor panel; please refer to [link / reference]. Figure 4 , Figure 5 and Figure 8 The X-ray sensor panel is manufactured using the X-ray sensor panel fabrication method described in any of the above embodiments.

[0088] Since the X-ray sensor panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments. That is, a semiconductor layer 4 is introduced into the metal cross-line region 12 of the X-ray sensor panel. The semiconductor layer 4 is disposed between the gate insulating layer 3 and the second conductive layer 5. On the one hand, the semiconductor layer 4 can increase the distance between the first conductive layer 2 and the second conductive layer 5, thereby reducing the risk of breakdown and short circuit. On the other hand, the semiconductor layer 4 can also protect the gate insulating layer 3 of the metal cross-line region 12, so that the gate insulating layer 3 of the metal cross-line region 12 is not affected by the etching process in the panel image detection area 11, and the gate insulating layer 3 of the metal cross-line region 12 is prevented from being accidentally etched and thinned or damaged, thereby avoiding the decrease in its insulation performance due to the thinning of the gate insulating layer 3. Based on the above scheme, the insulation performance of the metal crossover region 12 can be enhanced by the combined action of the gate insulating layer 3 and the semiconductor layer 4, thereby improving the withstand voltage of the metal crossover region 12 under high voltage differential conditions, effectively avoiding the breakdown and short circuit problem caused by electrostatic discharge, improving the operational reliability of the X-ray sensor panel, and extending the service life of related devices.

[0089] This application also provides an X-ray detector, which includes the X-ray sensor panel of any of the above embodiments.

[0090] The beneficial technical effects of the X-ray detector provided in this embodiment are the same as those of the X-ray sensor panel in the above embodiments, and will not be repeated here.

[0091] It should be noted that the preparation method of the X-ray sensor panel, other contents of the X-ray sensor panel and X-ray detector disclosed in this application can be found in the prior art, and will not be repeated here.

[0092] The above are merely optional embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for fabricating an X-ray sensor panel, characterized in that, The method for preparing the X-ray sensor panel includes the following steps: A first conductive layer is formed on a substrate to serve as the gate of a thin-film transistor in the X-ray sensor panel; the substrate includes a panel image detection area and a metal crossover area. A gate insulating layer is formed on the first conductive layer; A semiconductor layer is formed on the gate insulating layer, and the semiconductor layer is distributed in the panel image detection area and the metal cross-line area; the material of the semiconductor layer is amorphous silicon or indium gallium zinc oxide. A second conductive layer is formed on the semiconductor layer to serve as the source and drain of the thin-film transistor in the X-ray sensor panel. The step of forming a first conductive layer on the substrate includes: Argon gas was used as the sputtering gas and nitrogen gas was used as the reaction gas. A gate molybdenum layer was deposited on the substrate by a first magnetron sputtering operation. Argon gas was used as the sputtering gas and nitrogen gas was used as the reaction gas. A first gate copper layer was deposited on the gate molybdenum layer by a second magnetron sputtering operation. Argon gas is used as the sputtering gas, and a second gate copper layer is deposited on the first gate copper layer through a third magnetron sputtering operation; The thickness of the gate molybdenum layer is 450~550 Å, and the sputtering power of the first magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm; and / or, the thickness of the first gate copper layer is 2900~3100 Å, and the sputtering power of the second magnetron sputtering operation is 28~32 kW, the argon flow rate is 240~260 sccm, and the nitrogen flow rate is 90~110 sccm; and / or, the thickness of the second gate copper layer is 2900~3100 Å, and the sputtering power of the third magnetron sputtering operation is 23~27 kW, and the argon flow rate is 190~210 sccm; And / or, the step of forming a second conductive layer on the semiconductor layer includes: Source and drain molybdenum layers are deposited on the semiconductor layer by a fourth magnetron sputtering operation; the fourth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; A source / drain copper layer is deposited on the source / drain molybdenum layer by a fifth magnetron sputtering operation; the fifth magnetron sputtering operation uses argon as the sputtering gas and nitrogen as the reaction gas; The thickness of the source / drain molybdenum layer is 450-550 Å, and the sputtering power of the fourth magnetron sputtering operation is 28-32 kW, the argon flow rate is 240-260 sccm, and the nitrogen flow rate is 90-110 sccm; and / or, the thickness of the source / drain copper layer is 2900-3100 Å, and the sputtering power of the fifth magnetron sputtering operation is 28-32 kW, the argon flow rate is 240-260 sccm, and the nitrogen flow rate is 90-110 sccm.

2. The method for preparing an X-ray sensor panel according to claim 1, characterized in that, Prior to the step of forming a gate insulating layer on the first conductive layer, the method includes: The first conductive layer is subjected to hydrogen plasma treatment to remove impurities from the surface of the first conductive layer. And / or, the step of forming a gate insulating layer on the first conductive layer includes: Using silane and ammonia as reactants and nitrogen as a carrier gas, a first insulator layer and a second insulator layer are sequentially deposited on the first conductive layer via plasma-enhanced chemical vapor deposition; the second insulator layer is located between the first insulator layer and the semiconductor layer.

3. The method for preparing an X-ray sensor panel according to claim 2, characterized in that, The radio frequency power of the plasma-enhanced chemical vapor deposition operation is 19~23kW, the silane flow rate is 5400~5600sccm, the ammonia flow rate is 34000~36000sccm, and the nitrogen flow rate is 89000~91000sccm. And / or, the material of the first insulator layer is silicon nitride, and the material of the second insulator layer is silicon oxide; And / or, the thickness of the first insulator layer is 3400~3600 Å; And / or, the thickness of the second insulator layer is 1000~1200 Å.

4. An X-ray sensor panel, characterized in that, The X-ray sensor panel is manufactured using the X-ray sensor panel manufacturing method as described in any one of claims 1 to 3.

5. An X-ray detector, characterized in that, The X-ray detector includes the X-ray sensor panel as described in claim 4.

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