Multiplication delay locked loop

Abstract

The present disclosure relates to a device (2) that receives an input signal (In) and delivers an output signal (Out). The oscillator (RO) comprises a first circuit (MUX1) and an inverting gate (INV); the first circuit (MUX1) sends an input signal on its output (112) when the first signal (Sel ') is in a first state, otherwise the first circuit (MUX1) sends an output signal on its output (112); an inverting gate (INV) is connected in series between the first circuit and the output (102). The loop (Loop3) has a second circuit (MUX2) identical to the first circuit; the second circuit (MUX2) sends an output signal on its output (112) regardless of the state of the first signal. When the first signal is in the first state, the loop controls a delay between the input signal and the delayed signal (Ind) based on a delay between the output of the first circuit and the output of the second circuit. Another loop (Loop2) receives the delayed signal and controls the delay in the inverting gate.

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