An active disturbance method for parallel detection of an off-grid inverter

Abstract

The application provides an active disturbance method for parallel detection of an unconnected line inverter, and each inverter is used for realizing recognition of single-machine operation or parallel operation of the current system by injecting a specific harmonic disturbance signal at a specific moment. When the inverter is in single-machine operation, if the disturbance amount is injected, the output voltage changes greatly and the inductance current changes little; when the inverter is in parallel operation, the output voltage changes little with the injection of the disturbance amount, and the inductance current changes greatly with the injection of the disturbance amount. According to the characteristics, the current system is discriminated to be in single-machine operation or parallel operation. Experiments show that the method can effectively identify the current state of the system by each inverter, for example, when the bus is detected to be in parallel, the fault inverter can directly disconnect the connection with the bus; when the bus is detected to be in single-machine operation, the fault inverter can connect the grid voltage to the bus, so as to ensure the continuous power supply of the load and meet higher requirements and complex operation environment.

Description

Technical Field

[0001] This invention belongs to the field of power electronic and electrical equipment and electrical engineering technology, specifically relating to an active disturbance detection method for parallel inverters without tie lines. Background Technology

[0002] In inverter (uninterruptible power supply) systems, multiple inverters are typically operated in parallel to improve power capacity and reliability. The inverter system uses parallel inverters to distribute power evenly across the load, ensuring continuous power supply to critical loads even in the event of a single inverter failure. However, in a parallel architecture without communication interconnection, each inverter cannot directly obtain the operating status of other inverters, making it difficult for the system to determine whether it is currently in a multi-in-parallel or single-industry independent operation mode.

[0003] Traditional parallel inverter systems without interconnection lines have significant problems: when an inverter fails, if it is not possible to accurately determine whether there are other inverters online on the bus, it may lead to serious consequences. If it is mistakenly judged to be operating independently (when there are actually still inverters connected in parallel), the faulty unit will disconnect directly and connect the grid voltage to the load bus, causing electrical conflicts to occur on the remaining inverters on the bus. If it is mistakenly judged to be operating in parallel (when there are actually no other inverters), the disconnection of the faulty unit will cause a power outage to the load.

[0004] Currently, there are two main technical approaches to detecting this problem: one is to use a solution with interconnected communication to monitor the system status through real-time data exchange; the other is to use a unified grid-connected switch for centralized control. While the interconnected solution can accurately obtain the status of each inverter through the communication network, it significantly increases system complexity and cost-effectiveness, and reduces system reliability. The unified switch-based solution, on the other hand, suffers from poor flexibility and difficulty in expansion, making it difficult to adapt to the development needs of distributed power systems. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this invention discloses an active disturbance detection method for parallel inverters without tie lines.

[0006] Based on the differences between inverter parallel operation systems and stand-alone operation systems, it was found that when the inverter is operating as a stand-alone unit, if a specific disturbance is injected, both the inverter's output voltage and inductor current will change with the disturbance. However, when the inverter is operating in parallel, the inverter's output voltage does not change with the disturbance, while the inductor current still changes with the disturbance. Therefore, based on these characteristics, an active disturbance detection method for parallel inverters without tie lines was designed.

[0007] The technical solution of this invention is: an active disturbance detection method for parallel inverters without tie lines, comprising the following steps:

[0008] S1. At different times specified by each inverter, the operating inverters first need to inject waveforms according to the inverter address and use logic algorithms to realize specific disturbance waveforms; the AC output bus provides a unified time reference signal for each inverter operating in parallel.

[0009] S2. Inject a high-frequency disturbance voltage into the modulation voltage, and use a notch filter and FIR filter based on the second-order generalized integrator SOGI to filter the output voltage and inductor current and extract the injected disturbance characteristics.

[0010] S3. When the inverter is running as a standalone unit, if a disturbance is injected, the output voltage will change significantly while the inductor current will change little. However, when running in parallel, the output voltage will change little with the injection of disturbance, while the inductor current will change significantly. The difference can be determined by comparing the disturbance in the inductor current with the disturbance in the output voltage.

[0011] Furthermore, in step S1, the AC output bus is first used to provide a unified time reference signal for each inverter operating in parallel. Phase-locked loop (PLL) is then applied to the AC output bus, and the zero-crossing point of the PLL output angle is used as the unified disturbance start position. Based on the uniqueness of each parallel inverter's address, the offset of the disturbance time is determined from the inverter address. Assuming the disturbance start position is 0, the disturbance start and end positions for each inverter are shown in the formula:

[0012]

[0013] In the formula, posMax is the number of sampling points contained in one cycle of the parallel bus voltage, n is the maximum number of inverters that may be in operation, DISGAP is the disturbance waveform period, addr is the inverter address, posstart is the inverter disturbance start position, and posend is the inverter disturbance end position. When a phase-locked loop is introduced, posMax is the number of sampling points between the two zero-crossing points of the phase angle of the phase-locked loop.

[0014] Furthermore, in step S1, during high-frequency disturbance within the disturbance period, a positive signal with a duration of DISGAP / 2 sampling periods is first continuously injected, followed by a negative signal with a duration of DISGAP / 2 sampling periods, as shown in the following formula:

[0015]

[0016] In the formula, S DIS k is the amount of disturbance injected. DIS The gain coefficient for the disturbance is 0.01, which is selected in this invention. DIS For a square wave, b k The value is half a cycle of the disturbance waveform, and Loc is the position of the phase-locked loop tracking bus.

[0017] Furthermore, in step S2, the output voltage and inductor current are filtered and injected disturbance characteristics are extracted using a notch filter based on SOGI and an FIR filter. First, the fundamental component of the output voltage and inductor current waveforms needs to be filtered out using the notch filter, as expressed by the following formula:

[0018]

[0019] In the formula, ω n This is the fundamental angular frequency, which we choose in this paper as 100π. k is the proportionality coefficient, and U... DIS_SOGI and I DIS_SOGI Here, U and I represent the extracted harmonic components, respectively, and the inverter output voltage and inductor current, respectively. To improve the accuracy of harmonic extraction, cascaded notch filters are used to reduce the influence of the fundamental component. Then, the disturbance waveform within the harmonic is extracted using a pre-defined FIR filter to obtain the injected specific waveform. The formula for the FIR filter is shown below:

[0020]

[0021] In the formula, y[n] is the current output, x[nk] is the k-th input in the past, and c k Here are the FIR filter coefficients, and N is the filter order.

[0022] Furthermore, in step S3, after filtering by the filter, the output voltage and inductor current disturbances are U and U, respectively. hary_FIR and i hary_FIR Considering that this disturbance can be positive or negative, if we directly apply U... hary_FIR and i hary_FIR Determining the threshold is quite complex, so the abs() function is used to set the threshold for U. hary_FIR and i hary_FIR For positive values, the formula is as follows:

[0023]

[0024] To prevent misjudgment, the disturbance quantity U is detected. hary_FIR and i hary_FIR During the process, the MAX function is used to measure U hary_FIR and i hary_FIR The formula for finding the maximum value is shown below:

[0025]

[0026] When the test is completed, the U at this time hary_max and i hary_max These are the maximum values ​​during the detection process, and at this moment, U... hary_max and ihary_max The determination value can be obtained by performing division operations on each part, and the formula is shown below:

[0027]

[0028] i in standalone operation hary_max The change is small, while U hary_max Significant changes; and when running in parallel, U hary_max The change is small, while i hary_max Significant changes occur, at which point the data... Decision By selecting an appropriate threshold, it is possible to determine whether the inverter is operating in stand-alone mode or in parallel mode, thus adapting to higher requirements and more complex operating environments.

[0029] The appropriate threshold mentioned above is:

[0030]

[0031] In the formula, Z THR To determine the threshold, ω hary Z is the disturbance frequency, L is the filter inductance, 1.5 in the formula is a compromise value selected considering multiple inverters connected in parallel, and Z Lmin This is the minimum impedance for the inverter to operate, and this minimum impedance is determined by the inverter's rated voltage and rated current.

[0032] Compared with existing technologies, the beneficial effects are:

[0033] 1) The output voltage and inductor current are filtered using a notch filter based on SOGI to remove the fundamental component of the signal. However, the signal after filtering still contains certain high-order harmonics, so it is necessary to filter out the high-order harmonics using an FIR filter.

[0034] 2) Compared with the traditional method of discrimination through communication lines, the present invention does not require a communication line, and has higher practicality and economy.

[0035] 3) Compared with the simple inverter shutdown and bypass strategy, the present invention only needs to inject a certain amount of disturbance to identify the state of the system and thus take appropriate operating strategies, which has higher flexibility and economy. Attached Figure Description

[0036] Figure 1 Here is a block diagram of the parallel inverter operating system in this invention; (a) Schematic diagram of normal operation in single-unit mode; (b) Schematic diagram of disturbance injection in single-unit mode.

[0037] Figure 2 The diagram shows the parallel operation system of the parallel inverters in this invention; (a) schematic diagram of normal operation in parallel mode; (b) schematic diagram of normal operation in parallel mode.

[0038] Figure 3 This is a control block diagram of the parallel inverter system in this invention;

[0039] Figure 4 This is a control block diagram for extracting characteristic perturbation quantities in this invention;

[0040] Figure 5 This is the simulation output waveform of two single-phase inverters connected in parallel in this invention;

[0041] Figure 6 This refers to the amount of disturbance injected in each cycle of this invention;

[0042] Figure 7 This is the simulation output waveform of a single inverter in this invention;

[0043] Figure 8 This refers to the amount of disturbance injected into a single machine in each cycle of this invention. Detailed Implementation

[0044] The present invention will now be described in detail with reference to specific embodiments and accompanying drawings:

[0045] This invention first distinguishes the timing of the injected disturbance for each inverter based on the phase-locked loop, sampling frequency, and fundamental frequency of the waveform. The waveform of the injected disturbance can be modified according to the specific situation. The sampling frequency in this experiment is 5kHz and the fundamental frequency is 50Hz. Therefore, a standard sine wave is modulated for 100 cycles. The injected waveform used in this invention consists of 8 consecutive positive cycles plus 8 consecutive negative cycles, requiring a total of 16 sampling cycles.

[0046] After the waveform is injected, it is filtered step by step by a notch filter based on SOGI to remove the fundamental components of the output voltage and current. Then, the disturbance in the output voltage and inductor current is extracted by an FIR filter. The FIR filter for the inductor current is an 8th order filter, and the FIR filter for the output voltage is also an 8th order filter.

[0047] Meanwhile, during the extraction process, after filtering, the signal is evaluated by taking the positive value and maximum value using absolute and maximum value functions. Finally, the judgment value is obtained by the ratio of output current to output voltage. This judgment value satisfies the condition that it is relatively small in stand-alone operation and relatively large in parallel operation.

[0048] The specific process is as follows:

[0049] The following judgment criteria are proposed:

[0050] When an inverter operates as a standalone unit, the injected disturbance causes a large change in output voltage and a small change in inductor current. However, when operating in parallel, the output voltage changes less with the injection of disturbance, while the inductor current changes significantly. According to... Figure 1 As shown in (a) and (b), the inverter is in stand-alone operation mode. At this time, the output of inverter 1 after disturbance is:

[0051]

[0052] Where U0 and I are the output voltage and inductor current of the inverter, respectively, U dis I dis These represent the amount of disturbance added; U g and i L These are the fundamental components of the output voltage and the inductor current, respectively. Extracting the disturbance from equation (3) separately yields:

[0053]

[0054] At this time, the current disturbance I dis With voltage disturbance U sh Proportional to the load Z L Capacitive X c and resistance to X L Inversely proportional. Usually X c Z L The value is much greater than the resistance to X. L The value of X is therefore the main factor affecting the disturbance current. c Z L The value of this value determines the magnitude of the disturbance current, therefore the value of the disturbance current is relatively small. The disturbance amount U of the output voltage... dish for:

[0055]

[0056] Equation (5) ω dis Let U be the angular frequency of the disturbance. During standalone operation, the disturbance U of the output voltage... dish Approaching the disturbance quantity U Sh It is greatly affected by disturbance voltage.

[0057] according to Figure 2 As shown in (a) and (b), the inverter is in parallel operation mode. At this time, the output of inverter 1 after disturbance is still:

[0058]

[0059] Similarly, by extracting the disturbance amount from equation (6), we can obtain:

[0060]

[0061] At this time, the current disturbance I dis With voltage disturbance U sh Proportional to the bus load Z LThe capacitive reactance X of inverter 1 and inverter 2 c Anti-X L Inversely proportional to the output voltage disturbance U dish for:

[0062]

[0063] Similarly, compared to the parallel connection of the load and capacitor, the filter inductance is smaller, i.e., the inductive reactance X L The smaller value, and therefore equation (8) simplifies to:

[0064]

[0065] According to equation (9), the output voltage disturbance U of the inverter during parallel operation is... dish Approximately the injected disturbance amount U dish The voltage fluctuation of the inverter output voltage will be reduced to half of that of the parallel operation. Simplifying equation (7), the disturbance of the inductor current at this time is:

[0066]

[0067] Because the filter inductance value is small, the disturbance of the inductor current is large in parallel mode.

[0068] Therefore, according to equations (9) and (10), the disturbance U of the output voltage during parallel operation can be obtained. dish Smaller, while the disturbance I of the inductor current dish The disturbance is relatively large. According to equations (4) and (5), the output voltage disturbance during stand-alone operation is approximately U. dish Equal to the injected disturbance amount U Sh The inductor current is affected by the load and capacitance, therefore the disturbance I of the inductor current... dish Smaller.

[0069] Based on the above theoretical derivation, it is first necessary to inject waveforms based on the inverter address, and utilize the characteristic that the AC output bus provides a unified time reference signal for each inverter operating in parallel to perform phase-locked loop (PLL) on the AC output bus. The zero-crossing point of the PLL output angle is used as the unified disturbance start position. Based on the uniqueness of the address of each parallel inverter, the offset of the disturbance time is determined by the inverter address. Assuming the disturbance start position is 0, the disturbance start position and end position of each inverter are as shown in formula (1):

[0070]

[0071] In the formula, posMax is the number of sampling points contained in one cycle of the parallel bus voltage, n is the maximum number of inverters that may be in operation, DISGAP is the disturbance waveform period, addr is the inverter address, posstart is the inverter disturbance start position, and posend is the inverter disturbance end position. When a phase-locked loop is introduced, posMax is the number of sampling points between the two zero-crossing points of the phase angle of the phase-locked loop.

[0072] The specific disturbance waveform is mainly implemented using logic algorithms. For example, at the disturbance moment, inverter 1 first continuously injects a positive signal with a duration of DISGAP / 2 sampling periods, and then continuously injects a negative signal with a duration of DISGAP / 2 sampling periods. The formula is as follows:

[0073]

[0074] In equation (12), S DIS k is the amount of disturbance injected. DIS The gain coefficient for the disturbance is 0.01, which is selected in this invention. DIS For a square wave, b k The value is half a cycle of the disturbance waveform, and Loc is the position of the phase-locked loop tracking bus.

[0075] The extraction process mainly includes a notch filter based on SOGI and an FIR filter. First, the fundamental components in the output voltage and inductor current waveforms need to be filtered out by the notch filter represented by equation (13):

[0076]

[0077] In the formula, ω n This is the fundamental angular frequency, which we choose in this paper as 100π. k is the proportionality coefficient, and U... DIS_SOGI and I DIS_SOGI The extracted harmonic components are represented by U and I, respectively, and the inverter output voltage and inductor current are represented by I. To improve the accuracy of harmonic extraction, cascaded notch filters are used to reduce the influence of the fundamental component. Since the fundamental component cannot be completely filtered out by using it only once, the above operation needs to be repeated to obtain harmonics with fewer fundamental components. Then, the disturbance waveform is extracted from this harmonic using a set FIR filter to obtain the specific waveform injected in steps 2 and 3. The formula for the FIR filter is shown below:

[0078]

[0079] In the formula, y[n] is the current output; x[n-k] is the k-th input in the past; c k Here, represents the FIR filter coefficients (impulse response), and N represents the filter order.

[0080] Based on the above theoretical derivation, and considering the influence of higher harmonics and interference, this invention processes the data using the max() and abs() functions. After filtering, the output voltage and inductor current disturbances are U and U, respectively. hary_FIR and i hary_FIR Considering that this disturbance can be positive or negative, if we directly apply U... hary_FIR and i hary_FIR Determining the threshold is quite complex, so the abs() function is used to set the threshold for U. hary_FIR and i hary_FIR Take positive values. The formula is as follows:

[0081]

[0082] To prevent misjudgment, the disturbance quantity U is detected. hary_FIR and i hary_FIR During the process, the MAX function is used to measure U hary_FIR and i hary_FIR Take the maximum value. The formula is as follows:

[0083]

[0084] When the test is completed, the U at this time hary_max and i hary_max These are the maximum values ​​during the detection process, and at this moment, U... hary_max and i hary_max The determination value can be obtained by performing division operations on each part, and the formula is shown below:

[0085]

[0086] Data Decision This actually reflects the impedance of the high-frequency disturbance current path. It is a low-impedance path when operating in parallel and a high-impedance path when operating alone. Based on this characteristic, the midpoint between the impedance of the low-impedance path and the impedance of the high-impedance path can be selected as the judgment threshold. The judgment threshold is defined as follows:

[0087]

[0088] In equation (18), Z THR To determine the threshold, ω hary Z is the disturbance frequency, L is the filter inductance, and 1.5 in the formula is a compromise value selected considering multiple inverters connected in parallel. Lmin This is the minimum impedance for inverter operation. This minimum impedance is determined by the inverter's rated voltage and rated current. For a single-phase inverter... For three-phase inverters So when Z THR ≥Z LminAt this time, the inverter is in stand-alone operation mode, so when Z THR <Z Lmin At this time, the inverter is in parallel operation mode.

[0089] Figure 3 This is a control block diagram of the parallel inverter system in this invention;

[0090] Figure 4 This is a control block diagram for extracting characteristic perturbation quantities in this invention;

[0091] Figure 5 The output waveform of the parallel connection of two single-phase inverters in this invention is shown. The axis represents the time (Time(s)). The master inverter starts working at 0.1s and the slave inverter starts working at 0.5s. The output waveform shows that the parallel connection function is realized. As can be seen from the figure, switch and switch_s are the times when the inverters are connected to the bus. After the parallel connection, the flag bits isParallelState of inverter 1 and isParallelStates of inverter 2 are set to 1 at the same time, that is, it is detected that there are other inverters working on the parallel bus, which reflects the effectiveness of the strategy.

[0092] Figure 6 The perturbation amount injected in each cycle of this invention is represented by the horizontal axis, which is time (in seconds).

[0093] Figure 7 The waveform of the single inverter simulation output in this invention is shown. The horizontal axis is time (Time(s)). isParallelState and isParallelStates are the parallel detection flags of the inverter, and switch and switchs are the times when the inverter is connected to the bus. As can be seen from the figure, since inverter 2 is not connected to the bus, although inverter 1 made a misjudgment between 1s and 1.5s, the reason was caused by load change. However, after 1.5s, the load stabilized and the misjudgment disappeared.

[0094] Figure 8 This represents the amount of disturbance injected into a single machine in each cycle of this invention, with the horizontal axis representing time (S).

[0095] This invention proposes an active disturbance detection method for parallel inverters without tie lines. This method is applied to systems with multiple inverters connected in parallel. It can quickly determine whether an inverter is in stand-alone or parallel operation without relying on tie signals. This allows for accurate determination of whether the inverter bypass is activated before shutdown, avoiding situations where other operating inverters operate in grid-connected mode or fail to switch to bypass mode due to inverter shutdown and switching to bypass mode, resulting in power outages.

[0096] The specific description of the present invention above is obviously not intended to limit the scope of the invention. Any simple modifications made in accordance with the contents of the claims of the present invention should fall within the protection scope of the present invention.

Claims

1. A method for active disturbance detection in parallel operation of a tie-line-less inverter, characterized in that, Includes the following steps: S1. At different times specified by each inverter, the operating inverters first need to inject waveforms according to the inverter address and use logic algorithms to realize specific disturbance waveforms; the AC output bus provides a unified time reference signal for each inverter operating in parallel. S2. Inject a high-frequency disturbance voltage into the modulation voltage, and use a notch filter and FIR filter based on the second-order generalized integrator SOGI to filter the output voltage and inductor current and extract the injected disturbance characteristics. S3. When the inverter is running alone, if a disturbance is injected, the output voltage will change significantly while the inductor current will change little. However, when running in parallel, the output voltage will change little with the injection of disturbance, while the inductor current will change significantly. The difference can be determined by comparing the disturbance in the inductor current with the disturbance in the output voltage. In step S1, taking advantage of the AC output bus providing a unified time reference signal for each parallel-operating inverter, phase-locked loop (PLL) is applied to the AC output bus. The zero-crossing point of the PLL output angle is used as the unified disturbance start position. Based on the uniqueness of each parallel inverter address, the offset of the disturbance time is determined by the inverter address. Assuming the disturbance start position is 0, the disturbance start and end positions of each inverter are shown in the following formula: In the formula, posMax is the number of sampling points included in one cycle of the parallel bus voltage. The maximum number of inverters that can be operated. For the period of the disturbance waveform, This is the inverter address. This is the starting position of the inverter disturbance. This indicates the end position of the inverter disturbance; when a phase-locked loop (PLL) is introduced, posMax is the number of sampling points between the two zero-crossing points of the PLL's phase angle. In step S1, a specific perturbation waveform is implemented using a logic algorithm. During high-frequency perturbation within the perturbation period, the initial continuous injection time is... The positive signal of the sampling period, and the subsequent injection time is... The negative signal of the sampling period.

2. The active disturbance detection method for parallel inverters without tie lines according to claim 1, characterized in that, In step S2, a notch filter based on SOGI and an FIR filter are used to filter the output voltage and inductor current and extract the injected disturbance characteristics. First, the fundamental component in the output voltage and inductor current waveforms needs to be filtered out using the notch filter, as expressed by the following formula: In the formula, It is the fundamental angular frequency, which this paper selects. , It is a proportionality coefficient. and These are the extracted harmonic components, and These represent the inverter output voltage and inductor current, respectively. To improve the accuracy of harmonic extraction, cascaded notch filters are used to reduce the influence of the fundamental component. Then, the disturbance waveform within this harmonic is extracted using a pre-defined FIR filter to obtain the injected specific waveform. The formula for the FIR filter is shown below: In the formula, This is the current output. For the past number enter, These are the coefficients of the FIR filter. This represents the filter order.

3. The active disturbance detection method for parallel inverters without tie lines according to claim 1, characterized in that, In step S3, after filtering by the filter, the output voltage and inductor current disturbances are respectively and Considering that this disturbance can be positive or negative, if we directly apply... and Determining the threshold is quite complex, so the abs() function is used instead. and For positive values, the formula is as follows: To prevent misjudgment, when detecting disturbance quantities and During the process, the MAX function is used to... and The formula for finding the maximum value is shown below: After the test is completed, at this time and These are the maximum values ​​during the detection process, and at this moment... and The determination value can be obtained by performing division operations on each part, and the formula is shown below: When running in standalone mode Small changes, Significant changes; and when operating in parallel, Small changes, Significant changes, at this time... By selecting an appropriate threshold, it is possible to determine whether the inverter is operating in stand-alone mode or in parallel mode, thus adapting to higher requirements and more complex operating environments.

4. The active disturbance detection method for parallel inverters without tie lines according to claim 3, characterized in that, The appropriate threshold is: In the formula, For the threshold, Where is the disturbance frequency, L is the filter inductance, and 1.5 in the formula is a compromise value selected considering multiple inverters connected in parallel. This is the minimum impedance for the inverter to operate, and this minimum impedance is determined by the inverter's rated voltage and rated current.

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