Method for reading non-volatile two-terminal memory and related products

Abstract

This invention discloses a method and related products for reading non-volatile two-ended memory. The non-volatile two-ended memory includes at least one non-volatile two-ended memory cell. The circuit for reading the non-volatile two-ended memory includes a reference module, a comparison module, and a pre-charge module. The reference module includes a reference resistor. The comparison module includes a latch formed by cross-coupling a first inverter and a second inverter, and a control switch disposed between a first cross-connection and a second cross-connection of the latch. A first terminal of the non-volatile two-ended memory cell is connected to the output terminal of the first inverter via a first bit line. A first terminal of the reference resistor is connected to the output terminal of the second inverter via a second bit line. The pre-charge module is configured to pre-charge the first bit line and the second bit line. The control switch is configured to turn on and off in response to a pre-charge signal. The technical solution of this invention helps to improve the read accuracy of the memory.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor technology. More specifically, this invention relates to a method for reading non-volatile dual-ended memory and related products. Background Technology

[0002] In ReRAM, read margin refers to the difference in signal (such as voltage or current) between the high-resistance and low-resistance states that can be effectively detected by a sensitive amplifier during a read operation. The greater the difference, the more ample the read margin and the lower the risk of false reads. The distance between the low-resistance and high-resistance states of a memory cell is a crucial factor affecting ReRAM read margin; a larger distance results in a larger read margin, and a smaller distance results in a smaller read margin. In some applications, to improve memory performance in certain aspects, the distance between the high-resistance and low-resistance states of the ReRAM memory cell may be reduced, thereby decreasing the read margin and reducing read accuracy.

[0003] In view of this, the present invention provides a method and related products for reading non-volatile end-to-end memory, so as to improve the accuracy of memory read operations. Summary of the Invention

[0004] In order to at least solve one or more technical problems described in the background section above, the present invention proposes the following technical solutions and several embodiments thereof.

[0005] In a first aspect, the present invention discloses a circuit for reading a non-volatile two-way memory, the non-volatile two-way memory including at least one non-volatile two-way memory cell; the circuit includes a reference module, a comparison module, and a pre-charge module; the reference module includes a reference resistor; the comparison module includes: a latch formed by cross-coupling of a first inverter and a second inverter, and a control switch disposed between a first cross-connection and a second cross-connection of the latch; a first terminal of the non-volatile two-way memory cell is connected to the output terminal of the first inverter via a first bit line; a first terminal of the reference resistor is connected to the output terminal of the second inverter via a second bit line; the pre-charge module is configured to pre-charge the first bit line and the second bit line; the control switch is configured to turn on and off in response to a pre-charge signal.

[0006] In a second aspect, the present invention discloses a memory comprising the circuitry described in the first aspect.

[0007] In a third aspect, the present invention discloses a method for reading a non-volatile two-way memory, the non-volatile two-way memory including at least one non-volatile two-way memory cell; the method includes: cross-coupling a first inverter and a second inverter to form a latch; distributing a control switch between a first cross-connection and a second cross-connection of the latch; connecting a first terminal of the non-volatile two-way memory cell to the output terminal of the first inverter via a first bit line; connecting a first terminal of a reference resistor to the output terminal of the second inverter via a second bit line; pre-charging the first bit line and the second bit line using a pre-charge module; and switching the control switch on and off in response to a pre-charge signal.

[0008] The technical solution provided by this invention determines the data stored in the memory cell based on the relative magnitude of the reference resistor and the resistance value of the memory cell. Furthermore, by setting a control switch between the first cross connection and the second cross connection of the latch, a voltage difference is introduced between the first inverter output terminal and the second inverter output terminal after the pre-charging is completed. Moreover, the voltage difference is generated in response to the relative magnitude of the reference resistor and the resistance value of the memory cell, thereby helping to improve the read accuracy of the memory. Attached Figure Description

[0009] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 An exemplary schematic diagram of a memory according to some embodiments of the present invention is shown.

[0010] Figure 2 An exemplary structural diagram of a ReRAM memory cell in some embodiments of the present invention is shown.

[0011] Figure 3 A schematic diagram illustrating an exemplary relationship between the resistance value of the resistive switching layer and the storage state in some embodiments of the present invention is shown.

[0012] Figure 4 An exemplary structural diagram of a storage array according to some embodiments of the present invention is shown.

[0013] Figure 5 An exemplary schematic diagram of the peripheral circuitry in some embodiments of the present invention is shown.

[0014] Figure 6 An exemplary schematic diagram of a sensitive amplifier readout circuit according to some embodiments of the present invention is shown.

[0015] Figure 7An exemplary schematic diagram of a bit line signal acquisition circuit in some embodiments of the present invention is shown.

[0016] Figure 8 An exemplary schematic diagram of a sensitive amplifier readout circuit according to some embodiments of the present invention is shown.

[0017] Figure 9 An exemplary schematic diagram of a circuit for reading a non-volatile two-dimensional memory is shown in some embodiments of the present invention.

[0018] Figure 10 An exemplary structural diagram of a storage array according to some embodiments of the present invention is shown.

[0019] Figure 11 The diagram shows the current distribution of the pre-charging phase conduction control switch in some embodiments of the present invention.

[0020] Figure 12 The diagram shows the current distribution of the pre-charging phase conduction control switch in some embodiments of the present invention.

[0021] Figure 13 The diagram shows the current distribution of the pre-charging phase conduction control switch in some embodiments of the present invention.

[0022] Figure 14 An exemplary schematic diagram of a circuit for reading a non-volatile two-dimensional memory is shown in some embodiments of the present invention.

[0023] Figure 15 An exemplary schematic diagram of a circuit for reading a non-volatile two-dimensional memory is shown in some embodiments of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be understood that the terms "first," "second," etc., in the claims, specification, and drawings of this invention are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of this invention indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0026] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0027] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0028] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] Storage devices such as cache, main memory, and solid-state drives (SSDs) are core components of computing systems, and their performance and architecture directly affect the functionality of the entire system.

[0030] Figure 1 Exemplary schematic diagrams of a memory 100 according to some embodiments of the present invention are shown. For example... Figure 1 As shown, in some embodiments, the memory 100 includes a memory stack 110, peripheral circuits 120, and a communication connection 130 disposed between the memory stack 110 and the peripheral circuits 120.

[0031] The storage stack 110 is the physical carrier for actual data storage and can be obtained by three-dimensional integration technology from multiple storage arrays 111. The storage array 111 can be composed of multiple rows and columns of storage units. The storage units can include switch units and storage units. The control switch is used to control access to the storage units. The storage units can be dynamic random access memory (DRAM) storage units, static random access memory (SRAM) storage units, resistive random access memory (ReRAM) storage units, spin-transfer torque magnetoresistive random access memory (STT-MRAM) storage units, phase change memory (PCM) storage units, ferroelectric random access memory (FeRAM) storage units, or flash memory storage units.

[0032] Figure 2 Exemplary structural diagrams of ReRAM memory cells in some embodiments of the present invention are shown. For example... Figure 2 As shown, a ReRAM memory cell includes an upper electrode, a resistive switching layer, and a lower electrode. The upper and lower electrodes can be metal electrodes, such as those made of aluminum (Al), titanium (Ti), or copper (Cu). The resistive switching layer can be a metal oxide material, such as zinc oxide (ZnO), magnesium oxide (MgO), or zirconium oxide (ZrO). x Titanium oxide (TiO) x Materials include aluminum oxide (Al2O3), tantalum oxide (Ta2O5), and hafnium oxide (HfO2). The resistive switching layer can change its resistance value according to the voltage across it.

[0033] Figure 3 This diagram illustrates an exemplary relationship between the resistance value of the resistive switching layer and the storage state in some embodiments of the present invention. For example... Figure 3As shown, the positive direction of the resistance axis is the direction of increasing resistance. LR1 is the minimum resistance in the low resistance state, LR2 is the maximum resistance in the low resistance state, HR1 is the minimum resistance in the high resistance state, and HR2 is the maximum resistance in the high resistance state. Therefore, [LR1, LR2] is the low resistance state range of the resistive switching layer, and [HR1, HR2] is the high resistance state range of the resistive switching layer. In some embodiments, a high voltage pulse can be applied to the resistive switching layer, causing it to exhibit a low resistance state (LRS); in some embodiments, a low voltage pulse can be applied to the resistive switching layer, causing it to become a high resistance state (HRS). Moreover, even after the memory cell loses power, the resistive switching layer will maintain its resistance value. In a computing system, data can be represented using fixed-point numbers or floating-point numbers with multiple bits. In some embodiments, the storage array 111 uses each storage cell to store the value 0 / 1 of each bit, and multiple storage cells correspond to one data element; for example, when the storage cell is a ReRAM storage cell, the value 1 can be stored in the low resistance state of the resistive switching layer and the value 0 can be stored in the high resistance state of the resistive switching layer.

[0034] Figure 4 Exemplary structural diagrams of storage arrays according to some embodiments of the present invention are shown. For example... Figure 4 As shown, the memory array 111 consists of multiple rows and columns of memory sections, accessible via horizontal and vertical wires, commonly referred to as word lines (WL), source lines (SL), and bit lines (BL). A memory section can be deployed between two source lines and adjacent bit lines and word lines. Each memory section includes memory cells and switching units. The memory cells can be two-ended memory cells, such as ReRAM memory cells; the switching units can be metal-oxide-semiconductor field-effect transistors (MOSFETs). When using a MOSFET as a switching unit, the MOSFET's gate is connected to the word line, and the current flowing to the memory cell can be controlled by adjusting the word line voltage; the MOSFET's source is connected to the source line, and its drain is connected to the lower electrode of the memory cell. The upper electrode of the memory cell is connected to the bit line, and the switching unit can be used to control access to the memory cell.

[0035] Back Figure 1 The peripheral circuit 120 connects the storage array 111 to the external system and is responsible for coordinating the read and write operations, address encoding, signal processing and other functions of the storage array 111 to ensure the correct transmission and processing of data.

[0036] Figure 5Exemplary schematic diagrams of peripheral circuits in some embodiments of the present invention are shown. For example... Figure 5 As shown, in some embodiments, the peripheral circuit 120 includes a row multiplexer 121, a column multiplexer 122, a row address decoder 123, a read / write driver circuit 124, a control circuit 125, a column address decoder 126, a sensitive amplifier 127, and a data buffer 128. The data reading operation in the memory 100 is the process by which the peripheral circuit 120 retrieves target data from the storage array 111 based on an externally input address signal. Throughout the reading process, the control circuit 125 performs timing control and logic coordination for each step. The externally input address signal is divided into a row address and a column address, used to locate the specific storage cell where the data to be read needs to be. The row address and column address are transmitted to the row address decoder 123 and the column address decoder 126, respectively. The row address decoder 123 decodes the row address to determine the row where the target storage cell is located. The row multiplexer 121 connects the read / write driver circuit 124 to the storage array 111, enabling the read / write driver circuit 124 to activate the word line of the target storage cell. The column address decoder 126 decodes the column address to determine the column where the target storage cell is located; the column multiplexer 122 connects the sensitive amplifier 127 to the storage array 111 so that the information stored in the target storage cell can be sensed and processed by the sensitive amplifier 127, and the sensing result of the sensitive amplifier can be temporarily stored in the data buffer 128.

[0037] Figure 6 Exemplary schematic diagrams of sensitive amplifier readout circuits according to some embodiments of the present invention are shown. In these embodiments, the sensitive amplifier is connected to the bit line where the target memory cell is located, and determines the stored data of the target memory cell by detecting the signal on the bit line. Figure 6 As shown, in some embodiments, the sensitive amplifier is a comparator used to receive a bit line signal and a reference signal, and to obtain an output signal representing the stored data of the target memory cell based on the comparison result of the bit line signal and the reference signal. The bit line signal and the reference signal can be voltage or current. In some embodiments, the memory cell is a ReRAM memory cell, and the bit line signal can be expressed as a function of the resistance value of the memory cell, or in other words, the bit line signal changes in response to the resistance value of the memory cell, so that the resistance value of the memory cell can be characterized by the bit line signal; furthermore, in response to the range of values ​​of the ReRAM memory cell resistance value, the bit line signal also has a certain range of values. In some embodiments, the median or average value of the bit line signal range can be used as a reference signal to distinguish the low-resistance state and the high-resistance state of the ReRAM memory cell, thereby identifying the stored data of the memory cell.

[0038] Figure 7 Exemplary schematic diagrams of bit line signal acquisition circuits in some embodiments of the present invention are shown. For example... Figure 7As shown, in some embodiments, the memory cell is grounded through a switching unit, and the current mirror provides a fixed current I to the target memory cell through the bit line where the target memory cell is located, so that a bit line signal U in the form of voltage can be detected at one end of the target memory cell, i.e., U=IR, where R is the resistance of the target memory cell.

[0039] Figure 8 Exemplary schematic diagrams of sensitive amplifier readout circuits in some embodiments of the present invention are shown. For example... Figure 8 As shown, in some embodiments, the sensitive amplifier is a latching sensitive amplifier, including a bit-line side inverter composed of S1 and S3 and a reference-side inverter composed of S2 and S4; wherein: S1 and S2 are P-MOSFETs, and S3 and S4 are N-MOSFETs; the sources of S1 and S2 are connected to the power supply voltage of the readout circuit; the sources of S3 and S4 are grounded through S5, and S5 is an N-MOSFET; the gates of S1 and S3 are interconnected to form the input terminal of the bit-line side inverter, and the drains of S1 and S3 are interconnected to form the output terminal of the bit-line side inverter; the gates of S2 and S4 are interconnected to form the input terminal of the reference-side inverter, and the drains of S2 and S4 are interconnected to form the output terminal of the reference-side inverter. In some embodiments, the bit-line signal is connected to the output terminal of the bit-line side inverter through S6, and the reference signal is connected to the output terminal of the reference-side inverter through S7, wherein S6 and S7 are N-MOSFETs. According to the working principle of latch-type sensitive amplifiers, the larger of the bit line signal and the reference signal will cause the output potential of the inverter connected to it to quickly become high (e.g., circuit power supply voltage VDD), and the smaller of the bit line signal and the reference signal will cause the output potential of the inverter input to it to quickly become low (e.g., circuit ground voltage GROUND). For example, if the bit line signal is connected to the output of the bit line-side inverter, the output of the bit line-side inverter is OUT_1; if the reference signal is connected to the output of the reference-side inverter, the output of the reference-side inverter is OUT_2. When the bit line signal is less than the reference signal, OUT_2 quickly becomes high and OUT_1 quickly becomes low; when the bit line signal is greater than the reference signal, OUT_1 quickly becomes high and OUT_2 quickly becomes low.

[0040] In some embodiments, Figure 8 The bit line signal in the middle is through Figure 7 The circuit shown acquires the signal. In these embodiments, the bit line signal increases with the resistance of the target memory cell, so as... Figure 3Taking the diagram showing the relationship between the resistance of a memory cell and its storage state as an example, we can take the reference signal as R_Ref*I, where R_Ref∈(LR2,HR1). Therefore, when the target memory cell is in a low-impedance state, the bit line signal is less than the reference signal, OUT_1 is low and OUT_2 is high; when the target memory cell is in a high-impedance state, the bit line signal is greater than the reference signal, OUT_1 is high and OUT_2 is low. Thus, the value stored in the target memory cell can be determined based on either OUT_1 or OUT_2.

[0041] In ReRAM, read margin refers to the difference in signal (such as voltage or current) between the high-resistance and low-resistance states that can be effectively detected by a sensitive amplifier during a read operation. The greater the difference, the more ample the read margin and the lower the risk of false reads. Understandably, for the read schemes mentioned earlier, the distance between the low-resistance and high-resistance states of the memory cell is a crucial factor affecting the ReRAM read margin. This distance can be evaluated by the resistance difference between LR2 and HR1; a larger distance results in a larger read margin, and a smaller distance results in a smaller read margin. In some applications, to improve memory performance in certain aspects, the distance between the high-resistance and low-resistance states of the ReRAM memory cell may be reduced, leading to a smaller read margin and decreased read accuracy.

[0042] In order to at least partially solve one or more of the technical problems mentioned above, the present invention provides a method and related products for reading non-volatile end-to-end memory in order to improve the accuracy of memory read operations.

[0043] Figure 9 Exemplary schematic diagrams of circuits for reading non-volatile dual-ended memory according to some embodiments of the present invention are shown. Figure 9 As shown, in some embodiments, the non-volatile two-ended memory includes at least one non-volatile two-ended memory cell; the circuit includes a reference module, a comparison module, and a pre-charge module; the reference module includes a reference resistor; the comparison module includes: a latch formed by cross-coupling of a first inverter and a second inverter, and a control switch disposed between a first cross-connection and a second cross-connection of the latch; a first terminal of the non-volatile two-ended memory cell is connected to the output terminal of the first inverter via a first bit line; a first terminal of the reference resistor is connected to the output terminal of the second inverter via a second bit line; the pre-charge module is configured to pre-charge the first bit line and the second bit line; the control switch is configured to turn on and off in response to a pre-charge signal.

[0044] In some embodiments, the circuit for reading non-volatile two-way memory provided by the present invention can be implemented in the peripheral circuit 120, for obtaining the data stored in the target memory cell from the non-volatile two-way memory according to the externally input address signal.

[0045] A non-volatile two-way memory includes at least one non-volatile two-way memory cell. In some embodiments, the non-volatile two-way memory may include a memory stack, peripheral circuitry, and a communication connection between the memory stack and the peripheral circuitry. The memory stack may be obtained by three-dimensional integration of multiple memory arrays, and the memory array may be composed of multiple rows and columns of non-volatile two-way memory units. Each memory unit includes a switching unit and non-volatile two-way memory cells. The non-volatile two-way memory cells can be memory cells that store data using two electrodes and a memory material, and can retain the stored data even after power failure, such as ReRAM memory cells, STT-MRAM memory cells, FeRAM memory cells, and PCM memory cells. In the following text, the technical solution of this invention is mainly described using ReRAM memory cells as an example. For other types of non-volatile two-way memory cells, similar technical solutions can be used. The preceding text has already combined... Figure 4 This provides an implementation method for a storage array, in Figure 4 In the memory array shown, the switching unit can be a MOSFET, such as an N-MOSFET or a P-MOSFET. Another memory array implementation will be provided next.

[0046] Figure 10 Exemplary structural diagrams of storage arrays according to some embodiments of the present invention are shown. For example... Figure 10 As shown, the memory array includes word lines and bit lines. A memory section can be deployed within the area formed by two adjacent word lines and two adjacent bit lines. The memory section includes non-volatile two-ended memory cells and a selector. The selector can be a bidirectional diode-type selector or other non-linear selection devices, such as a bidirectional threshold switch (OTS) or a metal-insulator transition (MIT). The selector is used to control access to the series-connected non-volatile two-ended memory cells.

[0047] The reference module includes a reference resistor to provide a reference signal for distinguishing between low-resistance and high-resistance memory cells. In some embodiments, the resistance value of the reference resistor is determined based on the resistance range [LR1, LR2] of the low-resistance state and the resistance range [HR1, HR2] of the high-resistance state of the memory cell. For example, the resistance value of the reference resistor can be a value between (LR2, HR1).

[0048] like Figure 9 As shown, in some embodiments, the first inverter includes a first P-type field-effect transistor and a first N-type field-effect transistor. The first non-gate terminal of the first P-type field-effect transistor is connected to a pre-charge module, the second non-gate terminal of the first P-type field-effect transistor is connected to the output terminal of the first inverter, the first non-gate terminal of the first N-type field-effect transistor is connected to the output terminal of the first inverter, and the second non-gate terminal of the first N-type field-effect transistor is grounded. The second inverter includes a second P-type field-effect transistor and a second N-type field-effect transistor. The first non-gate terminal of the second P-type field-effect transistor is connected to the pre-charge module; the second non-gate terminal of the second P-type field-effect transistor is connected to the output terminal of the second inverter; the first non-gate terminal of the second N-type field-effect transistor is connected to the output terminal of the second inverter; and the second non-gate terminal of the second N-type field-effect transistor is grounded. The N-MOSFET and P-MOSFET each have three terminals: a gate terminal, a source terminal, and a drain terminal. The first non-gate terminal and the second non-gate terminal can be either the source terminal or the drain terminal. In some embodiments, the gate of the first P-type field-effect transistor and the gate of the first N-type field-effect transistor are interconnected to form the input terminal of the first inverter, and the drain of the first P-type field-effect transistor and the drain of the first N-type field-effect transistor are interconnected to form the output terminal of the first inverter; the gate of the second P-type field-effect transistor and the gate of the second N-type field-effect transistor are interconnected to form the input terminal of the second inverter, and the drain of the second P-type field-effect transistor and the drain of the second N-type field-effect transistor are interconnected to form the output terminal of the second inverter. In some embodiments, the input terminal of the first inverter is connected to the output terminal of the second inverter, and the input terminal of the second inverter is connected to the output terminal of the first inverter, thereby the first inverter and the second inverter are cross-coupled to form a latch.

[0049] It is understood that the input terminal of the first inverter is connected to the output terminal of the second inverter, thereby forming a first cross connection between the input terminal of the first inverter and the output terminal of the second inverter; the input terminal of the second inverter is connected to the output terminal of the first inverter, thereby forming a second cross connection between the input terminal of the second inverter and the output terminal of the first inverter. In some embodiments, the comparison module includes a control switch disposed between the first cross connection and the second cross connection of the latch. In these embodiments, when the control switch is turned on, the first cross connection and the second cross connection are interconnected, and the input and output terminals of the first inverter and the second inverter are at the same potential.

[0050] The first terminal of the non-volatile two-ended memory cell is connected to the input terminal of the second inverter via the first bit line, and the first terminal of the reference resistor is connected to the input terminal of the first inverter via the second bit line. Since the first inverter and the second inverter are cross-coupled to form a latch, it can also be considered that the first terminal of the non-volatile two-ended memory cell is connected to the output terminal of the first inverter via the first bit line, and the first terminal of the reference resistor is connected to the output terminal of the second inverter via the second bit line.

[0051] A precharge module is configured to precharge the first bit line and the second bit line. In some embodiments, the precharge module is connected to the power supply voltage VDD of a non-volatile two-terminal memory read circuit and uses the power supply voltage of the read circuit to precharge the first bit line and the second bit line to generate current flowing through the reference resistor and the memory cell. In some embodiments, the first non-gate terminal of a first P-type field-effect transistor is connected to the precharge module, and the first non-gate terminal of a second P-type field-effect transistor is also connected to the precharge module. Thus, the precharge module can precharge the first bit line and the second bit line through the first and second P-type field-effect transistors, and can turn the first and second P-type field-effect transistors on or off in response to precharge start and end signals.

[0052] The control switch is configured to turn on and off in response to a precharge signal. In some embodiments, when the precharge signal is on, the precharge module precharges the first and second bit lines, and the control switch is on; when the precharge signal is off, the precharge module does not precharge the first and second bit lines, and the control switch is off. Figure 9 As shown, in some embodiments, the control switch includes a first control switch and a second control switch; the first control switch is an N-MOSFET with its drain connected to a first cross-connection and its source connected to a second cross-connection; the second control switch is a P-MOSFET with its source connected to the first cross-connection and its drain connected to the second cross-connection. In some embodiments, the parameters of the first control switch and the second control switch are matched, for example, the threshold voltage, channel length, channel width, on-resistance, and span parameters of the first control switch and the second control switch are the same. In some embodiments, in response to a precharge signal being turned on, the first control switch and the second control switch are simultaneously turned on; in response to a precharge signal being turned off, the first control switch and the second control switch are simultaneously turned off.

[0053] Figure 11 The diagram shows the current distribution of the pre-charge phase conduction control switch in some embodiments of the present invention. For example... Figure 11As shown, when the control switch is on, the first cross connection and the second cross connection are interconnected, and the input and output terminals of the first inverter and the second inverter are at the same potential. Therefore, the current IPCH0 flowing through the first P-type field-effect transistor is equal to the current IPCH1 flowing through the second P-type field-effect transistor. Furthermore, when the reference resistor and the memory cell have the same resistance value, the current I_Cell flowing through the memory cell = IPCH1 = IPCH0 = the current I_Ref flowing through the reference resistor.

[0054] Figure 12 The diagram shows the current distribution of the pre-charge phase conduction control switch in some embodiments of the present invention. For example... Figure 12 As shown, when the reference resistor's resistance is greater than the memory cell's resistance, the first inverter requires a larger pre-charge current than the second inverter to raise its output to the same voltage as the second inverter's output. Therefore, it can be assumed that a portion of the current IPCH0, IPCH2, flows from the second inverter's output to the first inverter's output via the control switch. Consequently, the current flowing through the memory cell, I_Cell, is greater than the current flowing through the reference resistor, I_Ref. Furthermore, after the pre-charge is complete, the control switch is turned off, and the current flowing through the memory cell decreases instantaneously. This causes the voltage at the first inverter's output to be less than the voltage at the second inverter's output. According to the operating principle of a latching sensitive amplifier, the voltage at the first inverter's output is quickly pulled down to a low level, while the voltage at the second inverter's output is quickly pulled up to a high level.

[0055] Figure 13 The diagram shows the current distribution of the pre-charge phase conduction control switch in some embodiments of the present invention. For example... Figure 13 As shown, when the reference resistor's resistance is less than the memory cell's resistance, the first inverter requires a smaller pre-charge current than the second inverter to raise its output to the same voltage as the second inverter's output. Therefore, it can be assumed that a portion of the current IPCH1, IPCH3, flows from the first inverter's output to the second inverter's output via the control switch. Consequently, the current flowing through the memory cell, I_Cell, is less than the current flowing through the reference resistor, I_Ref. Furthermore, after the pre-charge is complete, the control switch is turned off, and the current flowing through the reference resistor decreases instantaneously. This causes the voltage at the second inverter's output to be less than the voltage at the first inverter's output. According to the operating principle of a latching sensitive amplifier, the voltage at the second inverter's output is quickly pulled down to a low level, while the voltage at the first inverter's output is quickly pulled up to a high level.

[0056] Based on the above, it can be understood that this invention, by turning on the control switch during pre-charging and turning it off after pre-charging, can generate different I_Cell and I_Ref values ​​in response to the relative values ​​of the reference resistor and the memory cell during pre-charging, and can generate different first inverter output voltages and second inverter output voltages after pre-charging. Furthermore, when the reference resistor value is less than the memory cell resistance, the first inverter output voltage is high and the second inverter output voltage is low after pre-charging; when the reference resistor value is greater than the memory cell resistance, the first inverter output voltage is low and the second inverter output voltage is high after pre-charging. Therefore, after pre-charging, the resistance of the memory cell can be determined to be greater than or less than the reference resistor value based on the first inverter output and / or the second inverter output, thereby determining whether the memory cell is in a high-resistance state or a low-resistance state, and whether the data stored in the memory cell is logic 0 or 1.

[0057] It is understood that the circuit for reading non-volatile two-terminal memory provided by the present invention determines the data stored in the memory cell based on the relative magnitude of the reference resistor and the resistance value of the memory cell. Furthermore, by setting a control switch between the first cross connection and the second cross connection of the latch, a voltage difference is introduced between the first inverter output terminal and the second inverter output terminal after the pre-charging is completed. Moreover, the voltage difference is generated in response to the relative magnitude of the reference resistor and the resistance value of the memory cell, thereby helping to improve the read accuracy of the memory.

[0058] Figure 14 Exemplary schematic diagrams of circuits for reading non-volatile dual-ended memory according to some embodiments of the present invention are shown. Figure 14 As shown, in some embodiments, the first end of the non-volatile two-terminal storage cell is connected to the output of the first inverter via a first bit line and a first load switch; the first end of the reference resistor is connected to the output of the second inverter via a second bit line and a second load switch.

[0059] Understandably, the first load switch can be used to control the connection from the memory cell to the output of the first inverter, and the second load switch can be used to control the connection from the reference resistor to the output of the second inverter. In some embodiments, both the first load switch and the second load switch are composed of parameter-matched P-MOSFETs and N-MOSFETs.

[0060] Figure 15 Exemplary schematic diagrams of circuits for reading non-volatile dual-ended memory according to some embodiments of the present invention are shown. Figure 15As shown, in some embodiments, the non-volatile two-ended memory includes a non-volatile two-ended storage section, the non-volatile two-ended storage section includes a non-volatile two-ended storage cell and a first gating switch connected in series with the non-volatile two-ended storage cell; the reference module further includes a second gating switch connected in series with a reference resistor; the first gating switch and the second gating switch are used to be turned on when reading the non-volatile two-ended storage cell.

[0061] Understandably, the first gating switch can be used to control access to the non-volatile two-terminal memory cell, and the second gating switch can be used to control access to the reference resistor. In some embodiments, the first and second gating switches are N-MOSFETs or P-MOSFETs.

[0062] In some embodiments, the reference resistor includes a polysilicon resistor.

[0063] The present invention also discloses a memory comprising the circuitry described in the preceding embodiments.

[0064] The present invention also discloses a method for reading a non-volatile two-way memory, the non-volatile two-way memory including at least one non-volatile two-way memory cell; the method includes: cross-coupling a first inverter and a second inverter to form a latch; setting a control switch between the first cross-connection and the second cross-connection of the latch; connecting a first end of the non-volatile two-way memory cell to the output of the first inverter via a first bit line; connecting a first end of a reference resistor to the output of the second inverter via a second bit line; pre-charging the first bit line and the second bit line using a pre-charge module; and switching the control switch on and off in response to a pre-charge signal.

[0065] Corresponding to the non-volatile two-terminal memory read circuit disclosed in the present invention as described above, the present invention discloses the following embodiments of the non-volatile two-terminal memory read method: In some embodiments, the method further includes: connecting a first end of a non-volatile two-terminal memory cell to the output of a first inverter via a first bit line and a first load switch; and connecting a first end of a reference resistor to the output of a second inverter via a second bit line and a second load switch.

[0066] In some embodiments, the method further includes: connecting a non-volatile two-terminal memory cell in series with a first gating switch; connecting a reference resistor in series with a second gating switch; and turning on the first gating switch and the second gating switch when reading the non-volatile two-terminal memory cell.

[0067] In some embodiments, the reference resistor includes a polysilicon resistor.

[0068] Understandably, polycrystalline silicon resistors are made of polycrystalline silicon material, and their resistance value can be precisely controlled through process adjustments, thereby improving the accuracy of the reference resistor value and the precision of the memory read circuit.

[0069] In some embodiments, the first inverter includes a first P-type field-effect transistor and a first N-type field-effect transistor; the method further includes: connecting a pre-charge module using a first non-gate terminal of the first P-type field-effect transistor; connecting the output terminal of the first inverter using a second non-gate terminal of the first P-type field-effect transistor; connecting the output terminal of the first inverter using a first non-gate terminal of the first N-type field-effect transistor; and grounding the second non-gate terminal of the first N-type field-effect transistor.

[0070] In some embodiments, the second inverter includes a second P-type field-effect transistor and a second N-type field-effect transistor; the method further includes: connecting a pre-charge module using a first non-gate terminal of the second P-type field-effect transistor; connecting the output terminal of the second inverter using a second non-gate terminal of the second P-type field-effect transistor; connecting the output terminal of the second inverter using a first non-gate terminal of the second N-type field-effect transistor; and grounding the second non-gate terminal of the second N-type field-effect transistor.

[0071] In summary, the specific functions implemented by the memory and the method for reading the non-volatile end-to-end memory provided in the embodiments of this specification can be explained in comparison with the foregoing embodiments in this specification, and can achieve the technical effects of the foregoing embodiments. Therefore, they will not be repeated here.

[0072] It should be noted that, for the sake of brevity, this invention describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this invention is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this invention, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this invention can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this invention. In addition, depending on the solution, the description of some embodiments of this invention also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this invention can also refer to the relevant descriptions of other embodiments.

Claims

1. A circuit for reading a non-volatile two-dimensional memory, the non-volatile two-dimensional memory comprising at least one non-volatile two-dimensional memory cell; characterized in that, The circuit includes a reference module, a comparison module, and a pre-charge module; The reference module includes a reference resistor; The comparison module includes: a latch consisting of a first inverter and a second inverter cross-coupled, and a control switch disposed between the first cross connection and the second cross connection of the latch; The first end of the non-volatile two-ended memory cell is connected to the output of the first inverter via the first bit line. The first end of the reference resistor is connected to the output end of the second inverter via the second bit line; The pre-charge module is configured to pre-charge the first bit line and the second bit line; The control switch is configured to introduce a voltage difference between the first inverter output and the second inverter output after precharging is complete, wherein the voltage difference is generated in response to the relative magnitude of the reference resistor and the resistance of the storage cell.

2. The circuit according to claim 1, characterized in that: The first end of the non-volatile two-terminal storage unit is connected to the output of the first inverter via the first bit line and the first load switch. The first end of the reference resistor is connected to the output of the second inverter via the second bit line and the second load switch.

3. The circuit according to claim 1, characterized in that: The non-volatile two-terminal memory includes a non-volatile two-terminal storage section, which includes a non-volatile two-terminal storage unit and a first selection switch connected in series with the non-volatile two-terminal storage unit. The reference module also includes a second gating switch connected in series with the reference resistor; The first gating switch and the second gating switch are used to turn on when reading the non-volatile two-terminal memory cells.

4. The circuit according to claim 1, characterized in that: The reference resistor includes a polysilicon resistor.

5. The circuit according to claim 1, characterized in that: The first inverter includes a first P-type field-effect transistor and a first N-type field-effect transistor; The first non-gate terminal of the first P-type field-effect transistor is connected to the pre-charge module; The second non-gate terminal of the first P-type field-effect transistor is connected to the output terminal of the first inverter. The first non-gate terminal of the first N-type field-effect transistor is connected to the output terminal of the first inverter. The second non-gate terminal of the first N-type field-effect transistor is grounded.

6. The circuit according to claim 1, characterized in that: The second inverter includes a second P-type field-effect transistor and a second N-type field-effect transistor; The first non-gate terminal of the second P-type field-effect transistor is connected to the pre-charge module; The second non-gate terminal of the second P-type field-effect transistor is connected to the output terminal of the second inverter; The first non-gate terminal of the second N-type field-effect transistor is connected to the output terminal of the second inverter; The second non-gate terminal of the second N-type field-effect transistor is grounded.

7. A memory comprising the circuitry according to any one of claims 1-6.

8. A method for reading a non-volatile two-way memory, wherein the non-volatile two-way memory includes at least one non-volatile two-way storage cell; characterized in that: This method utilizes a circuit for reading, the circuit including a reference module, a comparison module, and a pre-charge module; The reference module includes a reference resistor; The comparison module includes: a latch consisting of a first inverter and a second inverter cross-coupled, and a control switch disposed between the first cross connection and the second cross connection of the latch; The first end of the non-volatile two-ended memory cell is connected to the output of the first inverter via the first bit line. The first end of the reference resistor is connected to the output end of the second inverter via the second bit line; The method includes: The first bit line and the second bit line are pre-charged using the pre-charge module; and The control switch introduces a voltage difference between the first inverter output and the second inverter output after precharging, wherein the voltage difference is generated in response to the relative magnitude of the reference resistor and the resistance of the storage cell.

9. The method according to claim 8, characterized in that: The first end of the non-volatile two-ended memory cell is connected to the output of the first inverter via the first bit line and the first load switch. The first end of the reference resistor is connected to the output of the second inverter via the second bit line and the second load switch.

10. The method according to claim 8, characterized in that: Connect the non-volatile two-terminal memory cell in series with the first gating switch; The reference resistor is connected in series with the second gating switch; and When reading the non-volatile two-terminal memory cell, the first gating switch and the second gating switch are turned on.

11. The method according to claim 8, characterized in that: The reference resistor includes a polysilicon resistor.

12. The method according to claim 8, wherein the first inverter comprises a first P-type field-effect transistor and a first N-type field-effect transistor; characterized in that: The precharge module is connected using the first non-gate terminal of the first P-type field-effect transistor. The second non-gate terminal of the first P-type field-effect transistor is connected to the output terminal of the first inverter. The first non-gate terminal of the first N-type field-effect transistor is connected to the output terminal of the first inverter. as well as The second non-gate terminal of the first N-type field-effect transistor is grounded.

13. The method according to claim 8, wherein the second inverter comprises a second P-type field-effect transistor and a second N-type field-effect transistor; characterized in that: The precharge module is connected using the first non-gate terminal of the second P-type field-effect transistor. The second non-gate terminal of the second P-type field-effect transistor is connected to the output terminal of the second inverter. The first non-gate terminal of the second N-type field-effect transistor is connected to the output terminal of the second inverter. as well as The second non-gate terminal of the second N-type field-effect transistor is grounded.

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