Memory, data reading method, and data programming method

Abstract

The present disclosure relates to a memory, a data reading method and a data programming method. The memory comprises a memory cell string. The memory cell string comprises a weight cell string and a mask cell string connected in series along a vertical substrate direction. The weight cell string is configured to store a weight vector. The mask cell string is configured to store a mask vector, which is a pre-programmed logic decision vector used to define whether the memory cell string outputs a calculation result of the weight vector. The weight cell string comprises a plurality of weight memory cells connected in series along the vertical substrate direction. The mask cell string comprises at least one mask memory cell. The weight memory cell is configured to operate in a saturation region in response to a read voltage. The mask memory cell is configured to operate in a linear region in response to the read voltage. The present disclosure is used to improve the calculation accuracy and operation flexibility of the memory, and reduce the power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a memory, a data reading method, and a data programming method. Background Technology

[0002] 3D-NAND flash memory, as one of the mainstream memory technologies, is widely used in fields such as the Internet of Things, smartphones, laptops, and cloud computing. 3D-NAND flash memory organizes storage cells in a series configuration and increases storage density through vertical stacking, offering significant advantages in both capacity and cost.

[0003] However, some problems still exist with 3D-NAND flash memory storage arrays in related technologies, such as:

[0004] (1) Insufficient calculation accuracy:

[0005] 3D-NAND flash memory typically uses the threshold voltage Vt of the memory cell as the calculation weight and the bit line current as the output of the multiplication-accumulation operation. It is understandable that the threshold voltage Vt is inherently subject to fluctuations, for example, due to material process variations (such as trap charge distribution, interface state fluctuations, etc.), the threshold voltage Vt of the memory cell has inherent randomness, which can easily lead to errors in weight calculation. Furthermore, 3D-NAND flash memory often suffers from Background Pattern Dependency (BPD) effect, meaning that the threshold state of non-target cells in the series structure modulates their conduction capability, causing a shift in the read current of the series structure. This severely reduces the computational reliability of 3D-NAND flash memory.

[0006] (2) Poor flexibility and hardware compatibility:

[0007] The inherent block erasure mechanism of 3D-NAND flash memory requires data to be erased on a block-by-block basis, which cannot support single-bit weight updates and restricts the real-time deployment of dynamic algorithms. For example, the block erasure operation of 3D-NAND flash memory usually relies on the Fowler-Nordheim (FN) tunneling effect, which requires applying a high voltage (e.g., >20V) to the source of the entire block (usually containing 128-256 layers, with hundreds of storage cells per layer), which can easily lead to significant power consumption. In addition, when model weights need to be adjusted online, the computational interruption time caused by block erasure far exceeds the single inference time limit of the neural network, which can easily lead to a bottleneck in the deployment of dynamic algorithms.

[0008] Therefore, the aforementioned shortcomings of 3D-NAND flash memory will affect its important performance indicators such as latency, power consumption, and bandwidth. For example, it may affect the deep integration of 3D-NAND flash memory with application scenarios such as the Internet of Things, artificial intelligence, and cloud computing. Summary of the Invention

[0009] Based on this, the present disclosure provides a memory, a data reading method, and a data programming method, which helps to improve the operational flexibility and computational accuracy of the memory, thereby improving memory performance.

[0010] To achieve the above objectives, in a first aspect, some embodiments of this disclosure provide a memory. The memory includes a string of storage cells. The string of storage cells includes a weight cell string and a mask cell string sequentially connected in series along a direction perpendicular to the substrate. The weight cell string is used to store a weight vector. The mask cell string is used to store a mask vector, which is a pre-programmed logical decision vector defining whether the storage cell string outputs the calculated weight vector.

[0011] In some embodiments of this disclosure, the weighting unit string includes a plurality of weight storage units sequentially connected in series along the direction perpendicular to the substrate. The weight storage units are used to store weight data for corresponding bits in the weight vector. The masking unit string includes at least one masking storage unit. When the masking unit string includes multiple masking storage units, each masking storage unit is sequentially connected in series along the direction perpendicular to the substrate. The masking storage unit is used to store mask data for corresponding bits in the mask vector. Wherein, when the masking storage unit and the weighting storage unit store the same data, the target threshold voltage value of the masking storage unit is greater than the target threshold voltage value of the weighting storage unit. The weighting storage unit is used to operate in the saturation region in response to the read voltage. The masking storage unit is used to operate in the linear region in response to the read voltage.

[0012] In some embodiments of this disclosure, when the mask storage unit and the weight storage unit store the same data, the voltage difference between the threshold voltage target value of the mask storage unit and the threshold voltage target value of the weight storage unit is greater than or equal to 2V.

[0013] In some embodiments of this disclosure, both the weight data and the mask data include data "0" and data "1". The read voltage is defined as Vread. The target threshold voltage when the weight storage unit pre-stores data "1" is the first weight target voltage Vt(1, Weight). The target threshold voltage when the mask storage unit pre-stores data "1" is the first mask target voltage Vt(1, Mask). The target threshold voltage when the weight storage unit pre-stores data "0" is the second weight target voltage Vt(0, Weight). The target threshold voltage when the mask storage unit pre-stores data "0" is the second mask target voltage Vt(0, Mask). Then: Vt(1, Weight) < Vt(1, Mask) < Vread < Vt(0, Weight) < Vt(0, Mask).

[0014] In some embodiments of this disclosure, the on-state voltage of the weight storage unit and the mask storage unit when not selected is greater than the second mask target voltage.

[0015] In some embodiments of this disclosure, multiple memory cell strings are arranged in rows along a first direction and in columns along a second direction; the first and second directions are parallel to the substrate and intersect each other.

[0016] Optionally, the memory further includes: a plurality of bit lines, a plurality of first gating circuits, and a plurality of first control signal lines. The plurality of bit lines are spaced apart along a first direction. The bit lines extend along a second direction. The plurality of first gating circuits are arranged in rows along the first direction and in columns along the second direction. Each mask cell string in a column of memory cells is connected to a bit line through a corresponding first gating circuit. The plurality of first control signal lines are spaced apart along the second direction. The first control signal lines extend along the first direction and connect to a row of first gating circuits.

[0017] Optionally, the memory further includes: multiple weight word lines and multiple mask word lines. Weight storage cells with the same sequence number along the vertical substrate direction in each weight cell string are arranged on the same layer and connected to a weight word line. Mask storage cells with the same sequence number along the vertical substrate direction in each mask cell string are arranged on the same layer, and one row of mask storage cells in each layer is connected to a mask word line.

[0018] In some embodiments of this disclosure, first control signal lines and mask word lines connected in the same row of memory cells are stacked at intervals along a direction perpendicular to the substrate. The memory also includes a plurality of isolation structures spaced apart along a second direction. The isolation structures extend along a first direction and penetrate the layer structure containing the first gating circuit and the mask cell string along a direction perpendicular to the substrate, located between adjacent first control signal lines and adjacent mask word lines in the second direction.

[0019] In some embodiments of this disclosure, the memory includes: a memory cell array; wherein a memory cell string is formed by a row of memory cells stacked in the memory cell array along a direction perpendicular to the substrate. Mask memory cells are formed by multiplexing redundant memory cells in the memory cell array.

[0020] Secondly, some embodiments of this disclosure provide a data reading method, which can be applied to the memory described in any of the foregoing embodiments. The data reading method includes:

[0021] Apply read voltages to the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string respectively;

[0022] Apply a pass voltage to the unselected weight storage cells in the weight cell string and the unselected mask storage cells in the mask cell string respectively;

[0023] The response uses the mask vector stored in the mask unit string to read the calculation result of the weight vector in the stored unit string.

[0024] In some embodiments of this disclosure, applying a read voltage to the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string respectively includes:

[0025] Apply a read voltage to the selected weight storage cell to make the weight storage cell operate in the saturation region;

[0026] Apply a read voltage to the selected mask storage cell to make the mask storage cell work in the linear region;

[0027] When the mask storage unit and the weight storage unit store the same data, the target threshold voltage value of the mask storage unit is greater than the target threshold voltage value of the weight storage unit.

[0028] In some embodiments of this disclosure, the weight data stored in the weight storage unit and the mask data stored in the mask storage unit both include data "0" and data "1". Accordingly, the read voltage is defined as Vread, the threshold voltage target value when the weight storage unit pre-stores data "1" is the first weight target voltage Vt(1, Weight), the threshold voltage target value when the mask storage unit pre-stores data "1" is the first mask target voltage Vt(1, Mask), the threshold voltage target value when the weight storage unit pre-stores data "0" is the second weight target voltage Vt(0, Weight), and the threshold voltage target value when the mask storage unit pre-stores data "0" is the second mask target voltage Vt(0, Mask). Then: Vt(1, Weight) < Vt(1, Mask) < Vread < Vt(0, Weight) < Vt(0, Mask).

[0029] In some embodiments of this disclosure, the on-state voltage is defined as Vpass, then: Vpass > Vt(0, Mask).

[0030] In some embodiments of this disclosure, when the mask storage unit and the weight storage unit store the same data, the voltage difference between the threshold voltage target value of the mask storage unit and the threshold voltage target value of the weight storage unit is greater than or equal to 2V.

[0031] Thirdly, some embodiments of this disclosure provide a data programming method that can be applied to the memory as described in any of the foregoing embodiments. The data programming method includes:

[0032] In the first programming stage, step increment pulses are applied to the selected mask storage cells in the mask cell string to adjust the threshold voltage of the mask storage cells to the first target range of the mask;

[0033] In the second programming stage, a programming erase composite pulse is applied to the selected mask storage cell in the mask cell string to adjust the threshold voltage of the mask storage cell to the second target range of the mask.

[0034] The second target range of the mask is located within the first target range of the mask, and the voltage interval length of the second target range of the mask is less than the voltage interval length of the first target range of the mask.

[0035] In some embodiments of this disclosure, the step size of the incremental pulse is a fixed step size.

[0036] In some embodiments of this disclosure, the step size of the programmable erase composite pulse is variable, and the step size of the programmable erase composite pulse gradually decreases as the threshold voltage of the mask storage cell approaches the second target range of the mask.

[0037] The embodiments disclosed herein may have, or at least have, the following advantages:

[0038] In this embodiment of the disclosure, a weight unit string and a mask unit string are set in the storage unit string, and the weight unit string and the mask unit string are sequentially connected in series along the direction perpendicular to the substrate. After the weight vector is stored in the weight unit string and the mask vector is stored in the mask unit string, the mask vector stored in the mask unit string is used as the logical determination vector for whether the storage unit string outputs the calculation result of the weight vector. That is, the mask unit string can be configured as a logic gate unit to control the overall calculation output of the storage unit string, thereby realizing the "AND" logic between different layers of weight storage units.

[0039] Therefore, compared to the traditional read operation which requires all storage cells except the target layer storage cell to be in the conducting state, making the target layer storage cell the sole factor determining the current on / off state, the embodiments of this disclosure innovatively adjust this constraint. By redefining the functional division of storage cells, i.e., by setting a mask cell string, it is beneficial to simultaneously apply read voltage to the weighted storage cells of multiple layers for weight vector selection calculation, effectively improving the in-memory calculation efficiency. At the same time, the mask cell string can be configured as a logic gate unit through the mask vector stored in the mask cell string, so as to flexibly control the overall calculation output of the storage cell string. It is also beneficial to match the functional implementation of the weighted storage cell and the mask storage cell so that the weighted storage cell and the mask storage cell work in different states, thereby effectively avoiding the signal crosstalk risk caused by the need for adjacent column storage cell strings to share bit lines for read current, and effectively improving the calculation accuracy and operational flexibility of the memory.

[0040] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the circuit architecture of a memory provided in some embodiments;

[0043] Figure 2 This is an equivalent circuit diagram of a string of storage cells provided in some embodiments;

[0044] Figure 3 A comparison diagram of the operating current of a weighted storage unit and a mask storage unit in response to a read voltage, provided in some embodiments;

[0045] Figure 4 This is a schematic diagram of the threshold voltage distribution when the storage cells in a storage cell array are pre-stored with data "1" and "0" in some embodiments.

[0046] Figure 5 This is a schematic diagram of a cross-sectional structure of a memory provided in some embodiments;

[0047] Figure 6 This is a flowchart illustrating a data reading method provided in some embodiments;

[0048] Figure 7 This is a timing control diagram of a data reading method provided in some embodiments;

[0049] Figure 8 This is a flowchart illustrating a data programming method provided in some embodiments;

[0050] Figure 9 A timing control diagram for a data programming method provided in some embodiments;

[0051] Figure 10 This is a flowchart of a data programming method provided in some embodiments. Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0053] Some exemplary embodiments of the invention have been described for illustrative purposes. It should be understood that the invention may be implemented in other ways not specifically shown in the accompanying drawings.

[0054] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0057] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] Please combine Figure 1 and Figure 2 Understood, some embodiments of this disclosure provide a memory. The memory includes a storage cell string U. The storage cell string U includes a weight cell string U1 and a mask cell string U2 sequentially connected in series along a direction perpendicular to the substrate (e.g., the Z direction). The weight cell string U1 is used to store a weight vector. The mask cell string U2 is used to store a mask vector, which is a pre-programmed logical decision vector defining whether the storage cell string U outputs the weight vector calculation result.

[0059] For example, the memory includes a memory cell array. The memory cell string U is composed of a row of memory cells stacked in the memory cell array along a direction perpendicular to the substrate (e.g., the Z direction).

[0060] For example, the weight unit string U1 includes a plurality of weight storage units 10 sequentially connected in series along the direction perpendicular to the substrate (e.g., the Z direction). The weight storage units 10 are used to store the weight data of corresponding bits in the weight vector. That is, the weight vector is formed by sequentially arranging the weight data stored in each weight storage unit 10 in the corresponding weight unit string U1.

[0061] For example, the mask unit string U2 includes at least one mask storage unit 20. When the mask unit string U2 includes multiple mask storage units 20, the mask storage units 20 are sequentially connected in series along the direction perpendicular to the substrate (e.g., the Z direction). The mask storage unit 20 is used to store mask data of corresponding bits in the mask vector. That is, the mask vector is formed by sequentially arranging the mask data stored in each mask storage unit 20 in the corresponding mask unit string U2.

[0062] In some embodiments of this disclosure, please refer to Figure 1 Multiple memory cell strings U are arranged in rows along a first direction (e.g., the X direction) and in columns along a second direction (e.g., the Y direction). The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) are parallel to the substrate and intersect, for example, orthogonal.

[0063] Optionally, the memory further includes: multiple bit lines BL, multiple first gating circuits 30, and multiple first control signal lines TSGs. The multiple bit lines BL are spaced apart along a first direction (e.g., the X direction). The bit lines BL extend along a second direction (e.g., the Y direction). The multiple first gating circuits 30 are arranged in rows along the first direction (e.g., the X direction) and in columns along the second direction (e.g., the Y direction). Each mask cell string U2 in a column of memory cells U is connected to a bit line BL through a corresponding first gating circuit 30. The multiple first control signal lines TSGs are spaced apart along the second direction (e.g., the Y direction). The first control signal lines TSGs extend along the first direction (e.g., the X direction) and connect to a row of first gating circuits 30.

[0064] Optionally, the memory further includes: a source line SL, a second control signal line BSG, and multiple second gating circuits 40. The multiple second gating circuits 40 are arranged in rows along a first direction (e.g., the X direction) and columns along a second direction (e.g., the Y direction). The weighted cell string U1 in each memory cell string U is connected to the source line SL through its corresponding second gating circuit 40. The second control signal lines are spaced apart along the second direction. The second control signal line BSG connects to all the second gating circuits 40 in the entire layer.

[0065] In some examples, the first gating circuit 30 is, for example, an up-gating transistor, and the first control signal lines TSGs are connected to the gates of the corresponding row of up-gating transistors. The first control signal lines TSGs can also be called top-select gates (TSGs). The up-gating transistors can be turned on or off in response to the voltage signal provided by the first control signal lines TSGs.

[0066] Similarly, the second selection circuit 40 is, for example, a bottom-select transistor. The second control signal line BSG is connected to the gate of each bottom-select transistor in the entire layer. The second control signal line BSG can also be called the bottom-select transistor control gate line (BSG). The bottom-select transistor can be turned on or off in response to the voltage signal provided by the second control signal line BSG.

[0067] In some examples, the upper and lower gate transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), but they are not limited to this; other types of transistors with switching functions are also applicable.

[0068] Optionally, the memory also includes: multiple weighted word lines (e.g. Figure 1 WL1~WL shown n ) and multiple mask word lines (e.g. Figure 1 or Figure 2 (Dummy shown). Here, both the mask word line and the weight word line are word lines and can be fabricated using the same process.

[0069] Optionally, the mask word lines can be constructed by segmenting redundant word lines in each word line.

[0070] For example, such as Figure 1 As shown, in each weight unit string U1, weight storage units 10 with the same sequence number along the vertical substrate direction (e.g., the Z direction) are arranged on the same layer and connected to a weight word line WL. In each mask unit string U2, mask storage units 20 with the same sequence number along the vertical substrate direction (e.g., the Z direction) are arranged on the same layer, and a row of mask storage units 20 in each layer of mask storage units is connected to a mask word line Dummy.

[0071] It is understandable that in other examples, each mask storage unit 20 set in the same layer can also be connected to a weight word line Dummy at the same time.

[0072] For ease of description, each weight storage unit 10 set in the same layer can be simply referred to as the weight layer (W), and each mask storage unit 20 set in the same layer can be simply referred to as the mask layer (M).

[0073] Accordingly, please combine Figure 2 Understanding, through the target weight word line WL Select Applying a read voltage Vread to the selected weight layer (W) allows the weight data stored in the weight storage cell 10 within that weight layer (W) to participate in the calculation of its corresponding storage cell string U; this can be achieved through other weight word lines (e.g., WL). n Applying a conduction voltage Vpass to a non-selected weight layer (W) can prevent the weight data stored in the weight storage cell 10 in that weight layer (W) from participating in the calculation of its storage cell string U.

[0074] Similarly, by applying a read voltage Vread to the mask storage cell 20 of the selected row or layer through the target mask word line Dummy, the mask data stored in each mask storage cell 20 of that row or layer can participate in the calculation of its own storage cell string U; by applying a conduction voltage Vpass to the mask storage cell 20 of the unselected row or layer through other mask word lines, the mask data stored in each mask storage cell 20 of that row or layer can be excluded from the calculation of its own storage cell string U.

[0075] From the above, in the storage cell string U, the weight data stored in the selected weight storage cell 10 is multiplied to obtain the weight vector calculation result W. Since the mask storage cell 20 and the weight storage cell 10 are connected in series in the storage cell string U, when the mask storage cell 20 is selected, the mask data stored in the mask storage cell 20, for example, M, can be multiplied with the aforementioned weight vector calculation result W to ensure that the final calculation result output by the storage cell string U can be represented as the read current Iread output to the corresponding bit line BL, and Iread = M·W.

[0076] For example, both the weight data and the mask data include data "0" and data "1". However, this is not the only possibility; for instance, both the weight data and the mask data can also be multi-valued data.

[0077] For example, if the mask data M stored in the mask storage unit 20 is "1", the final calculation result that the storage unit string U can output is the calculation result W of the weight vector. If the mask data M stored in the mask storage unit 20 is "0", the final calculation result that the storage unit string U can output is zero, that is, the calculation result W of the weight vector will be cleared to zero.

[0078] In this embodiment of the disclosure, by redefining the functional division of the storage unit, the vertically stacked storage units can be configured into two types: weight storage units and mask storage units (i.e., switch control units). That is, the storage unit string is provided with a weight unit string and a mask unit string connected in sequence, and the weight vector can be stored through the weight unit string and the mask vector can be stored through the mask unit string. Since the memory cells on the same memory cell string U are connected in series sequentially, compared to the traditional read operation which requires all memory cells except the target layer memory cell to be in the conducting state so that the target layer memory cell becomes the sole factor determining the current on / off state, this embodiment of the present disclosure innovatively adjusts this constraint. By setting a mask cell string U2, a read voltage Vread can be applied to multiple layers of weighted memory cells simultaneously to perform weight vector selection calculation, effectively improving the in-memory calculation efficiency. At the same time, the mask vector stored in the mask cell string U2 can be used as the logical determination vector for whether the memory cell string U outputs the weight vector calculation result. That is, the mask cell string U2 can be configured as a logic gate unit to control the overall calculation output of the memory cell string, thereby realizing the "AND" logic between different layers of weighted memory cells. It also facilitates the matching of the functions of the weighted memory cell and the masked memory cell, allowing the weighted memory cell and the masked memory cell to work in different states. This effectively avoids the risk of signal crosstalk between adjacent column memory cell strings because their read current needs to share bit lines, while effectively improving the calculation accuracy and operational flexibility of the memory.

[0079] It should be added that when the read voltage Vread is applied to at least one selected weight storage cell 10 and at least one row / layer mask storage cell 20 at the same time, the formation of the current path in the storage cell string U needs to satisfy the necessary condition that all unselected weight storage cells 10 and unselected mask storage cells 20 are in the conducting state with the applied conduction voltage Vpass.

[0080] Furthermore, when controlling the calculation results of the weight vector in the memory cell string U, the aforementioned first gating circuit 30 and second gating circuit 40 can also be controlled to be in the on state.

[0081] It is worth mentioning that, in some embodiments of this disclosure, the mask storage unit 20 is composed of redundant storage units in the storage unit array.

[0082] It is understood that, in order to avoid the influence of the first gating circuit 30 on the data stored in the storage cells of the storage cell array, the storage cells of the adjacent layers of the first gating circuit 30 are usually set as redundant storage cells to achieve reliable storage. In this embodiment of the present disclosure, the redundant storage cells in the storage cell array are reused as mask storage cells 20. That is, the redundant storage cells can be used as mask storage cells 20 by configuring mask vectors, without changing the hardware structure of the memory, and without losing the storage density of the memory.

[0083] In some embodiments of this disclosure, both the weight storage unit 10 and the mask storage unit 20 include, but are not limited to, storage transistors. Please refer to... Figure 3The weighted storage unit 10 operates in the saturation region in response to the read voltage Vread. The mask storage unit 20 operates in the linear region in response to the read voltage Vread. Thus, in this embodiment of the present disclosure, after applying the read voltage Vread to the selected weighted storage unit 10 and the mask storage unit 20, and applying the conduction voltage Vpass to the unselected weighted storage unit 10 and the mask storage unit 20, each weighted storage unit 10 is equivalent to a series resistor. Compared to the change in the equivalent channel resistance of the mask storage unit 20 operating in the linear region, the change in the equivalent channel resistance of the target weighted storage unit 10 operating in the saturation region, and the change in the sum of the equivalent channel resistances of the unselected storage units 10 in each forced conduction state in the weighted storage string U are all significantly smaller or negligible. This approach not only facilitates power consumption reduction but also ensures that the intrinsic fluctuations of the threshold voltage Vt of each memory cell in the memory cell string U are primarily reflected in the mask memory cell 20 operating in the linear region. This means that the intrinsic fluctuations of the threshold voltage Vt of each weighted memory cell 10 operating in the saturation region and under the on-state voltage can be ignored. Furthermore, it effectively reduces the impact of changes in the sum of the equivalent channel resistances of the unselected memory cells 10 on the overall equivalent resistance of the series structure, thus preventing read current offset. Therefore, it effectively suppresses, from a physical perspective, the weight calculation error caused by the intrinsic fluctuations of the threshold voltage of each memory cell and the current offset caused by the background mode dependence of each memory cell in related technologies, thereby improving the computational accuracy of the memory.

[0084] Therefore, in this embodiment of the present disclosure, the read current that can be output by the storage cell string U mainly depends on the threshold voltage distribution characteristics of each mask storage cell 20 in the mask cell string U2, while it is relatively insensitive to the changes in the threshold voltage distribution of each weight storage cell 10 in the weight cell string U1. Based on the synergy of the mask cell string U2 and the weight cell string U1, a better current limiting effect can be achieved, so as to significantly improve the calculation accuracy of the calculation results corresponding to the weight vector in the storage cell string U.

[0085] Based on this, in some examples, a column of memory cells U is connected to a bit line BL, and a row of mask memory cells 20 in a layer of mask memory cells is connected to a mask word line Dummy. This facilitates precise adjustment of the threshold voltage distribution of the mask memory cells 20. For example, a programming erase composite pulse can be applied to the mask memory cells 20 to finely adjust the threshold voltage distribution of the mask memory cells 20, thereby finely adjusting the output current of the memory cell column U to further improve the computational accuracy of the memory.

[0086] For example, please combine Figure 4It is understood that when the mask storage unit 20 and the weight storage unit 10 store the same data, the target threshold voltage value of the mask storage unit 20 is greater than the target threshold voltage value of the weight storage unit 10. This makes it easier to ensure that the change in the equivalent channel resistance of the mask storage unit 20, which operates in the linear region, is significantly greater than the change in the equivalent channel resistance of the target weight storage unit 10, which operates in the saturation region, as well as the change in the sum of the equivalent channel resistances of the unselected storage units 10 in each forced conduction state in the weight storage string U.

[0087] Optionally, when the mask storage unit 20 and the weight storage unit 10 store the same data, the voltage difference between the threshold voltage target value of the mask storage unit 20 and the threshold voltage target value of the weight storage unit 10 is greater than or equal to 2V, for example, 2V.

[0088] In some embodiments of this disclosure, please refer to Figure 4 To understand, taking the example where both weighted data and mask data include data "0" and data "1", let the read voltage be Vread. The threshold voltage target value when the weighted storage unit 10 stores data "1" is the first weighted target voltage Vt(1, Weight). The threshold voltage target value when the mask storage unit 20 stores data "1" is the first mask target voltage Vt(1, Mask). The threshold voltage target value when the weighted storage unit 10 stores data "0" is the second weighted target voltage Vt(0, Weight). The threshold voltage target value when the mask storage unit 20 stores data "0" is the second mask target voltage Vt(0, Mask). Then: Vt(1, Weight) < Vt(1, Mask) < Vread < Vt(0, Weight) < Vt(0, Mask).

[0089] In some embodiments of this disclosure, please refer to Figure 4 It is understood that the on-state voltage of weight storage unit 10 and mask storage unit 20 when not selected is greater than the second mask target voltage. If the on-state voltage is defined as Vpass, then Vpass > Vt(0, Mask).

[0090] It should be added that, such as Figure 4 As shown, the first weighted target voltage Vt(1, Weight), the first mask target voltage Vt(1, Mask), the second weighted target voltage Vt(0, Weight), and the second mask target voltage Vt(0, Mask) are all range values. The weighted storage unit 10 and the mask storage unit 20 that pre-store data "1" or "0" in the storage unit array all conform to a normal distribution.

[0091] In some embodiments of this disclosure, please refer to Figure 5In the memory cell array, an insulating layer 50 is provided between different layers of memory cells to effectively isolate adjacent word lines in the direction perpendicular to the substrate, such as two adjacent weighted word lines, or adjacent weighted word lines and mask word lines, or two adjacent mask word lines, etc.

[0092] For example, an insulating layer 50 is also provided between the top-layer mask storage cell 20 and the first gating circuit 30 to isolate the mask word lines Dummy and the first control signal lines TSGs that are adjacent in the direction perpendicular to the substrate.

[0093] For example, an insulating layer 50 is also provided between the underlying weighted storage cell 10 and the second gating circuit 40 to isolate adjacent weighted word lines WL in the direction perpendicular to the substrate. n And the second control signal line BSG.

[0094] For example, please continue reading Figure 5 Each row of mask storage cells 20 in each layer of mask storage cells is connected to a mask word line (Dummy). The first control signal lines (TSGs) and mask word lines (Dummy) connected in the same row of storage cells are stacked at intervals along a direction perpendicular to the substrate (e.g., the Z direction) and may have the same projection along the same direction. The memory also includes a plurality of isolation structures 60 spaced apart along a second direction (e.g., the Y direction). The isolation structures 60 extend along a first direction (e.g., the X direction) and penetrate the layer structure containing the first gate circuit 30 and the mask cell string U2 along a direction perpendicular to the substrate (e.g., the Z direction), located between adjacent first control signal lines (TSGs) and adjacent mask word lines (Dummy) in the second direction (e.g., the Y direction). That is, the isolation structure 60 can penetrate the layer structure corresponding to the first gating circuit 30 and the mask unit string U2 between adjacent row memory cell strings U, so as to effectively isolate the mask word lines Dummy adjacent in the second direction (e.g., the Y direction), thereby enabling the mask memory cell 20 to form an independent gate control structure to achieve bit erasure operation without array interference, which is beneficial to apply programming erasure composite pulse to the mask memory cell 20 to further improve the calculation accuracy of the memory.

[0095] In this embodiment, a weighted word line, a redundant word line layer, and a first control layer can be fabricated in one layer. Then, multiple isolation trenches are formed by etching back the first control layer and the redundant word line layer. The first control layer is isolated by the isolation trenches to form first control signal lines (TSGs), and the redundant word line layer is isolated by the isolation trenches to form mask word lines (Dummy). Finally, dielectric material is filled into the isolation trenches to form the above isolation structure 60.

[0096] In this embodiment, the fabrication process of the isolation structure 60 is simple and does not require any additional complex process steps.

[0097] This embodiment of the disclosure, by setting the aforementioned isolation structure 60, can fundamentally change the generation path of programming crosstalk and erasure crosstalk while maintaining the original function of the memory cell array. Specifically, it effectively isolates adjacent mask word lines (Dummy), enabling substantial isolation of the logic gate units of the memory cell string U. Thus, during programming or erasure operations, the unselected mask memory cells 20 sharing the same bit line BL do not require programming or erasure voltage applied to their gates, fundamentally avoiding the risk of misprogramming or miserasing. This embodiment of the disclosure provides a reliable guarantee for optimizing the precise programming and bit erasure operations of the mask memory cells 20, allowing for more precise control of the threshold voltage distribution of the mask memory cells 20.

[0098] This disclosure also provides a data reading method in some embodiments, which can be applied to the memory described in any of the foregoing embodiments. This data reading method also possesses all the technical advantages of the aforementioned memory.

[0099] Please see Figure 6 The data reading method includes the following steps S110~S130.

[0100] S110, apply read voltages to the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string respectively.

[0101] S120, apply conduction voltage to the unselected weight storage cells in the weight cell string and the unselected mask storage cells in the mask cell string respectively.

[0102] For example, in step 120, applying a read voltage to the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string respectively includes: applying a read voltage to the selected weight storage cell to make the weight storage cell work in the saturation region; and applying a read voltage to the selected mask storage cell to make the mask storage cell work in the linear region.

[0103] For example, when the mask storage unit and the weight storage unit store the same data, the target threshold voltage value of the mask storage unit is greater than the target threshold voltage value of the weight storage unit.

[0104] For example, when the mask storage unit and the weight storage unit store the same data, the voltage difference between the target threshold voltage value of the mask storage unit and the target threshold voltage value of the weight storage unit is greater than or equal to 2V, for example, equal to 2V.

[0105] S130: Respond to the mask vector stored in the mask unit string, and read the calculation result of the weight vector in the storage unit string.

[0106] It should be understood that, Figure 6 The steps in the data reading method shown are described sequentially according to their step numbers, but these steps are not necessarily executed in the order of their step numbers. Unless otherwise specified in this document, there is no strict order restriction on the execution of these steps: they can be executed synchronously, such as executing S110 and S120 synchronously; or they can be executed according to a preset step order, such as executing S110, S120 and S130 in sequence, or executing S120, S110 and S130 in sequence, etc.

[0107] In some embodiments of this disclosure, the weight data stored in the weight storage unit and the mask data stored in the mask storage unit both include data "0" and data "1". Accordingly, the read voltage is defined as Vread, the threshold voltage target value when the weight storage unit pre-stores data "1" is the first weight target voltage Vt(1, Weight), the threshold voltage target value when the mask storage unit pre-stores data "1" is the first mask target voltage Vt(1, Mask), the threshold voltage target value when the weight storage unit pre-stores data "0" is the second weight target voltage Vt(0, Weight), and the threshold voltage target value when the mask storage unit pre-stores data "0" is the second mask target voltage Vt(0, Mask). Then: Vt(1, Weight) < Vt(1, Mask) < Vread < Vt(0, Weight) < Vt(0, Mask).

[0108] In some embodiments of this disclosure, the on-state voltage is defined as Vpass, then: Vpass > Vt(0, Mask).

[0109] Figure 7 A timing control diagram for the data reading method described above is shown. Please refer to [link / reference]. Figure 7 Taking a mask cell string that includes only one mask storage cell and has the same turn-on control voltage for the first and second gating circuits as an example, when reading data from the target storage cell string: a turn-on control voltage V1 is applied to the first gating circuit connected to the target storage cell string through the first control signal line TSGs; a turn-on control voltage V1 is applied to the second gating circuit connected to the target storage cell string through the second control signal line BSG; and a read voltage V1 is applied to the mask storage cell in the target storage cell string through the mask word line Dummy. read Through the first target weight word line WL Select Apply a read voltage V to the selected weighted memory cell in the target memory cell string. read Through the second target weight line WL Unselect Apply a turn-on voltage V to the selected weighted memory cell in the target memory cell string. passThen, after providing the initial voltage V to the bit line BL, the calculation result of the weight vector in the target memory cell string can be read through the read current transmitted by the bit line BL.

[0110] For example, the turn-on control voltage V1 can be three times the initial voltage V on the bit line BL, i.e., V1 = 3V.

[0111] This disclosure also provides a data programming method in some embodiments, applicable to the memory described in any of the foregoing embodiments. This data programming method also possesses all the technical advantages of the aforementioned memory. Please refer to... Figure 8 The data programming method includes the following steps S210 and S220.

[0112] S210, in the first programming stage t1, a step increment pulse is applied to the selected mask storage cell in the mask cell string to adjust the threshold voltage of the mask storage cell to the first target range of the mask.

[0113] Optionally, please refer to Figure 9 The step size of the Increment Step Programming Pulse (ISPP) is a fixed step size.

[0114] S220, in the second programming stage t2, a programming erase composite pulse is applied to the selected mask storage cell in the mask cell string to adjust the threshold voltage of the mask storage cell to the second target range of the mask.

[0115] Optionally, the second target range of the mask is located within the first target range of the mask, and the voltage interval length of the second target range of the mask is shorter than the voltage interval length of the first target range of the mask. That is, in the first programming stage, the threshold voltage of the mask storage cell is adjusted coarsely, and in the second programming stage, the threshold voltage of the mask storage cell is adjusted finely.

[0116] Optionally, please combine Figure 9 It is understood that the programmable erase composite pulse includes, but is not limited to, alternating programmable pulses PGM and eraser pulses ERS. For example, a programmable erase composite pulse may begin with an eraser pulse ERS and end with an eraser pulse ERS; or, for example, a programmable erase composite pulse may begin with a programmable pulse PGM and end with a programmable pulse PGM; both are permitted.

[0117] Optionally, when applying the programmable erase composite pulse, the programmable erase composite pulse is composed of a programming pulse PGM and an erase pulse ERS, which is easy to dynamically control in real time; for example, after each application of the programming pulse PGM or the erase pulse ERS, the type of the next pulse can be selected according to the difference between the current threshold voltage of the mask storage cell and the second target range of the mask.

[0118] It is worth mentioning that, in some embodiments of this disclosure, the step size of the programmable erase composite pulse is variable, and the step size of the programmable erase composite pulse gradually decreases as the threshold voltage of the mask storage cell approaches the second target range of the mask. In this way, the step size of the programmable erase composite pulse can be adaptively adjusted to further improve the adjustment accuracy.

[0119] As described above, in this embodiment of the present disclosure, by adjusting the threshold voltage distribution of the mask storage unit in stages, it is beneficial to quickly adjust the threshold voltage of the mask storage unit to the first target range (i.e., a wider target range) of the mask through continuous ISPP pulses with a fixed step size in the first programming stage. Then, the threshold voltage of the mask storage unit is precisely fine-tuned by programming and erasing composite pulses with a variable step size, so as to converge the threshold voltage to a narrower second target range of the mask. This enables precise control of the threshold voltage of the mask storage unit, that is, precise adjustment of the mask vector in the mask unit string.

[0120] It is understood that the intrinsic fluctuations in the threshold voltage of each memory cell in the memory cell string are mainly reflected in the mask memory cells operating in the linear region. By precisely controlling the threshold voltage of the mask memory cells in the embodiments of this disclosure, the output current of the memory cell string can be finely adjusted, thereby effectively improving the computational accuracy of the memory.

[0121] In some examples, the step size of the programmable erase composite pulse can be set with multiple levels of parameters. See also... Figure 10 Define the current threshold voltage of the mask storage cell as V. T The target voltage value is V target The total number of adjustment steps corresponding to the first programming stage is N. c The total number of adjustment steps corresponding to the second programming stage is N. f If the range of the second target of the mask is ε, then the aforementioned data programming method can be implemented as follows:

[0122] In the first programming phase, if |V T -V target | > 0.5V and the number of adjustments i < N c Then the increment of the step increment pulse increases sequentially with the number of adjustments, until |V T -V target If |≤0.5V, then proceed to the second programming stage.

[0123] In the second programming stage, if |V T -V target |>ε and the number of adjustments j<N f Then it can be in |V T -V target When |> 0.3V, use a step size of 0.5 steps; when 0.2V < |VT -V target When | ≤ 0.3V, use a step size of 0.25 steps; when ε < |V T -V target When |V ≤ 0.2V, use a step size of 0.1 steps. Adjust the step size gradually as the number of adjustments increases until |V T -V target |≤ε End.

[0124] Alternatively, the weight storage unit and the mask storage unit can be driven independently. The data programming method further includes applying incremental pulses to selected weight storage units in the weight unit string to adjust the threshold voltage of the weight storage units to the target weight range.

[0125] Optionally, the target range for weights and the target range for masks can be different.

[0126] Optionally, the threshold voltage adjustment stage of the weighted storage unit can be performed in the first programming stage, or in the second programming stage, or throughout the entire first programming stage and the second programming stage.

[0127] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The embodiments described above are merely examples of several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure.

Claims

1. A memory, characterized in that, include: The storage cell string includes: a weight cell string and a mask cell string that are sequentially connected in series along the direction perpendicular to the substrate; The weight unit string is used to store the weight vector; the weight unit string includes a plurality of weight storage units connected in series along the direction perpendicular to the substrate; the weight storage unit is used to store the weight data of the corresponding bit in the weight vector; The mask unit string is used to store a mask vector, which is a pre-programmed logical decision vector used to define whether the storage unit string outputs the calculation result of the weight vector; the mask unit string includes at least one mask storage unit; when the mask unit string includes multiple mask storage units, each mask storage unit is sequentially connected in series along the direction perpendicular to the substrate, and the mask storage unit is used to store the mask data of the corresponding bit in the mask vector; The storage cell string is used to read the calculation result of the weight vector in the storage cell string in response to the mask vector stored in the mask cell string; wherein, the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string are respectively applied with a read voltage; the unselected weight storage cell in the weight cell string and the unselected mask storage cell in the mask cell string are respectively applied with an on voltage.

2. The memory according to claim 1, characterized in that, The weight unit string includes multiple weight storage units sequentially connected in series along the direction perpendicular to the substrate; the weight storage units are used to store weight data of corresponding bits in the weight vector; the mask unit string includes at least one mask storage unit; when the mask unit string includes multiple mask storage units, each mask storage unit is sequentially connected in series along the direction perpendicular to the substrate; the mask storage unit is used to store mask data of corresponding bits in the mask vector; wherein... When the mask storage unit and the weight storage unit store the same data, the threshold voltage target value of the mask storage unit is greater than the threshold voltage target value of the weight storage unit; the weight storage unit is used to operate in the saturation region in response to the read voltage; the mask storage unit is used to operate in the linear region in response to the read voltage.

3. The memory according to claim 2, characterized in that, When the mask storage unit and the weight storage unit store the same data, the voltage difference between the threshold voltage target value of the mask storage unit and the threshold voltage target value of the weight storage unit is greater than or equal to 2V.

4. The memory according to claim 2, characterized in that, Both the weight data and the mask data include data "0" and data "1"; the read voltage is defined as Vread, the threshold voltage target value when the weight storage unit pre-stores the data "1" is the first weight target voltage Vt(1, Weight), the threshold voltage target value when the mask storage unit pre-stores the data "1" is the first mask target voltage Vt(1, Mask), the threshold voltage target value when the weight storage unit pre-stores the data "0" is the second weight target voltage Vt(0, Weight), and the threshold voltage target value when the mask storage unit pre-stores the data "0" is the second mask target voltage Vt(0, Mask), then: Vt(1,Weight)<Vt(1,Mask)<Vread<Vt(0,Weight)<Vt(0,Mask).

5. The memory according to claim 4, characterized in that, The on-state voltage of the weight storage unit and the mask storage unit when not selected is greater than the target voltage of the second mask.

6. The memory according to claim 2, characterized in that, The plurality of memory cell strings are arranged in rows along a first direction and in columns along a second direction; the first direction and the second direction are parallel to and intersect the substrate; wherein, the memory further includes: Multiple bit lines are spaced apart along the first direction; the bit lines extend along the second direction. Multiple first gating circuits are arranged in rows along the first direction and in columns along the second direction; each of the mask cell strings in a column of the memory cell strings is connected to a bit line through a corresponding first gating circuit; Multiple first control signal lines are spaced apart along the second direction; the first control signal lines extend along the first direction and are connected to a row of first gating circuits; Multiple weight word lines; weight storage cells with the same sequence number along the vertical substrate direction in each weight cell string are arranged on the same layer and connected to one weight word line; Multiple mask word lines; mask storage cells with the same sequence number along the vertical substrate direction in each mask cell string are arranged in the same layer; one row of mask storage cells in each layer of mask storage cells is connected to one mask word line.

7. The memory according to claim 6, characterized in that, The first control signal line and the mask word line, which are connected in series in the same row of memory cells, are stacked at intervals along the direction perpendicular to the substrate. The memory further includes: a plurality of isolation structures spaced apart along the second direction; The isolation structure extends along the first direction and penetrates the layer structure containing the first gating circuit and the mask unit string along the direction perpendicular to the substrate, located between two adjacent first control signal lines and between two adjacent mask word lines in the second direction.

8. The memory according to any one of claims 2 to 7, characterized in that, include: A storage cell array; wherein the storage cell string is composed of a row of storage cells stacked along the direction perpendicular to the substrate in the storage cell array; the mask storage cell is composed of redundant storage cells in the storage cell array.

9. A data reading method, characterized in that, Applied to the memory as described in any one of claims 1 to 8; The data reading method includes: A read voltage is applied to the selected weight storage cell in the weight cell string and the selected mask storage cell in the mask cell string, respectively. Apply an on-state voltage to the unselected weight storage cells in the weight cell string and the unselected mask storage cells in the mask cell string respectively; In response to the mask vector stored in the mask unit string, the calculation result of the weight vector in the storage unit string is read.

10. The data reading method according to claim 9, characterized in that, Applying read voltages to the selected weight storage cells in the weight cell string and the selected mask storage cells in the mask cell string respectively includes: The read voltage is applied to the selected weight storage cell to make the weight storage cell operate in the saturation region; The read voltage is applied to the selected mask storage cell to make the mask storage cell operate in the linear region; When the mask storage unit and the weight storage unit store the same data, the target threshold voltage value of the mask storage unit is greater than the target threshold voltage value of the weight storage unit.

11. The data reading method according to claim 10, characterized in that, The weight data stored in the weight storage unit and the mask data stored in the mask storage unit both include data "0" and data "1"; Wherein, the read voltage is defined as Vread, the threshold voltage target value when the weighted storage unit pre-stores the data "1" is the first weighted target voltage Vt(1, Weight), the threshold voltage target value when the mask storage unit pre-stores the data "1" is the first mask target voltage Vt(1, Mask), the threshold voltage target value when the weighted storage unit pre-stores the data "0" is the second weighted target voltage Vt(0, Weight), and the threshold voltage target value when the mask storage unit pre-stores the data "0" is the second mask target voltage Vt(0, Mask), then: Vt(1,Weight)<Vt(1,Mask)<Vread<Vt(0,Weight)<Vt(0,Mask).

12. The data reading method according to claim 11, characterized in that, Define the conduction voltage as Vpass, then: Vpass > Vt (0, Mask).

13. The data reading method according to any one of claims 10 to 12, characterized in that, When the mask storage unit and the weight storage unit store the same data, the voltage difference between the threshold voltage target value of the mask storage unit and the threshold voltage target value of the weight storage unit is greater than or equal to 2V.

14. A data programming method, characterized in that, Applied to the memory as described in any one of claims 1 to 8; The data programming method includes: In the first programming stage, step increment pulses are applied to the selected mask storage cells in the mask cell string to adjust the threshold voltage of the mask storage cells to the first target range of the mask; In the second programming stage, a programming erase composite pulse is applied to the selected mask storage cell in the mask cell string to adjust the threshold voltage of the mask storage cell to the second target range of the mask. Wherein, the second target range of the mask is located within the first target range of the mask, and the voltage interval length of the second target range of the mask is less than the voltage interval length of the first target range of the mask.

15. The data programming method according to claim 14, characterized in that, The step size of each incremental pulse is a fixed step size; The step size of the programmable erase composite pulse is variable, and the step size of the programmable erase composite pulse gradually decreases as the threshold voltage of the mask storage cell approaches the second target range of the mask.

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