Switching power supply and automatic recovery control method for protection of switching power supply

Abstract

The application discloses a switching power supply and a protection automatic recovery control method thereof, and relates to the field of switching power supplies.The switching power supply comprises a main power circuit module, a control chip and an auxiliary power supply module; the control chip is connected with the main power circuit module and the auxiliary power supply module; the control chip is used for detecting the running state of the switching power supply after normal wave emission; when the abnormal state is continuously detected within a preset judgment time, the wave emission is stopped; after the wave emission is stopped, when it is detected that the preset condition is met and the power supply voltage of the control chip is higher than the starting threshold, the normal wave emission is resumed; wherein, the preset condition comprises that the time after the wave emission is stopped reaches an automatic recovery time, the time length of the automatic recovery time is longer than the time length of one restart after the control chip is powered off; and / or the number of restarts after the control chip is powered off reaches an automatic recovery restart number; the automatic recovery restart number is greater than 1, and the application can avoid the damage of the switching power supply caused by overheating.

Description

Technical Field

[0001] This application relates to the field of switching power supplies, and in particular to a switching power supply and a method for automatic recovery control of the protection of the switching power supply. Background Technology

[0002] A flyback switching power supply is a typical topology of switching power supplies. Its main characteristic is that energy is output from the secondary winding when the primary power transistor is off. Flyback switching power supplies are widely used in various power adapters due to their simple circuit structure and low cost.

[0003] In practical applications, flyback switching power supplies may encounter various harsh operating conditions. To ensure their safety and reliability, the control chip usually has a built-in protection circuit: when the control chip continuously detects an abnormal state within a preset judgment time, the control chip will stop transmitting waveforms. After the control chip stops transmitting waveforms, its VDD power supply will be cut off, which will trigger the control chip to restart. After restarting, waveform transmission will resume. If the abnormal state is still not resolved after restarting, the process of judging the abnormal state - stopping waveform transmission - restarting - resuming waveform transmission will continue.

[0004] Currently, there are generally two ways to handle the situation after the control chip triggers protection and stops transmitting waves:

[0005] The first method is to latch the protection signal. Even if the abnormal state is cleared later, the chip cannot automatically return to normal operation. The user needs to manually unplug and plug it in to restore its operation, which is cumbersome and inconvenient to use.

[0006] The second method involves clearing the protection signal after the control chip restarts. For flyback switching power supplies, when the control chip stops transmitting signals, VDD will power down, triggering a restart. If the abnormal state is not resolved after restarting, the chip enters the protection judgment process. To prevent accidental protection activation, the chip needs to continuously detect the abnormal state for a preset judgment time (usually set to 60ms to 120ms) before determining protection. Therefore, even if an abnormal state has occurred, the chip will continue to operate within the preset judgment time. In abnormal states, such as output overload or output overcurrent, the power consumption of the switching power supply is very high, and the inductor current cannot discharge to zero, causing the current flowing through the power transistor to gradually accumulate. According to the formula P = I... 2 The power transistors and other components will generate a lot of heat. If the restart time is too short, the power transistors will not have enough time to dissipate heat. As the control chip restarts repeatedly, the switching power supply will continue to accumulate heat, which may cause the switching power supply to overheat and be damaged. Summary of the Invention

[0007] The purpose of this application is to provide a switching power supply and an automatic recovery control method for the protection of the switching power supply, which can prevent the switching power supply from being damaged by overheating.

[0008] To achieve the above objectives, this application provides the following solution:

[0009] In a first aspect, this application provides a switching power supply, which includes: a main power circuit module, a control chip, and an auxiliary power supply module;

[0010] The control chip is connected to the main power circuit module and the auxiliary power supply module respectively;

[0011] The control chip is used to detect the operating status of the switching power supply after normal waveform transmission; when an abnormal state is continuously detected within a preset judgment time, waveform transmission is stopped; after waveform transmission is stopped, when a preset condition is met, the control chip's power supply voltage is checked to see if it is higher than the threshold; if the control chip's power supply voltage is higher than the threshold, normal waveform transmission is resumed.

[0012] The preset conditions include:

[0013] The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage;

[0014] And / or,

[0015] The number of times the control chip restarts after a power failure reaches the automatic recovery restart count; the automatic recovery restart count is greater than 1.

[0016] Secondly, this application provides an automatic recovery control method for the protection of a switching power supply. This method is applied to a control chip in the switching power supply as described in the first aspect, and the method includes:

[0017] After normal waveform generation, the operating status of the switching power supply is checked;

[0018] If an abnormal state is continuously detected within a preset judgment time, the wave transmission will stop.

[0019] After the wave transmission stops, when the preset conditions are met, the system checks whether the power supply voltage of the control chip is higher than the activation threshold. If the power supply voltage of the control chip is higher than the activation threshold, normal wave transmission resumes.

[0020] The preset conditions include:

[0021] The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage;

[0022] And / or,

[0023] The number of times the control chip restarts after a power failure reaches the automatic recovery restart count; the automatic recovery restart count is greater than 1.

[0024] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0025] This application provides a switching power supply and an automatic recovery control method for its protection. The switching power supply includes a main power circuit module, a control chip, and an auxiliary power supply module. The control chip is connected to both the main power circuit module and the auxiliary power supply module. The control chip is used to detect the operating status of the switching power supply after normal signal transmission. When an abnormal state is continuously detected within a preset judgment time, signal transmission is stopped. After signal transmission stops, normal signal transmission resumes when preset conditions are met and the supply voltage of the control chip is higher than the activation threshold. The preset conditions include: the time after signal transmission stops reaches the automatic recovery time, the duration of the automatic recovery time is greater than the duration of a single restart after the control chip loses power; and / or, the number of restarts after the control chip loses power reaches the automatic recovery restart count; and the automatic recovery restart count is greater than 1. This disclosure addresses abnormal operating scenarios after the control chip triggers protection by reasonably setting preset conditions within the control chip, effectively solving the overheating problem under abnormal conditions. On the one hand, since the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage, and the number of automatic recovery restarts is greater than 1, even if the control chip is restarted continuously during the abnormal state, the switching power supply can avoid overheating due to frequent restarts, thus ensuring the safe operation of the switching power supply and preventing overheating damage. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a common flyback switching power supply circuit according to an embodiment of this application;

[0028] Figure 2 This is a schematic diagram of the structure of a switching power supply according to an exemplary embodiment;

[0029] Figure 3 This application illustrates the operating waveform of a prior art solution under abnormal conditions in one embodiment.

[0030] Figure 4 This is a schematic diagram of the internal circuitry of a control chip according to an embodiment of this application;

[0031] Figure 5 This is a schematic diagram of a startup circuit shown in one embodiment of this application;

[0032] Figure 6 A schematic diagram of a logic circuit shown in one embodiment of this application. Figure 1;

[0033] Figure 7 This is a waveform diagram illustrating an abnormal state restart operation according to an embodiment of this application;

[0034] Figure 8 This is a waveform diagram showing the operation after the VDD power-down time without logic processing, as illustrated in an embodiment of this application.

[0035] Figure 9 This is a waveform diagram showing the operation after the automatic recovery time has ended, as illustrated in an embodiment of this application;

[0036] Figure 10 A schematic diagram of a logic circuit shown in one embodiment of this application. Figure 2 ;

[0037] Figure 11 A schematic diagram of a logic circuit shown in one embodiment of this application. Figure 3 ;

[0038] Figure 12 This is a flowchart illustrating an automatic recovery control method for the protection of a switching power supply according to an exemplary embodiment. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] To address the aforementioned technical problems, this disclosure proposes a switching power supply and an automatic recovery control method for its protection. The switching power supply in this disclosure may include a flyback switching power supply. The solution in this disclosure is described in detail below.

[0042] Figure 1 This is a schematic diagram of a common flyback switching power supply circuit, such as... Figure 1 As shown, the flyback switching power supply includes a primary-side circuit, a secondary-side circuit, a control chip, and an auxiliary-side circuit.

[0043] The control chip includes: HV pin, DRV pin, VDD pin, FB pin, ZCD pin, CS pin, and GND pin, of which the GND pin is grounded;

[0044] The primary-side circuit mainly includes: primary winding Np, power transistor Q1, first resistor R1, first capacitor C1, first diode D1, and primary current sampling resistor R. CS 1. Current limiting resistor R0, phototransistor I1B, fifth capacitor C5, sixth capacitor C6, seventh resistor R7.

[0045] The opposite-named terminal of the primary winding Np is connected to the input voltage Vin of the flyback switching power supply, and the same-named terminal of the primary winding Np is connected to the drain of the power transistor Q1. The two ends of the primary winding Np are connected to R1, C1, and D1 to form an RCD spike absorption circuit. The source of the power transistor Q1 is connected to the primary current sampling resistor R. CS After grounding, the gate of power transistor Q1 is connected to the DRV pin of the control chip. The input voltage Vin is connected to the HV pin after passing through the current-limiting resistor R0, providing the start-up voltage for the chip. The emitter of phototransistor I1B is grounded, and the collector of phototransistor I1B is connected to the FB pin. One end of the fifth capacitor C5 is grounded, and the other end of the fifth capacitor C5 is connected between the collector of phototransistor I1B and the FB pin. One end of the sixth capacitor C6 is connected to the CS pin, and one end of the seventh resistor R7 is connected between the CS pin and the sixth capacitor C6. The other end of the seventh resistor R7 is connected to the primary-side current sampling resistor R. CS Between the source of power transistor Q1 and the source of power transistor Q1.

[0046] The secondary side circuit includes: secondary winding Ns, output rectifier D2, light-emitting diode I1A, output capacitor C2, second resistor R2, third sampling resistor R3, fourth sampling resistor R4, voltage regulator TL431, and third capacitor C3.

[0047] The opposite-named terminal of the secondary winding Ns is grounded, and the same-named terminal of the secondary winding Ns is connected to the anode of the output rectifier D2. The cathode of the output rectifier D2 is connected to the output voltage terminal of the flyback switching power supply. One end of the second resistor R2 is connected between the output rectifier D2 and the output voltage terminal of the flyback switching power supply, and the other end of R2 is connected to the anode of the LED I1A. The cathode of the LED I1A is connected to the cathode of the voltage regulator TL431, and the anode of the voltage regulator TL431 is grounded. One end of the output capacitor C2 is connected between one end of the second resistor R2 and the output voltage terminal of the flyback switching power supply. The other end of resistor 2 is grounded. One end of the third sampling resistor R3 is connected between one end of the output capacitor C2 and the output voltage terminal of the flyback switching power supply. The other end of the third sampling resistor R3 is connected to one end of the fourth sampling resistor R4. The other end of the fourth sampling resistor R4 is grounded. One end of the third capacitor C3 is connected between the cathode of the light-emitting diode I1A and the cathode of the voltage regulator TL431. The other end of the third capacitor C3 is connected between the third sampling resistor R3 and the fourth sampling resistor R4. The reference terminal of the voltage regulator TL431 is connected between one end of the fourth sampling resistor R4 and the other end of the third capacitor C3.

[0048] The output rectifier diode D2 provides the output voltage Vout of the flyback switching power supply. The output voltage Vout is input to the TL431 through sampling resistors R3 and R4, while the output current of the TL431 is fed back to the FB pin of the control chip through an optocoupler composed of LED I1A and phototransistor I1B.

[0049] The auxiliary side circuit includes: auxiliary winding Na, third diode D3, fourth capacitor C4, fifth sampling resistor R5 and sixth sampling resistor R6.

[0050] The same-name terminal of the auxiliary winding Na is connected to the anode of the third diode D3, and the cathode of the third diode D3 is connected to the VDD pin. One end of the fifth sampling resistor R5 is connected between the same-name terminal of the auxiliary winding Na and one end of the fifth sampling resistor R5. One end of the fourth capacitor C4 is connected between the cathode of the third diode D3 and the VDD pin, and the other end of the fourth capacitor C4 is grounded. The other end of the fifth sampling resistor R5 is connected to one end of the sixth sampling resistor R6, and the other end of the sixth sampling resistor R6 is grounded. The opposite-name terminal of the auxiliary winding Na, the ZCD pin, is connected between the fifth sampling resistor R5 and the sixth sampling resistor R6.

[0051] The auxiliary winding Na, diode D3, and capacitor C4 provide the power supply voltage VDD to the control chip. The opposite-named terminal of the auxiliary winding Na is grounded, and the same-named terminal of the auxiliary winding Na is connected to the fifth sampling resistor R5 and the sixth sampling resistor R6, inputting the sampled voltage signal to the ZCD pin to detect demagnetization information and output voltage.

[0052] Figure 2This is a schematic diagram of the structure of a switching power supply according to an exemplary embodiment, such as... Figure 2 As shown, the switching power supply includes: a main power circuit module, a control chip, and an auxiliary power supply module;

[0053] The control chip is connected to the main power circuit module and the auxiliary power supply module respectively;

[0054] The control chip is used to detect the operating status of the switching power supply after normal waveform transmission; when an abnormal state is continuously detected within a preset judgment time, waveform transmission is stopped; after waveform transmission is stopped, when a preset condition is met, the control chip's power supply voltage is checked to see if it is higher than the threshold; if the control chip's power supply voltage is higher than the threshold, normal waveform transmission is resumed.

[0055] The preset conditions include:

[0056] The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage;

[0057] And / or,

[0058] The number of times the control chip restarts after a power failure reaches the automatic recovery restart count; the automatic recovery restart count is greater than 1.

[0059] When the preset condition is that the time after the wave transmission stops reaches the automatic recovery time, the specific implementation method is as follows: after the wave transmission stops, the automatic recovery time is started; after the automatic recovery time is completed, normal wave transmission is resumed. The duration of the automatic recovery time is longer than the duration of one restart after the control chip loses power.

[0060] When the preset condition is that the number of times the control chip restarts after a power failure reaches the automatic restart limit, the specific implementation method is as follows:

[0061] After stopping wave transmission, start the automatic recovery restart count; after the automatic recovery restart count is full, resume normal wave transmission, where the number of automatic recovery restarts is greater than 1.

[0062] The main power circuit module in this embodiment includes the primary side circuit and secondary side circuit in the above embodiments, and the auxiliary side circuit is equivalent to the auxiliary side circuit in the above embodiments.

[0063] One existing technical solution clears the protection signal after the chip restarts, and its operating waveform is as follows: Figure 3 As shown, when the preset judgment time T PWhen an abnormal state is continuously detected internally, protection is triggered. The DRV pin of the control chip stops transmitting waveforms, and the supply voltage VDD drops to the shutdown threshold VDD_OFF, triggering the control chip to restart. Upon restarting, the protection signal is cleared, and the supply voltage VDD rises to the turn-on threshold VDD_ON. The control chip then resumes transmitting waveforms, and the time interval between stopping waveform transmissions is the time it takes for VDD to drop from VDD_OFF to VDD_ON and then recharge. This can also be referred to as the restart duration of the control chip after a power outage. This method may result in insufficient heat dissipation due to the short time. As the control chip restarts repeatedly, the switching power supply will continuously accumulate heat, which may eventually lead to severe overheating and damage to the switching power supply.

[0064] This disclosure sets preset conditions, at a preset judgment time T. P When an abnormal state is continuously detected internally, the DRV pin of the control chip will stop transmitting waves. After stopping transmission, the DRV pin will not immediately resume transmitting waves after the control chip restarts once it is powered off. Instead, it will wait until the preset conditions are met and the supply voltage of the control chip is higher than the threshold before the DRV pin resumes transmitting waves. Since the duration of the preset conditions is longer than the duration of the control chip restarting once it is powered off, the DRV pin will not resume transmitting waves when the preset conditions are not met, even if the control chip restarts continuously. This gives the components in the switching power supply (e.g., power transistor Q1) more time to dissipate heat and avoids the accumulation of heat in the switching power supply, which could lead to an excessively high temperature.

[0065] The preset condition is an automatic recovery time T. F At the preset judgment time T P When an abnormal state is continuously detected internally, the DRV pin of the control chip will stop transmitting waveforms. After stopping the waveform transmission, the DRV pin will not resume transmitting waveforms after the control chip is powered off and restarted; instead, it will wait until the automatic recovery time T. F After the process ends, and the supply voltage of the control chip is higher than the threshold, the DRV pin will re-emerge. Since the automatic recovery time is longer than the restart time of the control chip after a power outage, the automatic recovery time T... F During this period, although the control chip keeps restarting, the DRV pin will not resume emitting waves. This gives the components in the switching power supply (such as the power transistor Q1) more time to dissipate heat, thus preventing the power supply from overheating due to heat accumulation.

[0066] For example, T F It can be more than 2 times T P This allows for more sufficient heat dissipation time. (T) F =6T P For example, in the automatic recovery time T FDuring this period, the control chip restarts continuously, but the interval between wave transmissions is 6 times the power-off and restart time of VDD, allowing for more sufficient heat dissipation time and preventing heat accumulation that could lead to excessively high temperatures.

[0067] When the preset condition is to automatically recover the number of restarts, at the preset judgment time T P When an abnormal state is continuously detected internally, the DRV pin of the control chip will stop transmitting waveforms. After stopping the waveform transmission, the DRV pin will not retransmit waveforms after the control chip restarts once after a power failure. Instead, it will wait until the number of restarts after a power failure reaches the automatic recovery restart count, and the supply voltage of the control chip is higher than the turn-on threshold before the DRV pin retransmits waveforms. Since the number of automatic recovery restarts is greater than 1, that is, the time between the DRV pin retransmitting waveforms and the DRV pin stopping the waveform transmission will be greater than the time of a single restart after a power failure of the control chip. Therefore, if the number of restarts after a power failure of the control chip has not reached the automatic recovery restart count, although the control chip keeps restarting, the DRV pin will not resume transmitting waveforms. This gives the components in the switching power supply (e.g., power transistor Q1) more time to dissipate heat, avoiding the accumulation of heat in the switching power supply and causing the switching power supply temperature to become too high.

[0068] For example, the automatic recovery restart count can be more than 2 times, allowing for more sufficient heat dissipation time. Taking an automatic recovery restart count of 5 times as an example, even if the control chip restarts less than 5 times after a power outage, the control chip will continuously restart, but the wave transmission interval will be 5 times the power outage restart time, allowing for more sufficient heat dissipation time and preventing heat accumulation that could lead to overheating.

[0069] This disclosure addresses abnormal operating scenarios after the control chip triggers protection. During the duration of the abnormal state, by reasonably setting preset conditions within the control chip, the control chip can be continuously restarted without causing the switching power supply to overheat. Once the abnormal state is resolved, it automatically returns to normal operating status without manual intervention.

[0070] like Figure 4As shown, the control chip includes: a startup circuit, a protection circuit, a PWM (Pulse Width Modulation) comparator, a valley detection circuit, a logic circuit, and an RS flip-flop. The inputs of the startup circuit are connected to the HV and VDD pins, respectively. The output of the startup circuit is connected to the inputs of the protection circuit and the logic circuit. The negative input of the PWM comparator is connected to the FB pin. The positive input of the PWM comparator is connected to the CS pin. The input of the protection circuit is also connected to the FB pin. The outputs of the protection circuit and the PWM comparator are connected to the inputs of the logic circuit. The output of the logic circuit is connected to the R terminal of the RS flip-flop. The input of the valley detection circuit is connected to the ZCD pin. The output of the valley detection circuit is connected to the S terminal of the RS flip-flop. The Q terminal of the RS flip-flop is connected to the input of the drive circuit. The output of the drive circuit is connected to the DRV pin.

[0071] Flyback switching power supplies typically employ peak current control mode, and the non-inverting input of the PWM comparator is the current sampling resistor R. CS Primary current sampling signal V CS The inverting input of the PWM comparator is the feedback voltage V. FB V CS It is a sloped voltage signal with a positive gradient. When power transistor Q1 is turned on, V CS The voltage value continues to increase until it exceeds the feedback voltage V. FB When the PWM comparator outputs a high-level signal, it sets the output of the RS flip-flop to low, which in turn turns off the power transistor Q1 through the drive circuit.

[0072] The valley detection circuit is used to detect the resonant waveform of power transistor Q1. During normal operation, when power transistor Q1 is turned off, the inductance of the secondary winding begins to discharge and demagnetize. When the inductance current of the secondary winding drops to zero, the LC circuit formed by the inductance of the primary winding and the parasitic capacitance of the power transistor (not shown in the figure) begins to resonate. In a flyback switching power supply, the voltage waveform of the auxiliary winding changes in the same direction as the voltage waveform of the drain of power transistor Q1. Therefore, during the turn-off period of power transistor Q1, sampling the voltage of the ZCD pin can obtain the resonant voltage waveform. The sampled voltage of the ZCD pin is input to the valley detection circuit. Whenever the sampled voltage of the ZCD pin resonates to the valley, the valley detection circuit will immediately generate a quasi-resonant conduction signal. The quasi-resonant conduction signal is sent to the S terminal of the RS flip-flop, setting the output of the RS flip-flop to high. After passing through the drive circuit, the power transistor Q1 is turned on.

[0073] The startup circuit detects the VDD pin voltage. After the control chip stops transmitting waveforms, the auxiliary winding cannot supply power to VDD, so the VDD voltage gradually decreases. When the startup circuit detects that the VDD voltage is lower than the control chip's set turn-off threshold VDD_OFF, it charges VDD through the HV pin using the input voltage Vin until the VDD voltage exceeds the control chip's set turn-on threshold VDD_ON, at which point charging stops. The startup circuit then outputs a power undervoltage signal UVLO to the logic circuit, indicating that the control chip has completed a restart. Simultaneously, the startup circuit also detects the HV pin voltage. When the HV pin voltage is higher than the threshold voltage Brown-in, the startup circuit outputs BRN to the logic circuit, indicating that the input voltage meets the control chip's operating conditions.

[0074] The circuit diagram of the startup circuit is as follows: Figure 5 As shown, the startup circuit includes: comparator 1, comparator 2, switch S1, and a two-to-one multiplexer circuit;

[0075] The input voltage terminal of the switching power supply is connected to the HV pin of the control chip, the non-inverting input terminal of comparator 2 is connected to the HV pin of the control chip, the negative input terminal of comparator 2 is connected to the threshold voltage BRN_IN, and the output terminal of comparator 2 is the line voltage detection signal output terminal of the startup circuit, and the output signal is BRN.

[0076] The HV pin is also connected to the first terminal of switch S1, the second terminal of switch S1 is connected to the power supply voltage terminal VDD of the control chip, the control terminal of switch S1 is connected to the output terminal of comparator 1, and a current source I0 is set between the HV pin and switch S1.

[0077] The power supply voltage terminal VDD is also connected to the negative phase input terminal of comparator 1;

[0078] The first data input terminal of the 2-to-1 multiplexer is connected to the enable threshold VDD_ON, and the second data input terminal is connected to the disable threshold VDD_OFF. The control input terminal of the 2-to-1 multiplexer is connected to the output terminal of comparator 1, and the output terminal of the 2-to-1 multiplexer is connected to the non-inverting input terminal of comparator 1. The enable threshold VDD_ON is greater than the disable threshold VDD_OFF. In the 2-to-1 multiplexer, when the signal input to the control input terminal is high, VDD_ON is selected as the output, and vice versa. In the initial state, the 2-to-1 multiplexer outputs VDD_ON.

[0079] The output of comparator 1 is the undervoltage signal output of the startup circuit, and the output signal is UVLO;

[0080] Specifically, when the input voltage of the switching power supply is less than the threshold voltage BRN_IN, the line voltage detection signal BRN output by comparator 2 is at a low level; when the input voltage Vin of the switching power supply is not less than the threshold voltage BRN_IN, the line voltage detection signal BRN output by comparator 2 is at a high level.

[0081] When the supply voltage VDD is not greater than the threshold VDD_ON, the power supply undervoltage signal UVLO output by comparator 1 is a high level indicating that the control chip is undervoltage; when the supply voltage VDD is greater than the threshold VDD_ON, the power supply undervoltage signal output by comparator 1 is a low level indicating that the control chip is released from the power supply undervoltage.

[0082] Specifically, the negative input of comparator 1 is the VDD voltage, and the positive input is the output of a 2-to-1 multiplexer. The input signals of the multiplexer are the on-threshold VDD_ON and the off-threshold VDD_OFF, and the control signal is the undervoltage signal UVLO output by comparator 1. When the VDD voltage is lower than the off-threshold VDD_OFF, the output signal UVLO of comparator 1 is high, and the output of the multiplexer is the on-threshold VDD_ON. When the VDD voltage exceeds the on-threshold VDD_ON, the output signal UVLO of comparator 1 flips to low, and the output of the multiplexer is the off-threshold VDD_OFF. When the undervoltage signal UVLO is high, it indicates that the chip is underpowered, so switch S1 is closed, and the input voltage Vin charges VDD through the HV pin. The current source I0 can be implemented in various ways, such as a high-voltage resistor, a high-voltage junction field-effect transistor (JFET), or a high-voltage depletion-mode field-effect transistor. When the undervoltage signal UVLO is low, it indicates that the control chip has resolved the undervoltage issue, so switch S1 opens and HV stops charging VDD. The non-inverting input of comparator 2 is the sampling signal of the input voltage Vin, and the inverting input is the threshold voltage BRN_IN. When the sampling signal of the input voltage Vin is lower than the threshold voltage BRN_IN, the line voltage detection signal BRN output by comparator 2 is low, indicating that the input voltage is too low. The control chip will not enter normal operation until the sampling signal of the input voltage Vin is higher than the threshold voltage BRN_IN. At this point, the output BRN of comparator 2 is high, and the input voltage Vin meets the normal operating requirements of the control chip. Both the undervoltage signal UVLO and the line voltage detection signal BRN are fed into the logic circuit.

[0083] The protection circuit is used to detect abnormal operating states of the flyback switching power supply. Different abnormal states have different characteristics, and the protection circuit makes protection decisions by detecting these characteristic signals. For example, when there is an output overcurrent or output overload, the output current is very large, that is, the load is very heavy. At this time, the current flowing into the FB pin through the optocoupler feedback to the primary side decreases. The voltage value obtained at the FB pin is inversely proportional to the current, so the feedback voltage V... FB Increase. Feedback voltage V FB The larger the value, the heavier the load. Therefore, when the protection circuit detects the feedback voltage V... FB Exceeding the set threshold and continuing for a preset judgment time T P If the output is considered to be overcurrent or overloaded at this time, the output protection signal Pro will be sent to the logic circuit.

[0084] It is worth noting that the actual working conditions of a switching power supply are complex and diverse. Therefore, the protection behavior is not limited to output overcurrent, output overload, output overvoltage, abnormal overcurrent, and input undervoltage, but includes all abnormal states of all pins. The detection of abnormal states is similar to that in related technologies, and will not be elaborated here.

[0085] After the logic circuit detects the protection signal Pro output by the protection circuit, it starts the automatic recovery time T. F The timing process begins, and upon completion, a high-level signal is sent to the R terminal of the RS flip-flop, setting its output low. This, after passing through the drive circuit, turns off the power transistor Q1. The preset judgment time T for protection is typically used for this process. P The automatic recovery time is 60ms to 120ms. To ensure sufficient heat dissipation of the switching power supply, the automatic recovery time T is... F The timeout should be at least 1.2 seconds. Therefore, after the control chip triggers its protection, it will not operate for at least 1.2 seconds to allow heat to accumulate. If the abnormal state is resolved within the automatic recovery time, the control chip will resume normal operation after the next restart following the completion of the automatic recovery time. If the automatic recovery time T... F If the abnormal state is not resolved after the count is full, the control chip will enter the protection judgment process after restarting the ignition, and will determine the outcome within the preset judgment time T. P After the event ends, the protection mechanism is triggered, and the system automatically enters recovery mode, continuously cycling until the abnormal state is resolved.

[0086] In one embodiment, the logic circuit structure is as follows: Figure 6 As shown, the logic circuit includes: a first counting circuit, a first inverter inv1, a first NOR gate nor1, a first NAND gate nand1, and a second inverter inv2;

[0087] The first input terminal of the first counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the first counting circuit is connected to the clock signal, the output terminal of the first counting circuit is connected to the first input terminal of the first NOR gate NOR1, the signal output by the first counting circuit is the fault signal, and the signal output by the protection circuit is the protection signal Pro.

[0088] The line voltage detection signal output terminal of the startup circuit is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second input terminal of the first NOR gate NOR1.

[0089] The undervoltage signal output of the startup circuit is connected to the third input of the first NOR gate NOR1;

[0090] The output of the first NOR gate NOR1 is connected to the first input of the first NAND gate NAND1. The signal output by the first NOR gate NOR1 is the enable signal EN.

[0091] The output of the PWM comparator is connected to the input of the second inverter inv2, and the output of the second inverter inv2 is connected to the second input of the first NAND gate nand1.

[0092] The output of the first NAND gate (nand1) is connected to the R terminal of the RS flip-flop. The signal output by the first NAND gate (nand1) is the reset signal (Reset).

[0093] In this logic circuit, after the control chip stops transmitting waves, the protection signal Pro output by the protection circuit is high, the fault signal Fault output by the first counting circuit is high, and the first counting circuit starts the automatic recovery time T. F During timing, the fault signal remains high until the timing ends. The fault signal is sent to the R terminal of the RS flip-flop, setting its output low. After passing through the driver circuit, the power transistor Q1 is turned off. The automatic recovery time T... F When the count is full, the fault signal goes low. When the fault signal goes high, the enable signal EN output by the first NOR gate NOR1 goes low, the reset signal Reset output by the first NAND gate NAND1 goes high, and the DRV pin stops transmitting. When the fault signal goes low, the DRV pin resumes normal transmission.

[0094] The transmission and processing flow of signals under abnormal conditions is clarified, enabling the switching power supply to stop transmitting signals in a timely manner when an abnormality occurs, and to accurately resume transmitting signals when the recovery conditions are met. This ensures the orderly implementation of the protection and recovery functions of the switching power supply, enhances the switching power supply's ability to cope with abnormal situations, and improves the stability of the switching power supply's operation.

[0095] Specifically, the input of the first inverter inv1 is the line voltage detection signal BRN, and its output is sent to the second input of the first NOR gate nor1. The input of the first counting circuit is the protection signal Pro and the clock signal clk, and its output is the fault signal, which is sent to the first input of the first NOR gate nor1. The signal at the third input of the first NOR gate nor1 is the undervoltage signal UVLO, and the output signal of the first NOR gate nor1 is the enable signal EN, which is sent to the first input of the first AND gate nand1. The input of the second inverter inv2 is the output signal cpm of the PWM comparator, and the output of the second inverter inv2 is sent to the second input of the first AND gate nand1. The reset signal Reset output of the first NAND gate nand1 is sent to the R terminal of the RS flip-flop.

[0096] When the control chip is working normally, the protection signal Pro is low, so the fault signal output by the first counting circuit is low; the line voltage detection signal BRN is high, so the output of the first inverter inv1 is low, and the power supply undervoltage signal UVLO is low. That is, all three input signals of the first NOR gate nor1 are low, so the enable signal EN output by the first NOR gate nor1 is high, indicating that the control chip is in normal working condition. The first input of the first NAND gate nand1 is always high, so its output reset signal Reset is determined by cpm. At this time, the control chip generates a normal waveform. When the power transistor Q1 is turned on, as the current in the primary side circuit continuously increases, the current sampling signal V... CS Exceeding the feedback voltage V FB Afterwards, the PWM comparator outputs a high-level CPM signal, so Reset is also high-level, and the RS flip-flop outputs a low-level signal. After passing through the drive circuit, the power transistor Q1 is turned off. When the secondary winding begins to resonate after demagnetization, the valley detection circuit controls the RS flip-flop output to be high-level. After passing through the drive circuit, the power transistor Q1 is turned on at the valley, and the switching action is repeated continuously.

[0097] As can be seen from the above analysis, in the technical solution provided in this disclosure, after the control chip triggers protection, the protection signal Pro is at a high level, and the abnormal state signal Fault is also at a high level. Furthermore, even if the protection signal Pro goes low before the timer ends, the abnormal state signal Fault will not go low and must remain high for the automatic recovery time T. F The fault signal will only go low after the count is full. When the fault signal is high, the enable signal EN from the first NOR gate (nor1) goes low, and the Reset signal from the first NAND gate (nand1) goes high, stopping the control chip from transmitting waveforms. The operating waveform is as follows: Figure 7 As shown, after the control chip enters an abnormal state, in order to avoid accidental activation of the protection mechanism, a preset judgment time T is required.P The protection mechanism is triggered only if an abnormal state is continuously detected within this period, after a preset judgment time T. P Afterwards, the protection signal Pro goes high, the DRV terminal stops transmitting waveforms, and the abnormal status signal Fault goes high. It is necessary to wait until the automatic recovery time T. F The signal is released only after the count is full. After the DRV pin stops transmitting, the VDD voltage continuously decreases due to the lack of auxiliary winding power supply. When it falls below the turn-off threshold VDD_OFF, UVLO is triggered to go high, the control chip restarts, clears the protection signal Pro to zero, and charges VDD using the input voltage Vin through the HV pin. Charging stops when the VDD voltage exceeds the turn-on threshold VDD_ON. Since the fault signal is still high at this time, the enable signal EN of the control chip is low, and the control chip will not transmit a signal. Therefore, during the automatic recovery time T... F During this period, the control chip restarts continuously, but the interval between wave transmissions is the time required for multiple VDD power outages and restarts, allowing for more sufficient heat dissipation and preventing heat accumulation that could lead to excessively high temperatures.

[0098] Combination Figure 3 and Figure 7 Assuming Figure 7 The VDD power-off and restart occurred 6 times. Figure 3 The DRV transmission interval is the time it takes for VDD to restart after a power outage (e.g., 200ms), while Figure 7 Automatic recovery time T was introduced. F (For example, 1.2S, or 1200ms) control, with an automatic recovery time T F Internally, although VDD repeatedly powered off and restarted approximately six times, DRV did not emit any waveforms, thus generating no additional system power consumption or heat. Compared to traditional control methods, the DRV waveform interval became T. F Time. T F The longer the time, the larger the DRV transmission interval, and the lower the overall power consumption and heat generation. Generally, T is set... F The time is 1.2S to 2S.

[0099] In the above embodiment, the automatic recovery time T is waited for... F When the fault signal goes low, the control chip does not immediately send a waveform. It needs to monitor the supply voltage VDD and the input voltage Vin. If the supply voltage VDD and input voltage Vin are not monitored, and the control chip sends a waveform immediately after the fault is cleared, an error may occur. The waveform is as follows. Figure 8 As shown. Automatic recovery time T FAfter the abnormal state of the control chip is resolved, it immediately resumes normal operation and starts transmitting waveforms. However, at this time, the supply voltage VDD is close to the turn-off threshold VDD_OFF. Under light load, the control chip transmits waveforms at a very low frequency, and the supply voltage VDD continues to drop below the turn-off threshold VDD_OFF. The control chip then stops transmitting waveforms again, waiting for the HV pin to charge the supply voltage VDD until it reaches the turn-on threshold VDD_ON before resuming normal operation. This situation will result in an automatic recovery time T. F After the process ended, the system restarted after a short period of operation due to another power outage on VDD, giving users the impression of system instability and abnormal power loss, thus affecting the customer's user experience.

[0100] To avoid this situation, in this disclosure, when detecting that preset conditions are met and resuming normal wave transmission, the control chip is specifically used for:

[0101] After detecting that the preset conditions are met, the power supply voltage of the control chip is detected;

[0102] Normal waveform transmission resumes when the supply voltage is higher than the activation threshold.

[0103] Specifically, the automatic recovery time T F After completion, the control chip needs to detect the supply voltage VDD and the input voltage Vin to resume waveform transmission. Its operating waveform is as follows: Figure 9 As shown. After the fault signal goes low, the control chip will resume transmitting signals only after the power supply voltage VDD exceeds the turn-on threshold VDD_ON during the next restart.

[0104] Further reference Figure 8 Additionally, the input voltage Vin and the automatic recovery time T can also be considered. F After the abnormal state of the control chip is resolved, it immediately resumes normal operation and starts transmitting waves. However, at this time, the supply voltage VDD is close to the turn-off threshold VDD_OFF. The control chip transmits waves at a very low frequency under light load, and the input voltage Vin is also relatively low. This results in insufficient energy supply from the auxiliary winding to VDD. The supply voltage VDD continues to drop below the turn-off threshold VDD_OFF, and the control chip stops transmitting waves again, waiting for the HV pin to charge the supply voltage VDD. Once the supply voltage VDD reaches the turn-on threshold VDD_ON, it resumes normal operation. This situation also causes the system to restart after a short period of operation due to VDD power failure after the automatic recovery time TF ends. This gives users the feeling of system instability and abnormal power failure, affecting the customer's user experience.

[0105] To avoid this situation, the transmission will not be resumed directly when the supply voltage is higher than the threshold. Instead, normal transmission will only resume when the supply voltage is also higher than the threshold.

[0106] Specifically, the automatic recovery time T F After completion, the control chip needs to detect the supply voltage VDD and the input voltage Vin to resume waveform transmission. Its operating waveform is as follows: Figure 9 As shown. After the fault signal goes low, the system waits for the control chip to restart. Once the supply voltage VDD exceeds the threshold voltage VDD_ON, the undervoltage signal UVLO goes low, and the input voltage Vin is then detected. Since the input voltage Vin is an AC voltage, it may be lower than the threshold voltage BRN_IN when the control chip restarts. Therefore, the system waits until the input voltage Vin exceeds the threshold voltage BRN_IN. To prevent the supply voltage VDD from dropping too much during this period, the supply voltage VDD is recharged when the line voltage detection signal BRN flips to a high level. At the same time, the enable signal EN goes high, and the control chip resumes transmitting waveforms.

[0107] The automatic recovery timer circuit in this disclosure can be implemented in several ways. A common approach is to use a D flip-flop combined with a clock signal to achieve fixed-time timing. Alternatively, logic circuitry can be used to limit the number of automatic recovery restarts. For example, if a VDD power failure restart requires 200ms, then 6 restarts would yield a 1.2s time. The specific time depends on the size of the VDD capacitor and the charging / discharging current. The control chip internally uses logic circuitry to count the number of automatic recovery restarts. Only after the preset number of restarts is reached is the fault signal allowed to be released. Therefore, the time during which the chip stops transmitting signals is the automatic recovery time TF. The specific logic circuitry is as follows... Figure 10 As shown: The logic circuit includes: a third counting circuit, a third inverter inv3, a second NOR gate nor2, a second NAND gate nand2, and a fourth inverter inv4;

[0108] The first input terminal of the third counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the third counting circuit is connected to the power undervoltage signal output terminal of the startup circuit, and the output terminal of the third counting circuit is connected to the first input terminal of the second NOR gate NOR2.

[0109] The line voltage detection signal output of the startup circuit is connected to the input of the third inverter, and the output of the third inverter is connected to the second input of the second NOR gate NOR2.

[0110] The undervoltage signal output of the startup circuit is also connected to the third input of the second NOR gate NOR2;

[0111] The output of the second NOR gate NOR2 is connected to the first input of the second NAND gate NAND2.

[0112] The output of the PWM comparator is connected to the input of the fourth inverter inv4, and the output of the fourth inverter inv4 is connected to the second input of the second NAND gate nand2.

[0113] The output of the second NAND gate nand2 is connected to the R terminal of the RS flip-flop.

[0114] exist Figure 10 In the control chip, a third counting circuit counts the number of UVLO restarts. Only after the preset number of restarts is reached is the fault signal allowed to be cleared. Therefore, the time during which the control chip stops transmitting signals can also be called the automatic recovery time T. F .

[0115] Another implementation method can be to combine fixed-time timing with automatic recovery restart count, that is, to use automatic recovery time T. F In conjunction with the automatic recovery restart count, at this time, Figure 6 Based on this, the logic circuit also includes: a second counting circuit and an AND gate, such as Figure 11 As shown,;

[0116] The output of the first counting circuit is connected to the first input of the AND gate;

[0117] The power undervoltage signal output terminal of the startup circuit is connected to the input terminal of the second counting circuit, and the output terminal of the second counting circuit is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the first input terminal of the first NOR gate NOR1, and the output terminal of the AND gate outputs the fault signal.

[0118] When the control chip stops transmitting waves, the protection signal output by the protection circuit is high, the first counting circuit outputs low, the fault signal is high, the first counting circuit starts the automatic recovery timer, and the second counting circuit counts the number of automatic recovery restarts of the undervoltage signal UVLO. When the automatic recovery time is full and the number of automatic recovery restarts meets the preset number, the fault signal goes low.

[0119] Specifically, after each protection trigger, the first counting circuit times the clock signal clk. The fault signal is only allowed to be cleared after the automatic recovery time (e.g., 1.2 seconds) is reached. Simultaneously, the second counting circuit counts the number of automatic recovery restarts of the UVLO after the protection trigger. After the first counting circuit reaches the automatic recovery time, the second counting circuit's count requirement for the number of automatic recovery restarts of the UVLO must also be met (e.g., the fault signal can be cleared after the 7th restart). If the actual application uses a large VDD capacitor, resulting in a long UVLO restart time, and the automatic recovery time is reached before the count requirement is met, then it is necessary to wait for the UVLO to reach the required number of automatic recovery restarts before clearing the fault signal. Conversely, if the actual application uses a small VDD capacitor, resulting in a long UVLO restart time, and the automatic recovery time is not reached after the count requirement is met, then it is necessary to wait for the automatic recovery time to be reached before clearing the fault signal.

[0120] The second counting circuit counts the number of restarts caused by the power supply undervoltage signal, and combined with the first counting circuit to time the automatic recovery time, the automatic recovery condition judgment of the switching power supply is more comprehensive and accurate. By taking into account both time and the number of restarts, the shortcomings that may be caused by a single condition judgment are avoided, the automatic recovery function of the switching power supply is further optimized, and its ability to adapt to complex working environments is improved.

[0121] Figure 12 This is a flowchart illustrating an automatic recovery control method for the protection of a switching power supply according to an exemplary embodiment, such as... Figure 12 As shown, this method is applied to a control chip in a switching power supply as described in any of the above embodiments, and the method includes the following steps S101-S103:

[0122] In step S101, after normal waveform generation, the operating status of the switching power supply is detected.

[0123] In step S102, when an abnormal state is continuously detected within a preset determination time, the wave transmission stops.

[0124] In step S103, after stopping the wave transmission, when a preset condition is met, it is detected whether the power supply voltage of the control chip is higher than the activation threshold. When the power supply voltage of the control chip is higher than the activation threshold, normal wave transmission is resumed.

[0125] The preset conditions include:

[0126] The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage;

[0127] And / or,

[0128] The number of times the control chip restarts after a power failure reaches the automatic recovery restart count; the automatic recovery restart count is greater than 1.

[0129] In one embodiment, resuming normal waveform transmission when the supply voltage is higher than the activation threshold includes:

[0130] Detect the input voltage of the switching power supply;

[0131] Normal waveform transmission resumes when the input voltage is detected to be greater than the threshold voltage and the supply voltage is higher than the activation threshold.

[0132] In one embodiment, the control chip includes: a startup circuit, a protection circuit, a PWM comparator, a valley detection circuit, a logic circuit, and an RS flip-flop; it also includes: an HV pin, a DRV pin, a VDD pin, an FB pin, a ZCD pin, and a CS pin;

[0133] The input terminals of the startup circuit are connected to the HV pin and the VDD pin respectively; the output terminal of the startup circuit is connected to the input terminals of the protection circuit and the logic circuit.

[0134] The negative input of the PWM comparator is connected to the FB pin; the positive input of the PWM comparator is connected to the CS pin.

[0135] The output of the protection circuit and the output of the PWM comparator are connected to the logic circuit, and the output of the logic circuit is connected to the R terminal of the RS flip-flop.

[0136] The input terminal of the valley detection circuit is connected to the ZCD pin, and the output terminal of the valley detection circuit is connected to the S terminal of the RS flip-flop.

[0137] The Q terminal of the RS flip-flop is connected to the DRV terminal.

[0138] In one embodiment, the logic circuit includes: a first counting circuit, a first inverter inv1, a first NOR gate nor1, a first NAND gate nand1, and a second inverter inv2.

[0139] The first input terminal of the first counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the first counting circuit is connected to the clock signal, and the output terminal of the first counting circuit is connected to the first input terminal of the first NOR gate NOR1.

[0140] The line voltage detection signal output terminal of the startup circuit is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second input terminal of the first NOR gate NOR1.

[0141] The undervoltage signal output of the startup circuit is connected to the third input of the first NOR gate NOR1;

[0142] The output of the first NOR gate NOR1 is connected to the first input of the first NAND gate NAND1.

[0143] The output of the PWM comparator is connected to the input of the second inverter inv2, and the output of the second inverter inv2 is connected to the second input of the first NAND gate nand1.

[0144] The output of the first NAND gate (nand1) is connected to the R terminal of the RS flip-flop.

[0145] In one embodiment, after the control chip stops transmitting waves, the protection signal output by the protection circuit is high, the fault signal output by the first counting circuit is high, the first counting circuit starts the automatic recovery timer, and after the automatic recovery timer is full, the fault signal becomes low.

[0146] When the fault signal is high, the enable signal EN output by the first NOR gate NOR1 is low, the reset signal Reset output by the first NAND gate NAND1 is high, and the DRV pin stops transmitting. When the fault signal is low, the DRV pin resumes normal transmission.

[0147] In one embodiment, the logic circuit further includes: a second counting circuit and an AND gate;

[0148] The output of the first counting circuit is connected to the first input of the AND gate;

[0149] The power undervoltage signal output terminal of the startup circuit is connected to the input terminal of the second counting circuit, and the output terminal of the second counting circuit is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the first input terminal of the first NOR gate NOR1, and the output terminal of the AND gate outputs the fault signal.

[0150] When the control chip stops transmitting waves, the protection signal output by the protection circuit is high, the first counting circuit outputs low, the fault signal is high, the first counting circuit starts the automatic recovery timer, and the second counting circuit counts the number of automatic recovery restarts of the undervoltage signal UVLO. When the automatic recovery time is full and the number of automatic recovery restarts meets the preset number, the fault signal goes low.

[0151] In this disclosure, after the control chip detects an abnormal state, it enters the protection determination stage, and within a preset determination time T... PIf the internal abnormal state persists, protection is triggered. The control chip stops transmitting waves, enters automatic recovery mode, and begins timing. Even if the protection signal is cleared, wave transmission will cease until the automatic recovery time is completed. After timing is complete, the power supply is continuously monitored for abnormalities. If normal, the control chip resumes transmitting waves, restoring normal operation. If the abnormal state is not resolved, the wave transmission duration is determined for a time T. P Then the protection is triggered again to stop transmitting waves, and this process is repeated until the abnormal state is resolved.

[0152] In one embodiment, the logic circuit includes: a third counting circuit, a third inverter inv3, a second NOR gate nor2, a second NAND gate nand2, and a fourth inverter inv4;

[0153] The first input terminal of the third counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the third counting circuit is connected to the power undervoltage signal output terminal of the startup circuit, and the output terminal of the third counting circuit is connected to the first input terminal of the second NOR gate NOR2.

[0154] The line voltage detection signal output of the startup circuit is connected to the input of the third inverter, and the output of the third inverter is connected to the second input of the second NOR gate NOR2.

[0155] The undervoltage signal output of the startup circuit is also connected to the third input of the second NOR gate NOR2;

[0156] The output of the second NOR gate NOR2 is connected to the first input of the second NAND gate NAND2.

[0157] The output of the PWM comparator is connected to the input of the fourth inverter inv4, and the output of the fourth inverter inv4 is connected to the second input of the second NAND gate nand2.

[0158] The output of the second NAND gate nand2 is connected to the R terminal of the RS flip-flop.

[0159] In one embodiment, the main power circuit module includes a primary-side circuit and a secondary-side circuit, and the auxiliary power supply module includes an auxiliary-side circuit.

[0160] The primary-side circuit includes: primary winding, primary power transistor, and phototransistor;

[0161] The opposite-named terminal of the primary winding is connected to the input voltage of the switching power supply, the same-named terminal of the primary winding is connected to the drain of the power transistor, the source of the primary power transistor is connected to the CS pin, the gate of the primary power transistor is connected to the DRV pin, and the input voltage is connected to the HV pin.

[0162] The secondary-side circuit includes: a secondary winding and a light-emitting diode;

[0163] The opposite-named terminal of the secondary winding is grounded, and the same-named terminal of the secondary winding provides the output voltage; the light-emitting diode and the phototransistor form an optocoupler, with the light-emitting diode connected to the output voltage and the phototransistor connected to the FB pin;

[0164] The auxiliary side circuit includes: an auxiliary winding and a sampling resistor;

[0165] The opposite-named end of the auxiliary winding is grounded, and the same-named end of the auxiliary winding is connected to the VDD pin. The same-named end of the auxiliary winding is also connected to the ZCD pin through a sampling resistor.

[0166] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0167] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A switching power supply, characterized in that, The switching power supply includes: a main power circuit module, a control chip, and an auxiliary power module; The control chip is connected to the main power circuit module and the auxiliary power supply module respectively; The control chip is used to detect the operating status of the switching power supply after normal waveform transmission; when an abnormal state is continuously detected within a preset judgment time, waveform transmission is stopped; after waveform transmission is stopped, when a preset condition is met, the control chip's power supply voltage is checked to see if it is higher than the threshold; if the control chip's power supply voltage is higher than the threshold, normal waveform transmission is resumed. The preset conditions include: The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage; And / or, The number of times the control chip restarts after a power failure reaches the automatic recovery restart limit; the number of automatic recovery restarts is greater than 1. The control chip includes: a startup circuit, a protection circuit, a PWM comparator, a valley detection circuit, logic circuits, and an RS flip-flop; it also includes: HV pin, DRV pin, VDD pin, FB pin, ZCD pin, and CS pin. The input terminals of the startup circuit are connected to the HV pin and the VDD pin respectively; the output terminal of the startup circuit is connected to the input terminals of the protection circuit and the logic circuit. The negative input of the PWM comparator is connected to the FB pin; the positive input of the PWM comparator is connected to the CS pin. The output of the protection circuit and the output of the PWM comparator are connected to the logic circuit, and the output of the logic circuit is connected to the R terminal of the RS flip-flop. The input terminal of the valley detection circuit is connected to the ZCD pin, and the output terminal of the valley detection circuit is connected to the S terminal of the RS flip-flop. The Q terminal of the RS flip-flop is connected to the DRV terminal.

2. The switching power supply according to claim 1, characterized in that, In terms of restoring normal waveform transmission when the supply voltage of the control chip is higher than the threshold, the control chip is specifically used for: Detect the input voltage of the switching power supply; Normal waveform transmission resumes when the input voltage is detected to be greater than the threshold voltage and the supply voltage is higher than the activation threshold.

3. The switching power supply according to claim 1, characterized in that, The logic circuit includes: a first counting circuit, a first inverter, a first NOR gate, a first NAND gate, and a second inverter; The first input terminal of the first counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the first counting circuit is connected to the clock signal, and the output terminal of the first counting circuit is connected to the first input terminal of the first NOR gate. The line voltage detection signal output terminal of the startup circuit is connected to the input terminal of the first inverter, and the output terminal of the first inverter is connected to the second input terminal of the first NOR gate. The undervoltage signal output of the startup circuit is connected to the third input of the first NOR gate; The output of the first NOR gate is connected to the first input of the first NAND gate; The output of the PWM comparator is connected to the input of the second inverter, and the output of the second inverter is connected to the second input of the first NAND gate. The output of the first NAND gate is connected to the R terminal of the RS flip-flop.

4. The switching power supply according to claim 3, characterized in that, After the control chip stops transmitting waves, the protection signal output by the protection circuit is high, the fault signal output by the first counting circuit is high, the first counting circuit starts the automatic recovery timer, and after the automatic recovery timer is full, the fault signal becomes low. When the fault signal is high, the enable signal EN output from the first NOR gate is low, the reset signal Reset output from the first NAND gate is high, and the DRV pin stops transmitting waveforms; when the fault signal is low, the DRV pin resumes normal waveform transmission.

5. The switching power supply according to claim 3, characterized in that, The logic circuit also includes: a second counting circuit and an AND gate; The output of the first counting circuit is connected to the first input of the AND gate; The power undervoltage signal output terminal of the startup circuit is connected to the input terminal of the second counting circuit, and the output terminal of the second counting circuit is connected to the second input terminal of the AND gate; the output terminal of the AND gate is connected to the first input terminal of the first NOR gate NOR1, and the output terminal of the AND gate outputs the fault signal. When the control chip stops transmitting waves, the protection signal output by the protection circuit is high, the first counting circuit outputs low, the fault signal is high, the first counting circuit starts the automatic recovery timer, and the second counting circuit counts the number of automatic recovery restarts of the undervoltage signal UVLO. When the automatic recovery time is full and the number of automatic recovery restarts meets the preset number, the fault signal goes low.

6. The switching power supply according to claim 1, characterized in that, The logic circuit includes: a third counting circuit, a third inverter, a second NOR gate, a second NAND gate, and a fourth inverter; The first input terminal of the third counting circuit is connected to the output terminal of the protection circuit, the second input terminal of the third counting circuit is connected to the power undervoltage signal output terminal of the startup circuit, and the output terminal of the third counting circuit is connected to the first input terminal of the second NOR gate. The line voltage detection signal output of the startup circuit is connected to the input of the third inverter, and the output of the third inverter is connected to the second input of the second NOR gate. The undervoltage signal output of the startup circuit is also connected to the third input of the second NOR gate; The output of the second NOR gate is connected to the first input of the second NAND gate; The output of the PWM comparator is connected to the input of the fourth inverter, and the output of the fourth inverter is connected to the second input of the second NAND gate. The output of the second NAND gate is connected to the R terminal of the RS flip-flop.

7. The switching power supply according to claim 1, characterized in that, The main power circuit module includes a primary side circuit and a secondary side circuit, and the auxiliary power module includes an auxiliary side circuit. The primary-side circuit includes: primary winding, primary power transistor, and phototransistor; The opposite-named terminal of the primary winding is connected to the input voltage of the switching power supply, the same-named terminal of the primary winding is connected to the drain of the power transistor, the source of the primary power transistor is connected to the CS pin, the gate of the primary power transistor is connected to the DRV pin, and the input voltage is connected to the HV pin. The secondary-side circuit includes: a secondary winding and a light-emitting diode; The opposite-named terminal of the secondary winding is grounded, and the same-named terminal of the secondary winding provides the output voltage; the light-emitting diode and the phototransistor form an optocoupler, with the light-emitting diode connected to the output voltage and the phototransistor connected to the FB pin; The auxiliary side circuit includes: an auxiliary winding and a sampling resistor; The opposite-named end of the auxiliary winding is grounded, and the same-named end of the auxiliary winding is connected to the VDD pin. The same-named end of the auxiliary winding is also connected to the ZCD pin through a sampling resistor.

8. A method for automatic recovery control of protection in a switching power supply, characterized in that, The method is applied to a control chip in a switching power supply as described in any one of claims 1-7, and the method includes: After normal waveform generation, the operating status of the switching power supply is checked; If an abnormal state is continuously detected within a preset judgment time, the wave transmission will stop. After the wave transmission stops, when the preset conditions are met, the system checks whether the power supply voltage of the control chip is higher than the activation threshold. If the power supply voltage of the control chip is higher than the activation threshold, normal wave transmission resumes. The preset conditions include: The time after the wave transmission stops reaches the automatic recovery time, and the duration of the automatic recovery time is longer than the time it takes for the control chip to restart after a power outage; And / or, The number of times the control chip restarts after a power failure reaches the automatic recovery restart limit; the number of automatic recovery restarts is greater than 1. The control chip includes: a startup circuit, a protection circuit, a PWM comparator, a valley detection circuit, a logic circuit, and an RS flip-flop; it also includes: HV pin, DRV pin, VDD pin, FB pin, ZCD pin, and CS pin. The input terminals of the startup circuit are connected to the HV pin and the VDD pin respectively; the output terminal of the startup circuit is connected to the input terminals of the protection circuit and the logic circuit. The negative input of the PWM comparator is connected to the FB pin; the positive input of the PWM comparator is connected to the CS pin. The output of the protection circuit and the output of the PWM comparator are connected to the logic circuit, and the output of the logic circuit is connected to the R terminal of the RS flip-flop. The input terminal of the valley detection circuit is connected to the ZCD pin, and the output terminal of the valley detection circuit is connected to the S terminal of the RS flip-flop. The Q terminal of the RS flip-flop is connected to the DRV terminal.

9. The method according to claim 8, characterized in that, The step of restoring normal waveform transmission when the power supply voltage of the control chip is higher than the activation threshold includes: Detect the input voltage of the switching power supply; Normal waveform transmission resumes when the input voltage is detected to be greater than the threshold voltage and the supply voltage is higher than the activation threshold.

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