A low-complexity dq voltage acquisition method

Abstract

This invention discloses a method for obtaining dq voltage with low computational complexity, comprising the following steps: selecting a signal conditioning circuit, which is composed of a voltage divider circuit and a filter circuit cascaded together; deriving the transfer function corresponding to the signal conditioning circuit; selecting the parameters of the voltage divider circuit according to the voltage division ratio, and selecting the parameters of the filter circuit according to the frequency of the conditioned signal; deriving the corresponding discrete transfer function and time-domain difference equation based on the transfer function to obtain the signal recovery equation; sampling the output side of the three-phase signal conditioning circuit to obtain the three phases, respectively; performing a Clark transform on the sampled phases to obtain the sum of the voltages at the sampling time and several previous sampling times, and feeding the results at the sampling time and several previous sampling times into the signal recovery equation to obtain the true voltage sum at the sampling time, and then performing a Park transform to obtain the true dq voltage. This invention can obtain more accurate dq voltage, improve the observation accuracy without a position controller, and has the advantages of simple calculation, high implementation accuracy, and strong hardware versatility.

Description

Technical Field

[0001] This invention relates to the field of positionless control of permanent magnet synchronous motors, and specifically to a method for obtaining the dq voltage with low computational complexity. Background Technology

[0002] In the field of positionless control of permanent magnet synchronous motors, the motor's dq voltage is often used as the input of the positionless observer. There are many ways to obtain the dq voltage; a common method is to use the voltage setpoint from the previous cycle as the feedback value for the current cycle. However, due to dead time and the nonlinearity of the inverter, there is an error between the setpoint voltage and the actual phase voltage that cannot be accurately calculated. Furthermore, this error accounts for a large proportion when the synchronous motor is operating at low speeds, which can seriously affect control performance.

[0003] Existing sampling methods often reconstruct target voltage or current information by sampling and calculating the duty cycle of the PWM signal. Some patented solutions require combining high-performance ADCs and complex DSP operations, placing high demands on MCU computing resources. Furthermore, because they ignore the changes in PWM signal amplitude under bus voltage fluctuations, they are difficult to reconstruct the true signal waveform in scenarios with unstable power supply voltages or significant interference.

[0004] Alternatively, a filter with a cutoff frequency close to the switching frequency can be added to the circuit, and the phase voltage signal can be acquired via an ADC. This method can obtain a more realistic voltage signal with minimal increase in computation. However, the sampled signal still contains a certain amount of switching noise, limiting its improvement in control. Summary of the Invention

[0005] The purpose of this invention is to provide a method for obtaining dq voltage with low computational complexity, which can obtain more accurate dq voltage, thereby improving the observation accuracy without a position controller and improving dynamic and steady-state performance.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A method for obtaining dq voltage with low computational complexity includes the following steps:

[0008] (1) Select a signal conditioning circuit, which is composed of a voltage divider circuit and a filter circuit cascaded together; the signal conditioning circuit has and , This is the three-phase voltage output from the driver to the motor; The voltage fed into the MCU's ADC is The result after voltage divider filtering;

[0009] (2) Based on the selected signal conditioning circuit, derive the transfer function corresponding to the signal conditioning circuit;

[0010] (3) Select the parameters of the voltage divider circuit according to the voltage division ratio, and select the parameters of the filter circuit according to the frequency of the conditioned signal; and derive the corresponding discrete transfer function and time-domain difference equation based on the transfer function in step (2) to obtain... Signal recovery equation;

[0011] (4) During one motor control cycle, the three-phase signal conditioning circuit samples the three phase signals to obtain the three phase signals. As respectively ;right Perform Clark transformation to obtain and The results of the sampling time and several previous sampling times are sent to step (3). The signal recovery equations yield the actual voltage at each sampling moment. and Then, by performing the Park transformation, the actual dq voltage can be obtained.

[0012] Furthermore, the signal conditioning circuit is selected as a type I signal conditioning circuit, which consists of a voltage divider circuit and... It is composed of cascaded filter circuits;

[0013] The transfer function corresponding to the first type of signal conditioning circuit is:

[0014]

[0015] In the formula, For continuous complex frequency domain complex numbers

[0016] In the formula, the time constant for

[0017]

[0018] In the formula, voltage gain for

[0019]

[0020] In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type of filter circuit resistor; for Type-type filter circuit capacitor; The imaginary unit, ; For frequency.

[0021] Furthermore, the cutoff frequency corresponding to the first type of signal conditioning circuit for:

[0022] .

[0023] Furthermore, the discrete transfer function corresponding to the first type of signal conditioning circuit is:

[0024]

[0025] In the formula, Sampling time, It is a discrete frequency domain complex number;

[0026] In the formula, The transfer function in the continuous frequency domain. The transfer function in the discrete frequency domain. For discrete frequency domain output, For discrete frequency domain input;

[0027] The time-domain difference equation corresponding to the first type of signal conditioning circuit is, i.e. The signal recovery equation is:

[0028]

[0029] In the formula, for The input value at the sampling time, for The output value at the sampling time.

[0030] Furthermore, the signal conditioning circuit is selected as a type II signal conditioning circuit, which consists of a voltage divider circuit and... It is composed of cascaded filter circuits;

[0031] The transfer function corresponding to the second type of signal conditioning circuit is:

[0032]

[0033] Right now,

[0034] In the formula, For continuous complex numbers in the frequency domain,

[0035] In the formula,

[0036] In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type filter circuit resistor, and for Bypass capacitor in type filter circuit; The imaginary unit, ; For frequency.

[0037] Furthermore, the cutoff frequency corresponding to the second type of signal conditioning circuit for:

[0038] .

[0039] Furthermore, the discrete transfer function corresponding to the second type of signal conditioning circuit is:

[0040]

[0041] In the formula, Sampling time, It is a discrete frequency domain complex number;

[0042] The time-domain difference equation corresponding to the second type of signal conditioning circuit is:

[0043]

[0044] In the formula, The transfer function in the discrete frequency domain. For discrete frequency domain output, For discrete frequency domain input, for The input value at the sampling time, for Output value at the sampling time;

[0045] This leads to the second type of signal conditioning circuit. The signal recovery equation is:

[0046] .

[0047] Furthermore, in step (3), the voltage divider circuit must ensure that the voltage after voltage division is within the safe range of the ADC input voltage of the MCU platform when selecting the resistor parameters.

[0048] Furthermore, in the hardware circuit, the three-phase voltage of the motor is connected to the input terminals of three sets of signal conditioning circuits, and the output terminals of the signal conditioning circuits are connected to the ADC pins in the MCU.

[0049] The beneficial effects of this invention are:

[0050] This invention proposes a method for rapid voltage recovery waveform reconstruction, which has the advantages of simple calculation, high implementation accuracy, and strong hardware versatility, and is especially suitable for resource-constrained microcontroller platforms.

[0051] In terms of accuracy, this method does not require complex mathematical functions (such as square root calculations). Instead, it is based on a preset model and the selection results of hardware circuit parameters (such as inductors and capacitors). By simply inputting numerical values, an approximate voltage waveform of the voltage recovery process can be constructed.

[0052] In terms of computational complexity, this invention avoids the real-time solution of differential equations or convolution processing of high-frequency sampled data found in traditional algorithms. It only requires a small number of multiply-accumulate and table lookup operations to describe the complete voltage waveform. This allows the algorithm to run in real time on low-frequency, memory-constrained 8-bit or 16-bit microcontroller systems without the need for floating-point arithmetic support or reliance on high-performance processors such as DSPs or ARMs, significantly reducing the development and maintenance costs of embedded systems.

[0053] In terms of versatility, this method exhibits high circuit adaptability, independent of specific voltage sampling structures or control topologies. The proposed waveform recovery generation mechanism is based on general physical modeling and numerical input, enabling it to be easily embedded in various types of sampling circuits. Attached Figure Description

[0054] Figure 1 This invention is based on a signal conditioning circuit. Flowchart of the signal recovery equation;

[0055] Figure 2 According to the present invention A flowchart illustrating the process of obtaining the dq voltage using the signal recovery equation;

[0056] Figure 3 This is a schematic diagram of the first type of signal conditioning circuit in Embodiment 1 of the present invention;

[0057] Figure 4 This is a schematic diagram of the second type of signal conditioning circuit in Embodiment 2 of the present invention.

[0058] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. To better illustrate this embodiment, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings. Detailed Implementation

[0059] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0060] Example 1:

[0061] The hardware circuit selected in this embodiment is a first-type signal conditioning circuit.

[0062] like Figure 1 and Figure 2 As shown, this embodiment discloses a method for obtaining the dq voltage with low computational complexity, including the following steps:

[0063] like Figure 3 As shown, the first type of signal conditioning circuit consists of a voltage divider circuit and The first type of signal conditioning circuit is formed by cascading filter circuits. and , This is the three-phase voltage output from the driver to the motor, i.e., the high-voltage PWM that directly drives the motor; The voltage fed into the MCU's ADC is The result after voltage divider filtering.

[0064] According to Kirchhoff's laws:

[0065] (1-1)

[0066] (1-2)

[0067] In the formula, This is the voltage output by the voltage divider circuit; The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type of filter circuit resistor; for Type-type filter circuit capacitor; The imaginary unit, ; For frequency;

[0068] For (1-2), we can obtain:

[0069] (1-3)

[0070] Substituting (1-3) into (1-1), we get:

[0071] (1-4)

[0072] Therefore

[0073] (1-5)

[0074] Convert to frequency domain:

[0075] (1-6)

[0076] In the formula, For continuous complex frequency domain complex numbers

[0077] Where the time constant

[0078] (1-7)

[0079] Voltage gain

[0080] (1-8)

[0081] In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type of filter circuit resistor; for Type-type filter circuit capacitor; The imaginary unit, ; For frequency.

[0082] Cutoff angular frequency of a first-order delay element for:

[0083] (1-9)

[0084] Equation (1-9) can be used to calculate this: , The selection is used to step down the high-voltage PWM to 0~3.3 (the sampling range of the MCU's ADC). , Choose to select an appropriate cutoff frequency.

[0085] Using first-order backward difference It can transform the continuous frequency domain into the discrete frequency domain:

[0086] In the formula, Sampling time, For discrete frequency domain complex numbers

[0087] (1-10)

[0088] In the formula, Sampling time, It is a discrete frequency domain complex number;

[0089] In the formula, The transfer function in the continuous frequency domain. The transfer function in the discrete frequency domain. For discrete frequency domain output, It is a discrete frequency domain input.

[0090] Therefore, we obtain Signal recovery equation

[0091] (1-11)

[0092] In the formula, for The input value at the sampling time, for The output value at the sampling time.

[0093] Note that all coefficients in the above formula are obtained from hardware circuits, and can be calculated and imported in advance after the hardware selection is determined.

[0094] In the hardware circuit, the three-phase voltage of the motor needs to be connected to the input terminals of three sets of signal conditioning circuits respectively, and the output terminals of the signal conditioning circuits are connected to the ADC pins in the MCU.

[0095] During one control cycle, the three-phase voltages are sampled from the three sets of output voltages respectively. , and Perform a Clark transformation on it to obtain and The results of the sampling time and several previous sampling times are used as inputs to the signal recovery equation to obtain the true voltage at the sampling time. and Then, by performing a Park transformation, the actual dq voltage can be obtained.

[0096] In this embodiment, the following is used , , Three sampling times.

[0097] Example 2:

[0098] The hardware circuit selected in this embodiment is a type II signal conditioning circuit.

[0099] like Figure 1 and Figure 2 As shown, this embodiment discloses a method for obtaining the dq voltage with low computational complexity, including the following steps:

[0100] like Figure 4 As shown, the second type of signal conditioning circuit consists of a voltage divider circuit and The second type of signal conditioning circuit is formed by cascading filter circuits. and , This is the three-phase voltage output from the driver to the motor, i.e., the high-voltage PWM that directly drives the motor; The voltage fed into the MCU's ADC is The result after voltage divider filtering

[0101] According to Kirchhoff's laws:

[0102] (1-12)

[0103] (1-13)

[0104] In the formula, This is the voltage output by the voltage divider circuit. For the higher-order side resistor of the voltage divider circuit, The resistor is the low-side resistor in the voltage divider circuit. for Type filter circuit resistor, and for Bypass capacitor in type filter circuit; The imaginary unit ( ), For frequency.

[0105] For (1-13), we can obtain:

[0106] (1-14)

[0107] Substituting (1-14) into (1-12), we get:

[0108] (1-15) Therefore

[0109] (1-16)

[0110] Convert to frequency domain:

[0111] (1-17)

[0112] In the formula, For continuous complex frequency domain complex numbers

[0113] The transfer function of the signal conditioning circuit is analyzed as follows:

[0114] (1-18)

[0115] in

[0116] (1-19)

[0117] In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type filter circuit resistor, and for Bypass capacitor in type filter circuit; The imaginary unit, ; For frequency.

[0118] The cutoff frequency can then be calculated.

[0119] (1-20)

[0120] Equation (1-20) can be used to calculate this: , The selection is used to step down the high-voltage PWM to 0~3.3 (the sampling range of the MCU's ADC). , Choose to select an appropriate cutoff frequency.

[0121] Using first-order backward difference It can transform the continuous frequency domain into the discrete frequency domain:

[0122] (1-21)

[0123] In the formula, Sampling time, For discrete frequency domain complex numbers

[0124] and time-domain difference equations

[0125]

[0126] In the formula, The transfer function in the discrete frequency domain. For discrete frequency domain output, For discrete frequency domain input, for The input value at the sampling time, for The output value at the sampling time.

[0127] This leads to the recovery equation of the original input signal:

[0128] (1-25)

[0129] Similarly, note that all coefficients in the above formula are obtained from hardware circuits, and can be calculated and imported in advance after the hardware selection is determined.

[0130] Parameter selection:

[0131] (1) Selection of voltage divider circuit parameters

[0132] To ensure that the voltage after voltage division remains within the safe range of the ADC input voltage on the MCU platform, while simultaneously reducing overall power consumption and minimizing resistive effects, this invention preferably employs a high-resistance cascaded resistor network to construct the voltage divider. Taking the bus voltage range as an example, if the highest voltage is 400V, and it is desired that the maximum voltage after voltage division does not exceed 3.3V, then the design can be based on the following relationship:

[0133] (1-26)

[0134] In the formula, Bus voltage

[0135] For example, you can choose the following set of parameters: , It satisfies equation (1-26).

[0136] (2) Selection of filter circuit parameters (based on...) (Taking a type of filter circuit as an example)

[0137] First, based on the sampling requirements, determine which option needs to be selected. Size. For example, select... The required cutoff frequency.

[0138] Select , Calculations yielded

[0139] (1-27)

[0140] therefore

[0141] (1-28)

[0142] Meets design requirements.

[0143] In the hardware circuit, the three-phase voltage of the motor needs to be connected to the input terminals of three sets of signal conditioning circuits respectively, and the output terminals of the signal conditioning circuits are connected to the ADC pins in the MCU.

[0144] During one control cycle, the three-phase voltages are sampled from the three sets of output voltages respectively. , and Perform a Clark transformation on it to obtain and The results of the sampling time and several previous sampling times are used as inputs to the signal recovery equation to obtain the true voltage at the sampling time. and Then, by performing a Park transformation, the actual dq voltage can be obtained.

[0145] In this embodiment, the following is used , , Three sampling times.

[0146] The above embodiments are only used to illustrate and not limit the technical solutions of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention without departing from the spirit and scope of the present invention. Any modifications or partial substitutions should be covered within the scope of the claims of the present invention.

[0147] If the terms "first" or "second" are used in this document to define components, those skilled in the art should know that the use of "first" or "second" is merely for the convenience of describing the invention and simplifying the description, and unless otherwise stated, the above terms have no special meaning.

Claims

1. A method for obtaining dq voltage with low computational complexity, characterized in that... Includes the following steps: (1) Select a signal conditioning circuit, which is composed of a voltage divider circuit and a filter circuit cascaded together; the signal conditioning circuit has and , This is the three-phase voltage output from the driver to the motor; The voltage fed into the MCU's ADC is The result after voltage divider filtering; (2) Based on the selected signal conditioning circuit, derive the transfer function corresponding to the signal conditioning circuit; (3) Select the parameters of the voltage divider circuit according to the voltage division ratio, and select the parameters of the filter circuit according to the frequency of the conditioned signal; Based on the transfer function in step (2), the corresponding discrete transfer function and time-domain difference equation are derived, resulting in... Signal recovery equation; (4) During one motor control cycle, the three-phase signal conditioning circuit samples the three phase signals to obtain the three phase signals. As respectively ;right Perform Clark transformation to obtain and The results of the sampling time and several previous sampling times are sent to step (3). The signal recovery equations yield the actual voltage at each sampling time. and Then, by performing the Park transformation, the actual dq voltage can be obtained.

2. The method for obtaining dq voltage with low computational complexity according to claim 1, characterized in that: The signal conditioning circuit is selected as a type I signal conditioning circuit, which consists of a voltage divider circuit and... It is composed of cascaded filter circuits; The transfer function corresponding to the first type of signal conditioning circuit is: In the formula, For continuous complex frequency domain complex numbers In the formula, the time constant for In the formula, voltage gain for In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type of filter circuit resistor; for Type-type filter circuit capacitor; The imaginary unit, ; For frequency.

3. The method for obtaining dq voltage with low computational complexity according to claim 2, characterized in that: The cutoff frequency corresponding to the first type of signal conditioning circuit for: 。 4. The method for obtaining dq voltage with low computational complexity according to claim 3, characterized in that: The discrete transfer function corresponding to the first type of signal conditioning circuit is: In the formula, Sampling time, It is a discrete frequency domain complex number; In the formula, The transfer function in the continuous frequency domain. The transfer function in the discrete frequency domain. For discrete frequency domain output, For discrete frequency domain input; The time-domain difference equation corresponding to the first type of signal conditioning circuit is, i.e. The signal recovery equation is: In the formula, for The input value at the sampling time, for The output value at the sampling time.

5. The method for obtaining dq voltage with low computational complexity according to claim 1, characterized in that: The signal conditioning circuit is selected as a type II signal conditioning circuit, which consists of a voltage divider circuit and... It is composed of cascaded filter circuits; The transfer function corresponding to the second type of signal conditioning circuit is: Right now, In the formula, For continuous complex numbers in the frequency domain, In the formula, In the formula, The resistor on the higher-order side of the voltage divider circuit; The resistor is the low-side resistor in the voltage divider circuit. for Type filter circuit resistor, and for Bypass capacitor in type filter circuit; The imaginary unit, ; For frequency.

6. The method for obtaining dq voltage with low computational complexity according to claim 5, characterized in that: The cutoff frequency corresponding to the second type of signal conditioning circuit for: 。 7. The method for obtaining dq voltage with low computational complexity according to claim 6, characterized in that: The discrete transfer function corresponding to the second type of signal conditioning circuit is: In the formula, Sampling time, It is a discrete frequency domain complex number; The time-domain difference equation corresponding to the second type of signal conditioning circuit is: In the formula, The transfer function in the discrete frequency domain. For discrete frequency domain output, For discrete frequency domain input, for The input value at the sampling time, for Output value at the sampling time; This leads to the second type of signal conditioning circuit. The signal recovery equation is: 。 8. The method for obtaining dq voltage with low computational complexity according to claim 1, characterized in that: In step (3), when selecting resistor parameters, the voltage divider circuit must ensure that the voltage after voltage division is within the safe range of the ADC input voltage of the MCU platform.

9. A method for obtaining dq voltage with low computational complexity according to any one of claims 1-8, characterized in that: In the hardware circuit, the three-phase voltage of the motor is connected to the input terminals of three sets of signal conditioning circuits, and the output terminals of the signal conditioning circuits are connected to the ADC pins of the MCU.

Images