Marine pump set motor system common mode voltage suppression method, medium and equipment

Abstract

This invention discloses a common-mode voltage suppression method, medium, and device for a ship pump motor system, relating to the field of marine electrical engineering technology. The common-mode voltage suppression method for a ship pump motor system mainly includes: obtaining the modulation wave output from the closed-loop operation of the current loop of the ship pump motor system; dividing the system into sectors using the common-mode voltage modulation principle to obtain the spatial vector of the divided sectors; obtaining the high-level duty cycle of the three-phase branches using a three-phase reference wave; constructing a first intermediate duty cycle and a second intermediate duty cycle; deriving the zero-sequence duty cycle; and injecting it into the high-level duty cycle of the three-phase branches to obtain a new three-phase duty cycle. The new three-phase duty cycle is then used to modulate the ship pump motor system. Implementing the common-mode voltage suppression method, medium, and device for a ship pump motor system provided by this invention can reduce the common-mode voltage of the ship pump motor system without increasing the system size and weight.

Description

Technical Field

[0001] This invention relates to the field of marine electrical engineering technology, and more specifically, to a method, medium, and equipment for suppressing common-mode voltage in a marine pump motor system. Background Technology

[0002] Rapid switching of transistors in power electronic systems generates significant electromagnetic interference (EMI), which is emitted through conduction and radiation, affecting the normal operation of the system and impacting nearby systems. Conducted interference refers to the coupling (interference) of a signal from one electrical network to another through a conductive medium. Radiated interference refers to the coupling (interference) of a signal from an interference source to another electrical network through space. Power electronic systems primarily utilize the switching characteristics of power electronic devices to perform various energy conversions. The switching frequencies are very high; in addition to common low-frequency harmonics, a large number of switching frequency harmonics also appear in the conducted radio frequency band (above 10kHz) systems, affecting the operation of various devices during turn-on and turn-off. , These are all increasing. Moreover, the parasitic inductance and capacitance in the system often resonate, with frequencies reaching tens of megahertz. Due to the coordination of various switch states, a common-mode voltage is generated in the marine pump system. This voltage discharges through the common-mode circuit onto the pump bearings, reducing the safety and lifespan of the pump.

[0003] In marine systems, the most common method to reduce common-mode interference is to apply a common-mode filter. However, this method has limited effectiveness in suppressing common-mode voltage and increases the size and weight of the frequency converter cabinet, placing higher demands on the size and load-carrying capacity of the hull. Summary of the Invention

[0004] The purpose of this invention is to provide a method, medium, and device for suppressing common-mode voltage in a marine pump motor system, which can reduce the common-mode voltage of the marine pump motor system without increasing the system volume and weight.

[0005] This invention provides a common-mode voltage suppression method for a ship pump motor system, comprising the following steps: S1: Obtaining the modulation wave output from the closed-loop operation of the current loop according to the ship pump motor system; S2: Dividing the system into sectors according to the modulation wave and the common-mode voltage modulation principle to obtain the spatial vector of the divided sectors; S3: Obtaining the high-level duty cycle of the three-phase branches according to the spatial vector of the divided sectors and the three-phase reference wave; S4: Obtaining the first intermediate duty cycle and the second intermediate duty cycle according to the high-level duty cycle of the three-phase branches; S5: Obtaining the zero-sequence duty cycle according to the first intermediate duty cycle and the second intermediate duty cycle; S6: Obtaining a new three-phase duty cycle according to the zero-sequence duty cycle and the high-level duty cycle of the three-phase branches; S7: Modulating the ship pump motor system using the new three-phase duty cycle.

[0006] Further, step S3 specifically includes: obtaining the high-level duty cycle of the three-phase branch based on the spatial vector of the divided sector and the three-phase reference wave, as shown in the formula:

[0007] ,

[0008] in, The duty cycle for the high-level circuit of the three-phase branch; This is a three-phase reference wave; Represent Mutually, Mutually, Mutually.

[0009] Further, step S4 specifically includes: obtaining the first intermediate duty cycle and the second intermediate duty cycle based on the high-level duty cycle of the three-phase branch, as shown in the formula:

[0010]

[0011] in, Indicates the first intermediate duty cycle. Indicates the second intermediate duty cycle. and These represent the maximum and minimum values, respectively.

[0012] Further, step S5 specifically includes: obtaining the zero-sequence duty cycle based on the first intermediate duty cycle and the second intermediate duty cycle, as shown in the formula:

[0013] ,

[0014] in, This represents the zero-sequence duty cycle.

[0015] Further, step S6 specifically includes: obtaining a new three-phase duty cycle based on the zero-sequence duty cycle and the high-level duty cycle of the three-phase branch, as shown in the formula:

[0016] ,

[0017] in, For the new three-phase duty cycle.

[0018] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method for suppressing common-mode voltage in a marine pump motor system.

[0019] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the above-described common-mode voltage suppression method for a marine pump motor system.

[0020] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described common-mode voltage suppression method for a marine pump motor system.

[0021] The common-mode voltage suppression method, medium, and equipment for ship pump motor systems provided by this invention have the following beneficial effects:

[0022] This invention utilizes the modulation wave output from the closed-loop operation of the current loop in a ship pump motor system. It divides the common-mode voltage modulation principle into sectors to obtain the spatial vector of each sector. Combined with a three-phase reference wave, it obtains the high-level duty cycle of the three-phase branches, constructs the first and second intermediate duty cycles, and then derives the zero-sequence duty cycle. This zero-sequence duty cycle is then injected into the high-level duty cycle of the three-phase branches, ultimately completing the modulation and resulting in the inverter output voltage. This invention reduces the common-mode voltage of a ship pump motor system without increasing system size or weight; the method is simple, practical, and highly effective. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0024] Figure 1 This is a flowchart of the common-mode voltage suppression method for ship pump motor systems provided by the present invention;

[0025] Figure 2 This is a schematic diagram of the common-mode circuit of the three-level inverter provided by the present invention;

[0026] Figure 3 This is the three-level vector diagram provided by the present invention;

[0027] Figure 4 This is a vector diagram of the common-mode voltage reduction modulation provided by the present invention;

[0028] Figure 5 This is a schematic diagram of the first quadrant region division provided by the present invention;

[0029] Figure 6 This is a diagram illustrating the effect of the traditional SVPWM modulation method provided by this invention.

[0030] Figure 7 This is an effect diagram of the modulation method proposed in this paper, provided by the present invention;

[0031] Figure 8 This is a structural block diagram of the computer device provided by the present invention. Detailed Implementation

[0032] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram of the common-mode voltage suppression method for a ship pump set motor system according to this embodiment is shown. In this embodiment, the common-mode voltage suppression method for a ship pump set motor system includes the following steps:

[0034] S1: Obtain the modulated wave output from the closed-loop operation of the current loop based on the ship's pump set motor system;

[0035] S2: Divide the sectors according to the modulation wave and common-mode voltage modulation principle to obtain the spatial vector of the divided sectors;

[0036] S3: Based on the spatial vector of the divided sector and the three-phase reference wave, the high-level duty cycle of the three-phase branch is obtained;

[0037] In one exemplary embodiment, step S3 specifically includes: obtaining the high-level duty cycle of the three-phase branch based on the spatial vector of the divided sector and the three-phase reference wave, as shown in the formula:

[0038] ,

[0039] in, The duty cycle for the high-level circuit of the three-phase branch; This is a three-phase reference wave; Represent Mutually, Mutually, Mutually;

[0040] S4: Based on the high-level duty cycle of the three-phase branch, obtain the first intermediate duty cycle and the second intermediate duty cycle;

[0041] In one exemplary embodiment, step S4 specifically includes: obtaining a first intermediate duty cycle and a second intermediate duty cycle based on the high-level duty cycle of the three-phase branch, as shown in the formula:

[0042]

[0043] in, Indicates the first intermediate duty cycle. Indicates the second intermediate duty cycle. and These represent the maximum and minimum values, respectively.

[0044] S5: Obtain the zero-sequence duty cycle based on the first intermediate duty cycle and the second intermediate duty cycle;

[0045] In one exemplary embodiment, step S5 specifically includes: obtaining the zero-sequence duty cycle based on the first intermediate duty cycle and the second intermediate duty cycle, as shown in the formula:

[0046] ,

[0047] in, Zero-sequence duty cycle;

[0048] S6: Based on the zero-sequence duty cycle and the high-level duty cycle of the three-phase branch, obtain the new three-phase duty cycle;

[0049] In one exemplary embodiment, step S6 specifically includes: obtaining a new three-phase duty cycle based on the zero-sequence duty cycle and the three-phase branch high-level duty cycle, as shown in the formula:

[0050] ,

[0051] in, For the new three-phase duty cycle;

[0052] S7: Modulate the ship pump motor system using a new three-phase duty cycle.

[0053] In some embodiments, the above-described method for suppressing common-mode voltage in marine pump motor systems can also be implemented in the following ways.

[0054] like Figure 2 The diagram shows the common-mode circuit of a three-level inverter. Taking the midpoint of the two DC-side voltage divider capacitors as the potential reference point, the output voltage of a certain phase of the NPC three-level inverter is... The state of / 2 is called The output voltage is - The state of / 2 is called The state where the output voltage is 0 is called Based on the switch state, a system can be established as follows: Figure 3 The spatial vector diagram shown can be divided into four categories based on the length of the vectors. Red represents large vectors, green represents medium vectors, black represents small vectors, and yellow represents zero vectors. Common-mode voltage can be expressed as one-third of the sum of the three-phase voltages. Therefore, the common-mode voltage corresponding to all vectors can be obtained, as shown in Table 1. Since the PPP and NNN states are not used in actual control, the 27 vectors can be divided into three categories according to the magnitude of the generated common-mode voltage: large vectors will produce a common-mode voltage with an amplitude of Common-mode voltage; small vectors will produce an amplitude of or The common-mode voltage; the middle vector and zero vector do not generate common-mode voltage.

[0055] Table 1: Common-mode voltage corresponding to different vectors of the three-level circuit

[0056]

[0057] Conventional modulation methods, such as SVPWM and carrier comparison PWM, utilize all the vectors mentioned above except for PPP and NNN. Conventional modulation uses large, small, medium, and zero vectors, thus resulting in a maximum amplitude value. The common-mode voltage.

[0058] Common-mode voltage reduction modulation does not use common-mode voltage. The small vectors PPO, POP, OPP, ONN, NON, and NNO are used for vector synthesis and decomposition, thereby reducing the peak value of the common-mode voltage to [value missing]. ,like Figure 4 As shown; where the vector - They are:

[0059] OOO,POO,OON,OPO,NOO,OOP,ONO,PON,OPN,NPO,NOP,ONP,PNO,PNN,PPN,NPN,NPP,NNP,PNP.

[0060] In terms of region partitioning, common-mode voltage reduction modulation divides the traditional large sector (60°) into four smaller sectors, and each large sector is further divided into three smaller sectors to reduce space vector calculations. Figure 5 Taking the first quadrant region as an example, the method for synthesizing the reference voltage vector is as follows:

[0061] Region A: Consists of the zero vector small vector and synthesis;

[0062] Area B: Composed of small vectors , mid-vector and large vectors synthesis;

[0063] Region C: Composed of small vectors , mid-vector and large vectors synthesis;

[0064] Region D: Composed of small vectors and , mid-vector synthesis;

[0065] Region E: Composed of small vectors , mid-vector and large vectors Synthesis. The rules for synthesizing the reference voltage vectors of other sectors are similar to those for the first sector.

[0066] The specific implementation steps are as follows:

[0067] Step 1: Obtain the modulated wave output from the closed-loop operation of the system current loop;

[0068] Step 2: Divide the sectors according to the principle of common-mode voltage modulation;

[0069] Step 3: Assume the three-phase reference wave is The high-level duty cycle of the three-phase branch can then be derived:

[0070]

[0071] Step 4: Construct two intermediate duty cycles and :

[0072]

[0073] Step 5: Derive the zero-sequence duty cycle :

[0074]

[0075] Step 6: [The sentence is incomplete and requires more context to be translated accurately.] And inject it into the three-phase duty cycle:

[0076]

[0077] Step 7: Modulation complete, inverter output voltage.

[0078] This implementation verifies the above method through simulation. A simulation platform is built in Simulink to verify the proposed modulation method for reducing common-mode interference. A comparison is given between the traditional SVPWM and the proposed modulation method for reducing common-mode interference in a three-level inverter with a DC voltage of 3000V. Figure 6 The image shows the effect of the traditional SVPWM modulation method, as follows: Figure 7 The image shows the effect of the modulation method proposed in this embodiment. It can be seen that the maximum common-mode voltage of traditional SVPWM is 1000V, which is exactly... The modulation method proposed in this embodiment has a maximum common-mode voltage of 500V, which is exactly... .

[0079] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the common-mode voltage suppression method for a marine pump motor system described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium may also include combinations of the above types of memory.

[0080] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the above-described common-mode voltage suppression method for a ship pump motor system.

[0081] like Figure 8 As shown, the computer device 120 may include: at least one processor 121, such as a central processing unit (CPU), at least one communication interface 123, memory 124, and at least one communication bus 122. The communication bus 122 is used to enable communication between these components. The communication interface 123 may include a display screen and a keyboard; optionally, the communication interface 123 may also include a standard wired interface or a wireless interface. The memory 124 may be high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory 124 may also be at least one storage device located remotely from the aforementioned processor 121. The memory 124 stores application programs, and the processor 121 calls the program code stored in the memory 124 to execute any of the aforementioned method steps. The communication bus 122 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 122 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8The bus is represented by a single line, but this does not imply a single bus or a single type of bus. The memory 124 may include volatile memory, such as random-access memory (RAM); it may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); or it may include combinations of the above types of memory. The processor 121 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 121 may further include hardware chips. These hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. Optionally, the memory 124 is also used to store program instructions. The processor 121 can call the program instructions to implement the common-mode voltage suppression method for the ship pump motor system as described in this embodiment.

[0082] This embodiment provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described common-mode voltage suppression method for a ship pump motor system.

[0083] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A method of common mode voltage suppression for a marine pump set motor system, the method comprising: Includes the following steps: S1: Obtain the modulated wave output from the closed-loop operation of the current loop based on the ship's pump set motor system; S2: Divide the sectors according to the modulation wave and common-mode voltage modulation principle to obtain the spatial vector of the divided sectors; S3: Based on the spatial vector of the divided sectors and the three-phase reference wave, the high-level duty cycle of the three-phase branch is obtained, as shown in the formula: ， wherein, is a high level duty cycle for the three-phase leg; is a three-phase reference wave; respectively represent phase, phase, phase; S4: Based on the high-level duty cycle of the three-phase branch, obtain the first intermediate duty cycle and the second intermediate duty cycle, as shown in the formula: ， wherein denotes a first intermediate duty cycle, denotes a second intermediate duty cycle, and denotes a maximum value and a minimum value, respectively; S5: Based on the first intermediate duty cycle and the second intermediate duty cycle, obtain the zero-sequence duty cycle, as shown in the formula: ， wherein is the zero sequence duty cycle; S6: Based on the zero-sequence duty cycle and the high-level duty cycle of the three-phase branch, obtain the new three-phase duty cycle; S7: Modulate the ship pump motor system using a new three-phase duty cycle.

2. The common-mode voltage suppression method for a ship pump unit motor system according to claim 1, characterized in that, Step S6 specifically includes: obtaining a new three-phase duty cycle based on the zero-sequence duty cycle and the high-level duty cycle of the three-phase branch, as shown in the formula: ， wherein is the new three-phase duty cycle.

3. A computer-readable storage medium having stored thereon a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the common-mode voltage suppression method for a ship pump motor system as described in any one of claims 1-2.

4. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the common-mode voltage suppression method for a ship pump motor system as described in any one of claims 1-2.

5. A computer program product comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the common-mode voltage suppression method for the ship pump motor system as described in any one of claims 1-2.

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