A physical layer timing tracking method applied to a millimeter wave wireless communication system

Abstract

The application relates to the field of wireless communication, in particular to a physical layer timing tracking method applied to a millimeter wave wireless communication system. The method comprises the following steps: S1. In the millimeter wave communication system, oversampling is performed on a received modulation signal, and a timing error signal is extracted based on a Gardner algorithm; S2. An S curve is constructed based on the timing error signal, the S curve is processed according to different modes selected according to a signal-to-noise ratio condition, and an S curve used for estimating time offset is obtained; S3. The receiving end clock is closed-loop adjusted according to the estimation result of the S curve, and symbol timing tracking is realized. Through the timing tracking method, the problems of insufficient timing error detection precision, poor interpolation estimation stability and high operation complexity in the prior art can be effectively overcome in the millimeter wave communication system, the continuous alignment of symbol sampling time and optimal sampling time is realized, and therefore the precision of timing tracking and the robustness of the system are improved while the hardware operation amount is reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless communication, and in particular to a physical layer timing tracking method for millimeter-wave wireless communication systems. Background Technology

[0002] In millimeter-wave communication systems, because FPGA modules and ADCs / DACs typically employ discrete clock architectures, the transmitting and receiving ends often suffer from clock discrepancies. This leads to timing deviations between the sampling clock and the data processing clock, compromising symbol timing accuracy and consequently affecting system demodulation performance. To address this issue, existing technologies commonly employ timing synchronization methods based on the Gardner algorithm. For example, CN202411416782 proposes a timing synchronization recovery system based on the Gardner algorithm. This system uses a timing error detector, loop filter, and interpolation module at the receiving end to detect and compensate for errors in the received oversampled signal, thereby achieving symbol clock synchronization in noisy and multipath environments and ensuring correct data recovery. In practical implementations, existing technologies also frequently employ a double oversampling method to extract amplitude variation information between symbols and generate a correction signal through closed-loop control to feed back to the clock chip, reducing clock drift between the ADC / DAC and the FPGA. These methods exhibit good stability under long-distance communication and high signal-to-noise ratio conditions, but they still have shortcomings in more complex environments. For example, when the number of sampling points is limited or the signal-to-noise ratio is low, the S-curve obtained by traditional methods is prone to fluctuations, resulting in low interpolation estimation accuracy. Simultaneously, the system computation is large, leading to increased hardware resource consumption and making it difficult to balance real-time performance and accuracy. Therefore, current technology still lacks an improved method that can improve the accuracy of time offset estimation and noise resistance while maintaining controllable computational complexity. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art, such as insufficient timing error detection accuracy, poor interpolation estimation stability, and high computational complexity. This application provides a physical layer timing tracking method for millimeter-wave wireless communication systems, which can accurately estimate and correct symbol timing in millimeter-wave communication systems in real time, achieving stable and reliable timing synchronization even in low signal-to-noise ratio environments. In this method, the timing error can be extracted based on the amplitude difference relationship of the twice-oversampled signal. The time offset is estimated by constructing an S-curve and using piecewise linear interpolation and piecewise search. Then, a closed-loop correction mechanism is combined to dynamically adjust the FPGA's reference clock frequency, achieving continuous alignment between the symbol sampling time and the optimal sampling time. This reduces hardware computation while improving timing tracking accuracy and system robustness.

[0004] In a first aspect, embodiments of this application provide a physical layer timing tracking method for millimeter-wave wireless communication systems, applicable to receivers with a discrete independent clock architecture for digital intermediate frequency and FPGA. This method may include: S1. In millimeter-wave communication systems, the received modulated signal is oversampled, and the timing error signal is extracted based on the Gardner algorithm; S2. Construct an S-curve based on the timing error signal, and process the S-curve using different modes according to the signal-to-noise ratio condition to obtain an S-curve for estimating the time offset; S3. Based on the estimation result of the S-curve, the receiving clock is adjusted in a closed loop to achieve symbol timing tracking.

[0005] The physical layer timing tracking method for millimeter-wave wireless communication systems according to embodiments of this application has at least the following beneficial effects: This method first oversamples the modulated signal at the receiver of the millimeter-wave communication system and extracts the timing error signal based on the Gardner algorithm. Then, an S-curve is constructed based on the timing error signal and processed to obtain a result for time offset estimation. Subsequently, the receiver clock is adjusted in a closed loop according to the time offset to achieve continuous symbol timing tracking. Through the above processing, this method can effectively solve the problem of clock non-co-origin between the receiver and transmitter in an FPGA discrete independent clock architecture, improve the consistency between the symbol sampling time and the optimal sampling time, and thus ensure that the system maintains stable and reliable timing tracking performance even in complex channels and low signal-to-noise ratio environments.

[0006] According to some embodiments of this application, the sampling is double oversampling, and the mode includes: In the first mode, when the signal-to-noise ratio is >15dB, the number of sampling points is 500,000; In the second mode, when 10dB≤Signal-to-noise ratio≤15dB, the number of sampling points is 300,000; In the third mode, when 5dB ≤ signal-to-noise ratio < 10dB, the number of sampling points is 200,000.

[0007] According to some embodiments of this application, the mean square error (MSE) between the S-curve after multiple averaging and the mean curve is constrained to be less than [a certain value]. .

[0008] According to some embodiments of this application, the closed-loop adjustment includes: performing PID filtering on the timing error signal and outputting it to an interpolator for interpolation processing, wherein the interpolation processing uses one-quarter or one-half of the symbol period as the time base, and the interpolation result is fed back to the PID to achieve closed-loop feedback.

[0009] According to some embodiments of this application, the closed-loop adjustment further includes: the filtered control quantity driving a sine wave generator to generate a 25 MHz correction signal, the correction signal being processed by a DAC and a low-pass filter and then applied to a VCXO voltage-controlled crystal oscillator.

[0010] According to some embodiments of this application, the sampling is double oversampling, and the timing error signal is obtained based on the amplitude difference relationship between adjacent sampling points, and differential and superimposed on QAM according to in-phase and quadrature components.

[0011] Secondly, embodiments of this application provide a physical layer timing tracking device for millimeter-wave wireless communication systems, applied to a discrete independent clock architecture of digital intermediate frequency and FPGA. The device may include: The sampling and error detection module is used to sample the received modulated signal in the millimeter-wave communication system and extract the timing error signal based on the Gardner algorithm. The curve construction and mode selection module is used to construct an S-curve based on the timing error signal, and select different modes to process the S-curve according to the signal-to-noise ratio condition to obtain an S-curve for estimating the time offset. The offset estimation module is used to determine the time offset based on the estimation result of the S-curve; The clock adjustment module performs closed-loop adjustment of the receiver clock based on the estimation result of the S-curve to achieve symbol timing tracking.

[0012] The physical layer timing tracking device for millimeter-wave wireless communication systems according to embodiments of this application has at least the following advantages: This device includes a sampling and error detection module, a curve construction and mode selection module, an offset estimation module, and a clock adjustment module. These modules sequentially perform sampling and error extraction of the received signal, construction and processing of the S-curve, estimation of time offset, and closed-loop adjustment of the receiver clock. Through the coordinated operation of these modules, the device can achieve stable tracking of symbol timing under an FPGA-based discrete clock architecture, ensuring alignment between the receiver's symbol sampling time and the ideal sampling time. This effectively solves the clock synchronization problem under discrete clock conditions, thereby improving the reliability and long-term stability of the millimeter-wave communication system.

[0013] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the steps of the physical layer timing tracking method applied to a millimeter-wave wireless communication system according to Embodiment 1 of this application; Figure 2 This is a graph showing the sinusoidal shape of the output of the Gardner timing error detector in Embodiment 2 of this application; Figure 3 This is a coordinate diagram of the two-point linear equation of Embodiment 2 of this application; Figure 4 This is a schematic diagram of the physical layer timing tracking device applied to a millimeter-wave wireless communication system according to Embodiment 3 of this application; Figure 5 This is a schematic diagram of the system architecture of the independent clock system for digital intermediate frequency and FPGA in Embodiment 4 of this application. Detailed Implementation

[0015] The present application will now be described in further detail with reference to experimental examples and specific embodiments. However, this should not be construed as limiting the scope of the subject matter of the present application to the following embodiments. All technologies implemented based on the content of the present application fall within the scope of protection of the present application.

[0016] Unless otherwise specified, the terms "upper," "lower," "left," "right," "center," "inner," "outer," and "side" used in the description of specific embodiments of this application to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationship in which the product / equipment / device is usually placed during use. These terms are merely for the purpose of facilitating the description of the solution in this application or simplifying the description in specific embodiments, so as to enable those skilled in the art to quickly understand the solution, and do not indicate or imply that a particular device / component / element must have a specific orientation, or be constructed and operated in a specific positional relationship. Therefore, they should not be construed as limitations on this application.

[0017] In the description of the embodiments of this application, technical terms such as "first" and "second" only distinguish one entity or operation from another, and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Example 1 During the research process, the applicant discovered that when using traditional timing synchronization methods based on the Gardner algorithm, if it is desired to simultaneously ensure the accuracy of symbol sampling and the real-time performance of the system in millimeter-wave communication systems, it is necessary to calculate the timing error by using a large number of sampling points under high signal-to-noise ratio conditions and relying on a fixed interpolation method. This approach can only achieve limited synchronization accuracy under high complexity. In solving practical engineering problems, to achieve stable symbol synchronization under low signal-to-noise ratio and high-order modulation conditions, existing technologies cannot meet the requirements of improving timing tracking accuracy and system robustness while ensuring real-time performance.

[0020] Therefore, after researching this problem, the applicant proposed a physical layer timing tracking method for millimeter-wave wireless communication systems, especially for millimeter-wave communication systems where the digital intermediate frequency (IF) and FPGA adopt independent discrete clock architectures. In this architecture, the ADC / DAC and FPGA belong to different clock domains, making it difficult to guarantee the accuracy of symbol sampling and the real-time performance of the system using traditional methods. The method of this invention oversamples the received signal and extracts the timing error using the Gardner algorithm, then combines interpolation and lookup to estimate the time offset. Simultaneously, a closed-loop correction architecture is introduced, sending the timing error signal to a loop filter. The filtered signal drives a sine wave generator to produce a 25 MHz correction signal, which is then applied to the clock chip via a DAC and a low-pass filter, adjusting the clock chip that provides the FPGA clock. This forms a closed-loop link: "Timing Error Detector → Loop Filter → Sine Wave Generator → DAC → Low-Pass Filter → Clock Chip". This embodiment can effectively solve the synchronization problem of non-homogeneous discrete clock architecture at the receiver, and achieve continuous alignment between the symbol sampling time and the optimal sampling time. It maintains high timing tracking accuracy and system reliability even under low signal-to-noise ratio and high-order modulation conditions.

[0021] The timing error signal is first input to the loop filter. The sign of the input signal indicates whether the local clock phase leads or lags the received signal, and the amplitude reflects the magnitude of the error. The loop filter employs a PID algorithm to filter out high-frequency noise, smooth the error signal, adjust the loop bandwidth, and balance convergence speed and noise immunity. The PID output is further transmitted to an interpolator for interpolation processing. The interpolation process uses one-quarter or one-half of the symbol period as the time base, and the interpolation result is fed back to the PID to form closed-loop feedback, used to correct the input of the loop filter. Simultaneously, the output of the loop filter serves as the phase error control signal, which is used by a sine wave generator to generate a 25 MHz sine wave. This signal is then processed by a DAC and a low-pass filter before being fed back to the clock chip, thereby dynamically adjusting the FPGA's reference clock frequency, forming a complete closed-loop control chain.

[0022] Please refer to Figure 1 , Figure 1 This diagram illustrates the steps of a physical layer timing tracking method for a millimeter-wave wireless communication system provided in this application. The method is applicable to receivers with a discrete independent clock architecture for digital intermediate frequency (IF) and FPGA, and may include: S1. In millimeter-wave communication systems, the received modulated signal is oversampled, and the timing error signal is extracted based on the Gardner algorithm; S2. Construct an S-curve based on the timing error signal, and process the S-curve using different modes according to the signal-to-noise ratio condition to obtain an S-curve for estimating the time offset; S3. Based on the estimation result of the S-curve, the receiving clock is adjusted in a closed loop to achieve symbol timing tracking.

[0023] The physical layer timing tracking method for millimeter-wave wireless communication systems according to embodiments of this application has at least the following beneficial effects: This method first oversamples the modulated signal at the receiver of the millimeter-wave communication system and extracts the timing error signal based on the Gardner algorithm. Then, an S-curve is constructed based on the timing error signal and processed to obtain a result for time offset estimation. Subsequently, the receiver clock is adjusted in a closed loop according to the time offset to achieve continuous symbol timing tracking. Through the above processing, this method can effectively solve the problem of clock non-co-origin between the receiver and transmitter in an FPGA discrete independent clock architecture, improve the consistency between the symbol sampling time and the optimal sampling time, and thus ensure that the system maintains stable and reliable timing tracking performance even in complex channels and low signal-to-noise ratio environments.

[0024] According to some embodiments of this application, the sampling is double oversampling, and the mode includes: In the first mode, when the signal-to-noise ratio is >15dB, the number of sampling points is 500,000; In the second mode, when 10dB≤Signal-to-noise ratio≤15dB, the number of sampling points is 300,000; In the third mode, when 5dB ≤ signal-to-noise ratio < 10dB, the number of sampling points is 200,000.

[0025] According to some embodiments of this application, the mean square error (MSE) between the S-curve after multiple averaging and the mean curve is constrained to be less than [a certain value]. .

[0026] According to some embodiments of this application, the closed-loop adjustment includes: performing PID filtering on the timing error signal and outputting it to an interpolator for interpolation processing, wherein the interpolation processing uses one-quarter or one-half of the symbol period as the time base, and the interpolation result is fed back to the PID to achieve closed-loop feedback.

[0027] According to some embodiments of this application, the closed-loop adjustment further includes: the filtered control quantity driving a sine wave generator to generate a 25 MHz correction signal, the correction signal being processed by a DAC and a low-pass filter and then applied to a VCXO voltage-controlled crystal oscillator.

[0028] According to some embodiments of this application, the sampling is double oversampling, and the timing error signal is obtained based on the amplitude difference relationship between adjacent sampling points, and differential and superimposed on QAM according to in-phase and quadrature components.

[0029] In terms of application scenarios, millimeter-wave wireless communication systems generally refer to point-to-point or point-to-multipoint communication systems operating in the millimeter-wave wavelength range. This includes millimeter-wave communication systems following Wi-Fi protocols and those following 5G protocols. These systems are typically based on standard physical layer and data link layer protocols. Another type of millimeter-wave system is the proprietary protocol communication system, such as microwave point-to-point or microwave point-to-multipoint systems. These systems are often used in industry private networks and are developed according to specific needs. From the physical layer to the MAC layer, they focus more on performance indicators such as throughput, reliability, and channel utilization. Proprietary protocol millimeter-wave communication systems not only help solve the problem of reliance on imported high-end millimeter-wave chips but also enhance the ability to independently control core communication technologies. Among these, the most challenging aspect of proprietary protocol millimeter-wave systems is the physical layer functionality. Timing calibration in the physical layer involves clock tracking between the master and slave stations, which is one of the key technologies for ensuring data alignment and signal processing accuracy. The timing tracking method provided in this application can effectively improve system reliability in such scenarios.

[0030] The physical layer timing tracking method for millimeter-wave wireless communication systems provided in this application is particularly suitable for communication systems with a discrete independent clock architecture of digital intermediate frequency and FPGA. When controlling the timing of the receiving link, this method first oversamples the received signal and extracts the timing error signal. Then, it constructs an S-curve based on the error signal to estimate the time offset. Subsequently, it dynamically adjusts the reference clock frequency through closed-loop correction to achieve continuous tracking of symbol timing. This improves the accuracy of timing detection, reduces the complexity of hardware implementation, and enhances the robustness of the system under complex channel and low signal-to-noise ratio conditions.

[0031] Example 2 As a further optimization of the previous embodiment, this embodiment provides a specific implementation scheme for a physical layer timing tracking method applied to a millimeter-wave wireless communication system. The basic idea is to extract the amplitude and polarity change information of the optimal sampling points of adjacent symbols, and combine this with the characteristic that the transition point of adjacent symbols is zero, to derive the timing error signal from the sampled signal. The Gardner bit timing algorithm based on interpolation typically consists of an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator (NCO). The interpolation filter calculates the sampled value of the interpolation time based on the sampled value of the digital baseband signal. The timing error detector uses the interpolated value to measure the phase difference between the interpolated time and the optimal sampling time. The loop filter filters this phase difference and outputs a control quantity to adjust the NCO step size, thereby generating a new interpolation time. When the loop filter output converges to a stable small value, doubling the frequency of the interpolation clock yields the bit timing pulse, thus completing the bit synchronization of the digital symbols.

[0032] Based on this, the implementation steps of the interpolation Gardner bit timing algorithm proposed in this embodiment of the invention are as follows: 1) The timing tracking module receives downlink or uplink modulation signals y(n), and the system defaults to QAM modulation.

[0033] 2) Different modulation methods require different error detection methods, specifically: The error detection formula for the timing error detector for QAM (Quadrature Amplitude Modulation) signals is as follows: , , , In the formula, y(k) is the complex baseband signal with k interpolated sampling points; i () and y q () represents the real part (in phase) and the imaginary part (orthogonal) components, respectively; under the condition of double oversampling, k and k-2 can be regarded as samples near the boundary of two adjacent symbols (or equivalent optimal sampling time), and k-1 is the midpoint sample between the two; time_error(n) is the timing error calculated at the nth update, and the update period is the symbol period Tb.

[0034] In practical implementation, to simplify the complexity of FPGA implementation, the signal values ​​can be replaced by changing the sign of y(k) and y(k-2).

[0035] 3) Please refer to Figure 2 , Figure 2The error signal output by the Gardner timing error detector, which uses QAM periodic modulation with a data length of 200,000 symbols, is represented by a sinusoidal S-curve. The horizontal axis represents the time offset, and the vertical axis represents the error detector output. ±1 corresponds to one symbol period under a double oversampling condition. The error detection formula is defined based on the amplitude difference relationship between the in-phase component, the quadrature component, and adjacent sampling points. In this embodiment, piecewise linear interpolation and a LUT piecewise lookup table are used to determine the time offset corresponding to the actual error.

[0036] To balance accuracy and computational complexity under different channel conditions, this embodiment sets three operating modes, corresponding to the signal-to-noise ratio range of the received signal: When the signal-to-noise ratio is 5–10 dB, the number of sampling points is 200,000 (third mode). When the signal-to-noise ratio is 10–15 dB, the number of sampling points is 300,000 (second mode). When the signal-to-noise ratio is higher than 15dB, the number of sampling points is 500,000 (first mode).

[0037] Experiments have shown that, with 200,000 sampling points, an original signal-to-noise ratio (SNR) of 10 dB, and a test-estimated SNR of 10 dB, and after averaging the curve 100 times, the results obtained under the same parameter settings indicate that, for SNRs of 5, 10, and 20 dB, the mean square error (MSE) of the constructed S-curve compared to the mean curve is respectively... , and All remained The small differences shown below indicate that this method can guarantee the smoothness of the curve and the controllability of timing error under different signal-to-noise ratio conditions. In the above experiment, the number of segments was 2048, and the range of the horizontal axis was ±0.5, corresponding to one symbol period under the condition of double oversampling.

[0038] Furthermore, to improve the system's reliability under different channel conditions, this embodiment selects different numbers of sampling points to form different operating modes based on the signal-to-noise ratio (SNR) range of the received signal: when the SNR is 5–10 dB, the number of sampling points is controlled at 200,000 (third mode); when the SNR is 10–15 dB, the number of sampling points is controlled at 300,000 (second mode); and when the SNR is greater than 15 dB, the number of sampling points is controlled at 500,000 (first mode). Verification shows that the MSE can be maintained below 1.5 × 10⁻⁻⁴ under all three modes. 7 This ensures the smoothness of the S-curve and the stability of timing tracking. The system defaults to the first mode with 500,000 points to meet real-time requirements; in low signal-to-noise ratio environments, it can switch to the second or third mode as needed to further enhance system stability.

[0039] Through the above improvements, this embodiment can maintain the accuracy of timing tracking and the robustness of the system under different signal-to-noise ratio scenarios, while avoiding excessive consumption of hardware computing resources.

[0040] 4) Use piecewise linear interpolation to estimate the time offset. Given the coordinates of two adjacent points (x0, y0) and (x1, y1) on the S-curve, for any point y within the interval [y0, y1], please refer to... Figure 3 The corresponding x-coordinate can be calculated using the following two-point form of the straight line equation:

[0041] This yields the relationship between the horizontal and vertical coordinates of the interpolation points. Furthermore, n sub-points can be selected within each interval to generate continuous interpolation data, which can be used as a reference for subsequent searches.

[0042] 5) Estimate the actual time offset by segmented search. Compare the actual detected error value with the interpolation curve. If y0 ≤ error ≤ y, the time offset is estimated to be x0 or x, i.e.: If the error -y0 ≤ y - error, the time offset is estimated to be x0; If the error -y0 > y1 - error, the time offset is estimated to be x1.

[0043] 6) Finally, through the above piecewise linear interpolation and piecewise search method, the detected error value is mapped to the corresponding time offset to obtain the estimated result of symbol timing, and drive the closed-loop clock correction to realize continuous tracking and calibration of the receiver clock.

[0044] Example 3 As a device implementation of the methods described in Embodiments 1 and 2, this application provides a physical layer timing tracking device for millimeter-wave wireless communication systems. This device is suitable for receivers with a discrete independent clock architecture of digital intermediate frequency and FPGA, and includes a sampling and error detection module, a curve construction and mode selection module, an offset estimation module, and a clock adjustment module. The signal connections between these modules are clear, and they work together to complete the timing tracking process.

[0045] The sampling and error detection module is used to oversample the received millimeter-wave communication modulation signal and extract timing error signals based on the Gardner algorithm.

[0046] The curve construction and mode selection module is used to construct an S-curve based on the timing error signal and select different modes for processing according to the signal-to-noise ratio (SNR) conditions. In practical applications, three modes are set: the first mode is used when the SNR > 15dB, with 500,000 sampling points; the second mode is used when 10dB ≤ SNR ≤ 15dB, with 300,000 sampling points; and the third mode is used when 5dB ≤ SNR < 10dB, with 200,000 sampling points. Through the processing of this module, a smooth S-curve can be obtained under different SNR conditions, and the mean square error (MSE) between the averaged curve and the mean curve is kept at 1.5 × 10⁻⁻⁶. 7 the following.

[0047] The offset estimation module is used to determine the time offset value based on the processing result of the S-curve and provide the result to the clock adjustment module.

[0048] The clock adjustment module is used to perform closed-loop adjustment of the receiver reference clock based on the time offset result. Specifically, it includes: performing PID filtering on the timing error signal and outputting it to an interpolator for interpolation processing. The interpolation processing uses one-quarter or one-half of the symbol period as the time base, and the resulting interpolation result is fed back to the PID to achieve closed-loop feedback; the filtered control quantity drives a sine wave generator to generate a 25MHz correction signal, which is then processed by a DAC and a low-pass filter before being input to a VCXO voltage-controlled crystal oscillator, thereby dynamically adjusting the reference clock frequency and phase of the FPGA.

[0049] Through the coordinated operation of the above modules, the device in this embodiment can effectively achieve continuous tracking of symbol timing under the discrete independent clock architecture of digital intermediate frequency and FPGA, ensuring the alignment of the symbol sampling time at the receiving end with the optimal sampling time, and improving the stability and reliability of the system in low signal-to-noise ratio environments and complex channel conditions.

[0050] It should be understood that the various modules of the physical layer timing tracking device for millimeter-wave wireless communication systems provided in the above embodiments are only illustrated by the division of functional modules in the above description when performing timing tracking. In practical applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0051] The functional modules in the above embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of the embodiments of this application.

[0052] Example 4 As a specific application of the aforementioned method embodiments, this embodiment provides a system architecture for a physical layer timing tracking device applied to a millimeter-wave wireless communication system.

[0053] Please refer to Figure 5 , Figure 5 This diagram illustrates the system architecture of a separate digital intermediate frequency (IF) and FPGA clock system, applicable to millimeter-wave communication systems employing independent clock architectures for both the IF and FPGA. The system includes: an RF module, an AD / digital converter module, an FPGA logic unit, a DA module, a low-pass filter (LPF), and a VCXO (voltage-controlled crystal oscillator).

[0054] The RF module receives and down-converts the IF analog signal to obtain an intermediate frequency (IF) analog signal. The AD module performs analog-to-digital conversion on the IF signal and outputs a digital baseband signal, which is then fed into the FPGA. The FPGA internally includes a timing error detector, a loop filter, and a sine wave generator. The timing error detector uses the Gardner algorithm to extract the timing error signal under double oversampling conditions. The loop filter smooths the error signal based on a PID algorithm and combines the interpolation results to form a closed-loop feedback, improving the stability of error correction. The sine wave generator generates a 25MHz digital sine correction signal based on the output of the loop filter.

[0055] The correction signal is converted into an analog signal by the DA module and filtered by the LPF before being fed into the VCXO oscillator to dynamically adjust the frequency and phase of its output clock. The clock corrected by the VCXO is then fed back to the FPGA, forming a closed-loop control sequence of "timing error detector → loop filter → sine wave generator → DA → LPF → VCXO → FPGA".

[0056] Under different signal-to-noise ratio (SNR) conditions, the device can select different numbers of sampling points according to the three modes described in the method embodiments: 200,000 points when the SNR is 5–10 dB; 300,000 points when the SNR is 10–15 dB; and 500,000 points when the SNR is greater than 15 dB. Experiments show that the mean square error (MSE) can be kept less than [value missing] in all three modes. This ensures the accuracy of timed detection and tracking.

[0057] By combining the above structure and method, this embodiment can stably realize symbol timing detection and closed-loop tracking under digital intermediate frequency and FPGA discrete clock architecture under complex channel and low signal-to-noise ratio conditions, effectively improving the reliability and robustness of millimeter wave communication system.

[0058] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A physical layer timing tracking method for millimeter-wave wireless communication systems, applicable to receivers with discrete independent clock architectures of digital intermediate frequency and FPGA, characterized in that, include: S1. In a millimeter-wave communication system, an intermediate frequency analog signal is received and down-converted by an RF module, and the intermediate frequency analog signal is converted from analog to digital by an AD module to obtain a digital baseband signal input to the FPGA. The digital baseband signal is oversampled twice in the FPGA, and a timing error signal is extracted based on the Gardner algorithm. S2. Construct an S-curve based on the timing error signal, and process the S-curve by selecting the corresponding number of sampling points according to the signal-to-noise ratio range. Specifically, when the signal-to-noise ratio is >15dB, the number of sampling points is 500,000; when 10dB ≤ signal-to-noise ratio ≤15dB, the number of sampling points is 300,000; and when 5dB ≤ signal-to-noise ratio <10dB, the number of sampling points is 200,000. Map the actually detected timing error signal to a time offset value based on the processed S-curve. S3. Perform closed-loop adjustment of the receiving clock according to the time offset value to achieve symbol timing tracking; wherein, the closed-loop adjustment includes: performing PID filtering on the timing error signal to obtain the filtered control quantity; outputting the PID filter to an interpolator for interpolation processing, wherein the interpolation processing uses one-quarter or one-half of the symbol period as the time base, and the interpolation result is fed back to the PID to form closed-loop feedback; and the filtered control quantity drives a sine wave generator to generate a 25MHz correction signal, wherein the 25MHz correction signal is converted by a DA module and processed by a low-pass filter before being input to a VCXO voltage-controlled crystal oscillator to dynamically adjust the frequency and phase of the VCXO output clock, and feeding back the VCXO-corrected clock to the FPGA.

2. The method according to claim 1, characterized in that, The mean square error (MSE) between the S-curve, after multiple averaging, and the mean curve is constrained to be less than 1.5 × 10⁻⁶. -7 .

3. The method according to claim 1, characterized in that, The timing error signal is obtained based on the amplitude difference relationship between adjacent sampling points, and differential and superimposed on QAM according to in-phase and quadrature components.

4. A physical layer timing tracking device for a millimeter-wave wireless communication system, used to implement the physical layer timing tracking method for a millimeter-wave wireless communication system as described in claim 1, characterized in that, include: The sampling and error detection module is used in millimeter-wave communication systems to receive and down-convert intermediate frequency analog signals through the radio frequency (RF) module, perform analog-to-digital conversion on the intermediate frequency analog signals through the AD module to obtain digital baseband signals input to the FPGA, perform double oversampling on the digital baseband signals in the FPGA, and extract timing error signals based on the Gardner algorithm. The curve construction and mode selection module is used to construct an S-curve based on the timing error signal, and select different modes to process the S-curve according to the signal-to-noise ratio condition to obtain an S-curve for estimating the time offset. The offset estimation module is used to construct an S-curve based on the timing error signal and process the S-curve by selecting the corresponding number of sampling points according to the signal-to-noise ratio range. Specifically, when the signal-to-noise ratio is >15dB, the number of sampling points is 500,000; when 10dB ≤ signal-to-noise ratio ≤15dB, the number of sampling points is 300,000; and when 5dB ≤ signal-to-noise ratio <10dB, the number of sampling points is 200,000. The actual detected timing error signal is mapped to a time offset value based on the processed S-curve. A clock adjustment module is used to perform closed-loop adjustment of the receiving clock based on the time offset value to achieve symbol timing tracking. The closed-loop adjustment includes: performing PID filtering on the timing error signal to obtain a filtered control quantity; outputting the PID filter to an interpolator for interpolation processing, where the interpolation process uses one-quarter or one-half of the symbol period as a time reference, and feeding the interpolation result back to the PID to form closed-loop feedback; furthermore, the filtered control quantity drives a sine wave generator to generate a 25MHz correction signal, which is then converted by a DA module and processed by a low-pass filter before being input to a VCXO voltage-controlled crystal oscillator to dynamically adjust the frequency and phase of the VCXO output clock, and feeding the VCXO-corrected clock back to the FPGA.

5. The apparatus according to claim 4, characterized in that, The offset estimation module is configured to ensure that the mean square error (MSE) between the S-curve and the mean curve after multiple averaging is less than 1.5 × 10⁻⁶. -7 .

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