Circuit board and manufacturing method thereof

Abstract

The invention provides a circuit board and a manufacturing method thereof. The circuit board comprises two circuit substrates and a conductive layer. The circuit substrates are stacked with each other, and each circuit substrate comprises an insulating substrate and a conductive through hole arranged in the insulating substrate. The conductive through hole is communicated with two opposite sides of the insulating substrate. The conductive layer is arranged between the conductive through holes, the conductive through holes are electrically connected through the conductive layer, and the conductive layer comprises a nanometer hole structure. Therefore, under the condition that the electrical connection is not influenced, the connection strength between the conductive through holes of each circuit substrate is increased, so that the reliability of the circuit board is improved.

Description

Technical Field

[0001] This invention relates to a circuit board and a method for manufacturing a circuit board. Background Technology

[0002] In recent years, the application range of circuit boards using glass substrates has gradually expanded. However, due to the material properties of glass substrates, it is difficult to increase the aspect ratio of conductive vias within them. In other words, the depth of the conductive vias is limited by the processing technology of the glass substrate. This means that when the glass substrate is thicker, the width of the conductive vias must also be wider, which is detrimental to expanding the application range of circuit boards using glass substrates. Furthermore, increasing the aspect ratio of conductive vias in glass substrates by laminating multilayer boards would affect the electrical and mechanical reliability of the vias. Summary of the Invention

[0003] At least one embodiment of the present invention provides a circuit board.

[0004] At least one embodiment of the present invention provides a method for manufacturing the above-described circuit board.

[0005] The circuit board provided in at least one embodiment of the present invention includes two first circuit boards and a first conductive layer. The first circuit boards are stacked on top of each other, and each first circuit board includes an insulating substrate and a first conductive via disposed in the insulating substrate. The first conductive via connects opposite sides of the insulating substrate. The first conductive layer is disposed between the first conductive vias, and the first conductive vias are electrically connected through the first conductive layer, and the first conductive layer includes a nano-pore structure.

[0006] In at least one embodiment of the present invention, the circuit board further includes an insulating layer disposed between the first circuit substrates, and the insulating layer surrounds the periphery of the first conductive layer.

[0007] In at least one embodiment of the present invention, the circuit board further includes a conductive post disposed on the first conductive layer and located between one of the first conductive vias and the first conductive layer, wherein the first conductive via is electrically connected to the first conductive layer through the conductive post.

[0008] In at least one embodiment of the present invention, each first conductive via includes two pads. The two pads are respectively disposed on opposite end faces of the first conductive via, and the first conductive via is connected to the first conductive layer through one of the pads.

[0009] In at least one embodiment of the present invention, at least one of the insulating substrates is a glass substrate.

[0010] In at least one embodiment of the present invention, the circuit board further includes a second circuit substrate and a second conductive layer. The second circuit substrate is disposed between the first circuit substrates, and is located between one of the first circuit substrates and the first conductive layer. The second circuit substrate includes a second conductive via, which communicates opposite sides of the second circuit substrate and is electrically connected to the first circuit substrate. The second conductive via is connected to one of the first conductive vias through the first conductive layer. A second conductive layer is disposed on the second conductive via, and the second circuit substrate is located between the first conductive layer and the second conductive layer. The second conductive via is connected to the other of the first conductive vias through the second conductive layer, and the second conductive layer includes a nano-pore structure.

[0011] A method for manufacturing a circuit board according to at least one embodiment of the present invention includes: forming at least two circuit substrates, each circuit substrate including an insulating substrate and conductive vias disposed in the insulating substrate, the conductive vias connecting opposite sides of the insulating substrate; forming a plurality of metal nanowires on at least one end face of one of the conductive vias, the metal nanowires extending in a direction away from the end face; and laminating the circuit substrates after forming the metal nanowires, wherein the metal nanowires located on the conductive vias are aligned with another conductive via, and the metal nanowires are located between these conductive vias, so that the metal nanowires form a conductive layer. The conductive vias are electrically connected through the conductive layer, and the conductive layer includes a nanopore structure.

[0012] In at least one embodiment of the present invention, the method of manufacturing the circuit board further includes forming an insulating layer on the circuit substrate after laminating the circuit substrate. This insulating layer is located between the circuit substrates and surrounds the periphery of the conductive layer.

[0013] In at least one embodiment of the present invention, the method of manufacturing the circuit board further includes, before laminating the circuit board substrate, setting an insulating material on the nano-metal wire. This insulating material covers the end face of the aforementioned conductive via and encapsulates the nano-metal wire; and attaching another of the conductive vias to the nano-metal wire so that the other of the conductive vias directly contacts the nano-metal wire.

[0014] In at least one embodiment of the present invention, at least one of the insulating substrates of the circuit board is a glass substrate.

[0015] Based on the above, by setting nano-metal lines on the bonding surfaces of the circuit board substrates, a conductive layer containing nano-pore structures is formed between the connected conductive vias. This increases the connection strength between the conductive vias of each circuit board substrate without affecting electrical connections, thus improving the reliability of the circuit board. Therefore, when the insulating substrate of the circuit board is a glass substrate, the aspect ratio of the conductive vias in the glass substrate can be increased by stacking multiple circuit boards, thereby expanding the application range of the circuit board. Attached Figure Description

[0016] The nature of the invention can be understood from the following detailed description and accompanying drawings. It should be noted that many features are not drawn to industry-standard scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0017] Figure 1 This is a cross-sectional view of a circuit board according to at least one embodiment of the present invention;

[0018] Figure 2 This is a cross-sectional view of a circuit board according to at least one embodiment of the present invention;

[0019] Figure 3 This is a cross-sectional view of a circuit board according to at least one embodiment of the present invention;

[0020] Figures 4A to 4E This is a cross-sectional view of a circuit board manufacturing method according to at least one embodiment of the present invention;

[0021] Figure 5 This is a partial top view of a circuit board according to at least one embodiment of the present invention;

[0022] Figure 6 This is a cross-sectional view of a circuit board manufacturing method according to at least one embodiment of the present invention;

[0023] Figure 7 This is a cross-sectional view of a circuit board according to at least one embodiment of the present invention.

[0024] Figure label:

[0025] 100, 200, 300, 700: Circuit Boards

[0026] 110, 120, 130: Circuit board

[0027] 112, 122, 132: Insulating substrate

[0028] 114a, 114b, 124a, 124b: Line layers

[0029] 116, 126, 136: Conductive vias

[0030] 132f, 132s: Surface

[0031] 136e: End face

[0032] 150, 160: Conductive layer

[0033] 170a, 170b, 770: Insulation layer

[0034] 380: Conductive post

[0035] 404a, 404b: Metallic layer

[0036] 405: Nano Metal Wire

[0037] 406V: Through hole

[0038] 430: Initial circuit board

[0039] 434a, 434b: Seed layer

[0040] 670a, 670b: Insulating materials

[0041] 790a, 790b: Photoresist materials

[0042] P1, P2: Connecting pads

[0043] T1: Thickness

[0044] W1: Width Detailed Implementation

[0045] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, and depth) of components (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some components may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of components in the drawings or the dimensions and shapes presented by the components, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the components presented in the accompanying drawings are primarily for illustrative purposes and are not intended to precisely depict the actual shape of the components, nor are they intended to limit the scope of the claims in this application.

[0046] Secondly, the terms "approximately," "approximately," or "substantially" used in this document not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understood by someone skilled in the art to which this invention pertains. This deviation range can be determined by errors that occur during measurement, such as those arising from limitations of the measurement system or process conditions. Furthermore, "approximately" can mean within one or more standard deviations of the aforementioned numerical values, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this document can be chosen based on optical properties, etching properties, mechanical properties, or other properties to select an acceptable deviation range or standard deviation, and do not apply a single standard deviation to all optical properties, etching properties, mechanical properties, and other properties. Additionally, for clarity in the following embodiments, components with the same or similar functions are indicated by the same designation.

[0047] Figure 1 This is a partial cross-sectional view of a circuit board 100 according to at least one embodiment of the present invention. The circuit board 100 includes two stacked circuit boards 110 and 120, and a conductive layer 150. The circuit board 110 includes an insulating substrate 112, circuit layers 114a and 114b, and a conductive via 116, wherein the insulating substrate 112 is disposed between circuit layers 114a and 114b. The conductive via 116 is disposed in the insulating substrate 112 and connects opposite sides of the insulating substrate 112. Specifically, the conductive via 116 extends from circuit layer 114a through the insulating substrate 112 and to circuit layer 114b, thereby electrically connecting circuit layers 114a and 114b.

[0048] On the other hand, the circuit board 120 includes an insulating substrate 122, circuit layers 124a and 124b, and a conductive via 126, wherein the insulating substrate 122 is disposed between the circuit layers 124a and 124b. The conductive via 126 is disposed in the insulating substrate 122 and connects opposite sides of the insulating substrate 122. Specifically, the conductive via 126 extends from the circuit layer 124a through the insulating substrate 122 and to the circuit layer 124b, thereby electrically connecting the circuit layers 124a and 124b.

[0049] A conductive layer 150 is disposed between conductive vias 116 and 126, wherein conductive vias 116 and 126 are electrically connected through the conductive layer 150. More specifically, in this embodiment, the circuit board 100 further includes a circuit board 130 and another conductive layer 160. The circuit board 130 is disposed between circuit boards 110 and 120, and is located between circuit board 120 and the conductive layer 150. The circuit board 130 includes conductive vias 136, which connect opposite sides of the circuit board 130 and are electrically connected to circuit boards 110 and 120 respectively.

[0050] A conductive layer 160 is disposed on the conductive via 136, and the circuit board 130 is located between the conductive layers 150 and 160. This configuration allows the conductive via 136 to be connected to the conductive via 116 via the conductive layer 150, and the conductive via 136 to be connected to the conductive via 126 via the conductive layer 160. In other words, in this embodiment, the conductive vias 116 and 126 are electrically connected via the conductive layers 150, 136, and 160.

[0051] However, the present invention is not limited to the above. In other embodiments, the conductive via 116 may be electrically connected to the conductive via 126 only through the conductive layer 150 (that is, the conductive layer 150 directly contacts both the conductive via 116 and the conductive via 126). For example, please refer to... Figure 2 In this embodiment, circuit board 200 is similar to circuit board 100, also including circuit board 110, circuit board 120 and conductive layer 150. The difference between the two circuit boards is that circuit board 200 does not include circuit board 130 and conductive layer 160, so conductive via 116 and conductive via 126 are electrically connected only through conductive layer 150.

[0052] Conductive layers 150 and 160 comprise nanopore structures, and conductive layers 150 (and 160) may contain conductive materials such as metals, for example, copper. For instance, conductive layers 150 (and 160) may be metal layers with porous structures containing numerous pores with diameters ranging from 1 nm to 10 μm. Notably, the conductivity of such nanopore structures can be approximately 5.96 × 10⁻⁶. 7 S / m. In other words, the conductivity of conductive layer 150 (and conductive layer 160) is not reduced by the nanopore structure distributed therein.

[0053] Please return Figure 1The circuit board 100 also includes an insulating layer 170a and an insulating layer 170b. Insulating layers 170a and 170b are disposed between the circuit substrate 110 and the circuit substrate 120, and respectively surround the periphery of the conductive layer 150 and the periphery of the conductive layer 160. Specifically, insulating layer 170a is located between the circuit substrate 110 and the circuit substrate 130, while insulating layer 170b is located between the circuit substrate 130 and the circuit substrate 120.

[0054] Notably, each conductive via 116 (or conductive via 126) includes two pads P1. These pads P1 are respectively disposed on opposite end faces (not shown) of the conductive via 116 (or conductive via 126), wherein the conductive via 116 is connected to the conductive layer 150 through one of the pads P1, and the conductive via 126 is connected to the conductive layer 150 through one of the pads P1. In detail, in this embodiment, the conductive via 116 is directly connected to the conductive layer 150 through one of the pads P1, while the conductive via 126 is connected to the conductive layer 150 through one of the pads P1, the conductive layer 160, and the conductive via 136.

[0055] Please refer to Figure 3 In this embodiment, circuit board 300 is similar to circuit board 200, also including circuit board 110, circuit board 120, and conductive layer 150, but excluding circuit board 130 and conductive layer 160. The difference between circuit board 300 and circuit board 200 is that circuit board 300 also includes conductive posts 380. These conductive posts 380 are disposed on conductive layer 150 and located between conductive via 116 and conductive layer 150. Therefore, conductive via 116 can be electrically connected to conductive layer 150 through conductive posts 380. Conductive posts 380 may contain conductive materials such as metal, for example, copper.

[0056] It is worth mentioning that at least one of the insulating substrates 112 and 122 is a glass substrate, and the material of the glass substrate may include silicon, ceramic, or sapphire. Figure 1 or Figure 2 For example, both insulating substrate 112 and insulating substrate 122 are glass substrates, but the present invention is not limited thereto. In other embodiments, only insulating substrate 112 may be a glass substrate, while insulating substrate 122 may be a substrate containing other insulating materials, such as prepreg (PP), Ajinomoto buildup film (ABF), BT (Bimaleimide Triazine) resin, photosensitive dielectric (PID), or any kind of semi-cured (B-Stage) polymer.

[0057] When the insulating substrate 112 is a glass substrate, the ratio between the thickness T1 of the insulating substrate 112 and the width W1 of the conductive via 116 can fall between 1 and 20. For example, the thickness T1 of the insulating substrate 112 can range from 50 μm to 4000 μm, while the width W1 of the conductive via 116 can range from 50 μm to 200 μm.

[0058] In various embodiments of the present invention, the number of circuit boards in the circuit board 100 is not limited to the above embodiments (i.e., not limited to two or three). In other embodiments, the number of circuit boards in the circuit board 100 may be any number more than two, for example, five. Furthermore, although each circuit board in the above embodiments includes two conductive vias, the present invention is not limited thereto. In other embodiments, the number of conductive vias in each circuit board may be any number more than one, for example, one or three.

[0059] This invention provides a method for manufacturing a circuit board. Taking circuit board 100 as an example, this manufacturing method may include the following steps: Figures 4A to 4E The steps are as follows. First, at least two circuit boards are formed; in this embodiment, three circuit boards (i.e., circuit board 110, circuit board 120, and circuit board 130) may be formed. Each circuit board includes an insulating substrate and conductive vias, with the conductive vias disposed in the insulating substrate and connecting opposite sides of the insulating substrate. For example, circuit board 130 includes an insulating substrate 132 and conductive vias 136 disposed in the insulating substrate 132, with the conductive vias 136 connecting opposite sides of the insulating substrate 132 (e.g., ...). Figure 1 (As shown).

[0060] Taking circuit board 130 as an example, the method of forming circuit board 130 includes the following steps. Please refer to... Figure 4A First, an initial circuit board 430 is provided, which can be a general copper foil substrate (CCL). The initial circuit board 430 includes an insulating substrate 132 and metal layers 404a and 404b located on opposite sides of the insulating substrate 132. The insulating substrate 132 can be made of a polymer, such as resin, and the metal layers 404a and 404b can be deposited on the insulating substrate 132. Furthermore, the material of the metal layers 404a and 404b can include copper.

[0061] Next, laser drilling can be used to drill through the metal layer 404a and the insulating substrate 132, so that the initial circuit board 430 has through holes 406V, in order to form as shown in the figure. Figure 4A The structure shown is for your reference. Figure 4A and Figure 4B After forming the via 406V, a metal material, such as copper, can be deposited on the inner wall of the via 406V by means of electroplating, to form a portion of the conductive via 136. This portion of the conductive via 136 is located between metal layers 404a and 404b and is electrically connected to metal layers 404a and 404b.

[0062] Please refer to this as well. Figure 4B and Figure 4C After forming a portion of the conductive via 136, metal layers 404a and 404b, as well as a portion of the conductive via 136, can be removed by means such as chemical mechanical polishing (CMP) to expose surfaces 132f and 132s of the insulating substrate 132. Next, seed layers 434a and 434b can be deposited on surfaces 132f and 132s of the insulating substrate 132, respectively, by means such as sputtering or electroplating. The materials of seed layers 434a and 434b can include, for example, titanium, copper, or similar conductive materials. The insulating substrate 132 is located between seed layers 434a and 434b, and seed layer 434a is electrically connected to seed layer 434b through a portion of the conductive via 136.

[0063] After depositing seed layers 434a and 434b, please refer to... Figure 4D Multiple nanowires 405 can be formed on at least one end face 136e of the conductive via 136 by means such as electroplating. Specifically, this step involves first depositing pads P2 on seed layers 434a and 434b respectively to form the conductive via 136. Then, multiple nanowires 405 can be formed on the end face 136e of the conductive via 136 by means such as electroplating, and these nanowires 405 extend in a direction away from the end face 136e.

[0064] It is worth mentioning that, in this embodiment, the steps for forming circuit substrate 110 and circuit substrate 120 are similar to the steps for forming circuit substrate 130, and therefore will not be described in detail here. The difference is that nano-metal lines 405 are provided on both opposite sides of circuit substrate 130, while the nano-metal lines 405 are only formed on one side of circuit substrate 110 and one side of circuit substrate 120. However, when the insulating substrate, such as insulating substrate 132, is a glass substrate, in order to improve the adhesion between the glass substrate and the metal, an adhesion promotion layer (APL), such as an oxide or nitride, can be deposited on the surface 132f and surface 132s of the insulating substrate 132 and on the inner wall of the via 406V.

[0065] For example, the oxide of the subsequent promoting layer can include, for example, titanium oxide, silicon dioxide, or aluminum oxide, while the nitride of the subsequent promoting layer can include, for example, silicon nitride. Furthermore, the thickness of the subsequent promoting layer can range from 0.01 nm to 100 nm.

[0066] Please refer to this as well. Figure 4E and Figure 5 After the nano metal lines 405 are formed, the seed layers 434a and 434b (illustrated in the figure) can be removed or patterned by photolithography and etching. Figure 4D ), so as to expose a portion of the surface 132f and surface 132s of the insulating substrate 132. Figure 5 A partial top view of the circuit board 130 is shown. Figure 5 The seed layers 434a and 434b of the circuit substrate 130 have been removed, and nano metal lines 405 have been provided on the conductive vias 136 of the circuit substrate 130. Although Figure 5 The distribution area of ​​the nano-metal wires 405 is circular, but the present invention is not limited to this. The distribution area of ​​the nano-metal wires 405 can be adjusted according to the shape of the pad P2 of the conductive via 136. In other words, the distribution area of ​​the nano-metal wires 405 can also be square, triangular, or other patterns.

[0067] Next, as Figure 4EAs shown, circuit boards 110, 120, and 130 can be laminated by heating and pressurizing. During the lamination process, nanowires 405 located on conductive vias 136 are aligned with conductive vias 116 (and 126). These nanowires 405 are located between conductive vias 116 and 126. Specifically, nanowires 405 disposed on one end face 136e of conductive via 136 are located between conductive vias 136 and 116, while nanowires 405 disposed on the other end face 136e of conductive via 136 are located between conductive vias 136 and 126.

[0068] In addition, the nano metal lines 405 disposed on the conductive vias 116 of the circuit substrate 110 and the conductive vias 126 of the circuit substrate 120 are also located between the conductive vias 116 and 126. In other words, the nano metal lines 405 disposed on the circuit substrates 110 and 120 are arranged facing each other.

[0069] In this way, after the nanowires 405 are mated and pressed together, conductive layers 150 and 160 are formed on the nanowires 405. Specifically, the nanowires 405 are deformed by extrusion, and the conductive layers (e.g., conductive layer 150) formed by extrusion contain nanopore structures. Furthermore, metal atoms (e.g., copper atoms) in the nanowires 405 can diffuse to another nanowire 405 mated with this nanowire 405 or to conductive vias 116 (and 126), thereby forming a metal bond. Therefore, conductive vias 116, 126, and 136 can be electrically connected through conductive layers 150 and 160.

[0070] For example, in Figure 4E In one embodiment, after the nano-metal line 405 located on one side of the circuit substrate 130 and the nano-metal line 405 located on the circuit substrate 110 are mated and pressed together, a conductive layer 150 is formed between the conductive via 136 and the conductive via 116. On the other hand, after the nano-metal line 405 located on the other side of the circuit substrate 130 and the nano-metal line 405 located on the circuit substrate 120 are mated and pressed together, a conductive layer 160 is formed between the conductive via 136 and the conductive via 126.

[0071] However, in Figure 6In another embodiment illustrated, the nanowire 405 located on one side of the circuit substrate 130 is mated with the conductive via 116 of the circuit substrate 110 and directly contacts the conductive via 116 after lamination. The nanowire 405 located on the other side of the circuit substrate 130 is mated with the conductive via 126 of the circuit substrate 120 and directly contacts the conductive via 126 after lamination.

[0072] Please refer to this as well. Figure 1 and Figure 4E The method for manufacturing the circuit board further includes: after laminating the circuit substrate 110 and the circuit substrate 130, forming an insulating layer 170a on the circuit substrate 110. This insulating layer 170a is located between the circuit substrate 110 and the circuit substrate 130 and surrounds the periphery of the conductive layer 150. Furthermore, this step also includes forming an insulating layer 170b on the circuit substrate 120. This insulating layer 170b is located between the circuit substrate 120 and the circuit substrate 130 and surrounds the periphery of the conductive layer 160.

[0073] It is worth mentioning that the method of forming insulating layer 170a and insulating layer 170b may include: first filling the gap between circuit board 110, circuit board 120 and circuit board 130 with insulating material (not shown), and then hardening the insulating material by baking, drying or UV irradiation to form insulating layer 170a and insulating layer 170b.

[0074] Please refer to Figure 6 In this embodiment, the circuit board manufacturing method further includes: before laminating the circuit board 110 and the circuit board 130, providing an insulating material 670a on a nano-metal line 405 located on one side (upper side) of the circuit board 130. This insulating material 670a covers the end face 136e of the conductive via 136, and the insulating material 670a encapsulates the nano-metal line 405. On the other hand, this step further includes: providing an insulating material 670b on the nano-metal line 405 located on the other side (lower side) of the circuit board 130. This insulating material 670b covers the other end face 136e of the conductive via 136, and the insulating material 670b encapsulates the nano-metal line 405.

[0075] Next, conductive vias 116 and 126 are attached to the nanowire 405 so that they directly contact the nanowire 405. Specifically, since the insulating materials 670a and 670b are in a fluid state before being cured by baking, drying, or UV light, when the end face (not shown) of the conductive via 116 of the circuit board 110 and the end face (not shown) of the conductive via 126 of the circuit board 120 come into contact with the insulating materials 670a and 670b covering the nanowire 405, the insulating material 670a is forced to overflow elsewhere, thereby allowing the conductive vias 116 and 126 to directly contact the nanowire 405.

[0076] After the conductive vias 116 and 126 are in direct contact with the nanowire 405, the insulating materials 670a and 670b can be hardened by baking, drying, or UV irradiation to form a structure similar to... Figure 1 Insulating layers 170a and 170b are shown. At this point, the structure is roughly formed as shown... Figure 1 The circuit board 100 is shown.

[0077] Please refer to Figure 7 Another embodiment of the circuit board 700, similar to circuit board 200, includes a circuit substrate 110, a circuit substrate 120, and a conductive layer 150. The difference between the two circuit boards is that circuit board 700 also includes two layers of photoresist material 790a and two layers of photoresist material 790b. Photoresist material 790a is located on opposite sides of circuit substrate 110, while photoresist material 790b is located on opposite sides of circuit substrate 120. An insulating layer 770 located between photoresist material 790a and photoresist material 790b surrounds conductive layer 150. In other embodiments of the invention, only photoresist material 790a and insulating layer 770 may be included between circuit substrate 110 and circuit substrate 120. It is worth noting that in at least one step of the above-described circuit board manufacturing method, such as photoresist or lithography, photoresist material 790a and photoresist material 790b can be formed in circuit board 700 if the photoresist used in the process is not removed.

[0078] In summary, by placing nano-metal lines on the bonding surfaces of the circuit board substrates, a conductive layer containing nano-pore structures is formed between the connected conductive vias. This increases the connection strength between the conductive vias of each circuit board substrate without affecting electrical connections, thus improving the reliability of the circuit board. Therefore, when the insulating substrate of the circuit board is a glass substrate, the aspect ratio of the conductive vias in the glass substrate can be increased by stacking multiple circuit boards, thereby expanding the application range of the circuit board.

[0079] Although the invention has been described above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains may make some modifications and refinements without departing from the spirit and scope of this invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

Claims

1. A circuit board, characterized in that, Include: Two first circuit boards are stacked on top of each other, and each of the first circuit boards includes: Insulating substrate; A first conductive via is disposed in the insulating substrate, and the first conductive via connects opposite sides of the insulating substrate; and A first conductive layer is disposed between the first conductive vias, wherein the first conductive vias are electrically connected through the first conductive layer, and the first conductive layer includes a nanopore structure.

2. The circuit board as described in claim 1, characterized in that, Also includes: An insulating layer is disposed between the first circuit substrates and surrounds the periphery of the first conductive layer.

3. The circuit board as described in claim 1, characterized in that, Also includes: A conductive post is disposed on the first conductive layer and located between one of the first conductive vias and the first conductive layer, wherein one of the first conductive vias is electrically connected to the first conductive layer through the conductive post.

4. The circuit board as described in claim 1, characterized in that, Each of the first conductive vias includes: Two pads are respectively disposed on opposite end faces of the first conductive via, wherein the first conductive via is connected to the first conductive layer through one of the pads.

5. The circuit board as described in claim 1, characterized in that, At least one of the insulating substrates is a glass substrate.

6. The circuit board as described in claim 1, characterized in that, Also includes: A second circuit substrate is disposed between the first circuit substrates, and the second circuit substrate is located between one of the first circuit substrates and the first conductive layer, wherein the second circuit substrate comprises: The second conductive via connects the opposite sides of the second circuit substrate and is electrically connected to the first circuit substrate, and the second conductive via is connected to one of the first conductive vias through the first conductive layer. as well as A second conductive layer is disposed on the second conductive via, wherein the second circuit board is located between the first conductive layer and the second conductive layer, and the second conductive via is connected to the other of the first conductive via through the second conductive layer, wherein the second conductive layer includes a nano-pore structure.

7. A method for manufacturing a circuit board, characterized in that, Include: At least two circuit boards are formed, and each of the circuit boards comprises: Insulating substrate; A conductive via is disposed in the insulating substrate, and the conductive via connects opposite sides of the insulating substrate; On at least one end face of one of the conductive vias, a plurality of nano metal lines are formed, and the nano metal lines extend in a direction away from the end face. as well as After the nanowires are formed, the circuit board is laminated, wherein the nanowires located on one of the conductive vias are aligned with the other of the conductive vias, and the nanowires are located between the conductive vias to form a conductive layer, wherein the conductive vias are electrically connected through the conductive layer, and the conductive layer contains a nanopore structure.

8. The manufacturing method as described in claim 7, characterized in that, Also includes: After the circuit board is laminated, an insulating layer is formed on the circuit board and the insulating layer is located between the circuit boards, wherein the insulating layer surrounds the periphery of the conductive layer.

9. The manufacturing method as described in claim 7, characterized in that, Also includes: Before laminating the circuit board, an insulating material is disposed on the nano-metal wire, wherein the insulating material covers the end face of one of the conductive vias and the insulating material encapsulates the nano-metal wire; and The other of the conductive via is attached to the nanowire so that the other of the conductive via directly contacts the nanowire.

10. The manufacturing method as described in claim 7, characterized in that, At least one of the insulating substrates of the circuit board is a glass substrate.

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