SGTMOSFET with Ultra-Low Gate Charge and its Fabrication Method

Abstract

This invention discloses an SGT MOSFET with ultra-low gate charge and its fabrication method. The fabrication method includes: selecting an N-type substrate and growing an epitaxial layer on the upper surface of the N-type substrate; etching to form a deep trench structure extending into the epitaxial layer; forming a field oxide layer within the deep trench structure and forming field oxide trenches within the field oxide layer; growing polysilicon material inside the field oxide trenches to form the source electrode; forming gate polysilicon filling trenches on both sides of the upper surface of the field oxide layer; growing polysilicon material within the gate polysilicon filling trenches and above the source electrode to form the gate and floating polysilicon layers; forming a body injection layer and a source injection layer within the epitaxial layer on both sides of the gate; depositing a dielectric layer and etching multiple contact holes on the dielectric layer; and growing a front metal layer and a back metal layer. This invention can significantly reduce gate-source parasitic capacitance and achieve ultra-low gate charge characteristics.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to an SGTMOSFET with ultra-low gate charge and its fabrication method. Background Technology

[0002] In recent years, the demand for power semiconductor devices has surged in fields such as new energy, industrial control, and consumer electronics. Among them, SGT MOSFETs (semiconductor-shielded trench MOSFETs) have become core devices for medium and low voltage applications due to their excellent charge balance capability and low switching losses. In the voltage range of 120~250V, most traditional SGT MOSFETs adopt a symmetrical structure design, and their gate-source contact area is relatively large, resulting in a significant increase in gate-source parasitic capacitance (Cgs).

[0003] Specifically, the increase in gate charge (Qg) of this structure will directly cause the following problems: (1) Increased switching loss: High gate charge will prolong the switching time of the device, resulting in increased energy loss during the turn-on and turn-off process; (2) Reduced driving efficiency: The driving circuit needs to provide a higher amount of charge to complete the gate charging and discharging, increasing the system power consumption; (3) Limited thermal stability: The heat accumulation caused by parasitic capacitance affects the reliability of the device.

[0004] Therefore, there is an urgent need for an SGT MOSFET device that balances process feasibility and electrical performance to fundamentally solve the problem of excessive gate charge. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an SGT MOSFET with ultra-low gate charge and its fabrication method.

[0006] One aspect of the present invention provides a method for fabricating an SGT MOSFET with ultra-low gate charge, comprising:

[0007] S1: Select an N-type substrate, and sequentially grow an epitaxial layer, a first oxide layer, a silicon nitride layer, and a second oxide layer on the upper surface of the N-type substrate, wherein the first oxide layer, the silicon nitride layer, and the second oxide layer constitute an ONO composite hard mask layer.

[0008] S2: Using the ONO composite hard mask layer as a mask, a deep trench structure extending from the upper surface of the second oxide layer to the interior of the epitaxial layer is etched.

[0009] S3: A field plate oxide layer is grown inside the deep trench structure, and a field plate oxide layer trench is formed inside the field plate oxide layer.

[0010] S4: Deposit polycrystalline silicon material inside the field plate oxide layer trench to form the source electrode, and remove the ONO composite hard mask layer;

[0011] S5: Gate polysilicon filling trenches are formed on the left and right sides of the upper surface of the field plate oxide layer, and gate oxide layers are grown on the sidewalls of the gate polysilicon filling trenches and the upper surface of the source electrode.

[0012] S6: Deposit polysilicon material inside the gate polysilicon filling trench to form a gate, and simultaneously deposit polysilicon material inside the field plate oxide trench to form a floating polysilicon layer.

[0013] S7: A body region implantation layer and a source implantation layer are sequentially formed in the epitaxial layers on both sides of the gate;

[0014] S8: Deposit a dielectric layer on the upper surface of the device, and etch a plurality of contact holes on the dielectric layer, wherein the plurality of contact holes extend downward to the body injection layer, the gate or the source, respectively;

[0015] S9: A front metal layer is grown on the upper surface of the device, the front metal layer filling all contact holes, and a back metal layer is grown on the lower surface of the N-type substrate.

[0016] Another aspect of the present invention provides an SGT MOSFET with ultra-low gate charge, comprising an N-type substrate and an epitaxial layer, wherein,

[0017] The epitaxial layer is disposed on the upper surface of the N-type substrate. A deep trench structure is formed on the upper surface of the epitaxial layer. A field plate oxide layer is disposed inside the deep trench structure. The surface region of the device is divided into a unit cell region, gate lead-out regions located on both sides of the unit cell region, and source lead-out regions located on both sides of the corresponding gate lead-out regions. The deep trench structure extends from the outer edge of the source lead-out region on the first side to the outer edge of the source lead-out region on the second side.

[0018] The oxide layer of the field plate has grooves along its length, and a source electrode is disposed inside the grooves of the oxide layer of the field plate.

[0019] Gate polysilicon filling trenches are formed on both sides of the upper surface of the field plate oxide layer, and gate oxide layers are formed on the sidewalls of the gate polysilicon filling trenches and the upper surface of the source electrode.

[0020] A gate is disposed inside the gate polysilicon filling trench, and a floating polysilicon layer is disposed inside the field oxide trench. The floating polysilicon layer is separated from the source by the gate oxide layer. A body injection layer and a source injection layer are disposed sequentially in the epitaxial layers on both sides of the gate. A dielectric layer is deposited on the upper surface of the device, and a plurality of contact holes are formed on the dielectric layer. The plurality of contact holes extend downward to the body injection layer, the gate, or the source, respectively.

[0021] A front metal layer is grown on the upper surface of the device, which fills all contact holes, and a back metal layer is formed on the lower surface of the N-type substrate.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] 1. This invention provides an SGT MOSFET with ultra-low gate charge and its fabrication method. The width of the residual field plate oxide layer in the SGT MOSFET can be adjusted by selecting different photomasks during photolithography etching, which can reduce the gate-source parasitic capacitance. A floating polysilicon layer is formed above the source and spaced apart from the source. This floating polysilicon layer replaces the gate polysilicon or source polysilicon in the existing device structure, and has the function of shielding the original gate-source parasitic capacitance, which can significantly reduce the gate-source parasitic capacitance and achieve ultra-low gate charge characteristics. This effectively solves the problems of switching loss and driving efficiency caused by excessive gate charge in traditional SGT MOSFETs. Moreover, the fabrication process is easy to implement and has low cost.

[0024] 2. This invention improves switching speed and response performance by reducing gate-source parasitic capacitance: shortening turn-on / turn-off delay, increasing switching speed, improving device dynamic response time, and reducing the risk of Miller plateau oscillation caused by resonance due to trace inductance; reducing drive losses and device power consumption, reducing drive charge Qg requirements, and alleviating pressure on the drive chip; optimizing thermal management and reliability, shortening turn-on and turn-off times, reducing switching losses, and reducing heat generated by turn-on losses, reducing MOSFET temperature rise, and reducing the risk of increased parasitic conduction caused by excessively large gate-source capacitance coupling in dV / dT (rate of change of voltage) scenarios; supporting high-frequency and high-density designs, the reduced turn-on / turn-off time allows for higher device switching frequencies, breaking frequency limitations, allowing the use of smaller gate resistors, and reducing board area footprint.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0026] Figure 1This is a flowchart illustrating a method for fabricating an SGT MOSFET with ultra-low gate charge according to an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram illustrating the fabrication process of an N-type substrate and an epitaxial layer according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram illustrating the fabrication process of an ONO composite hard mask layer provided in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram illustrating the fabrication process of a deep trench structure provided in an embodiment of the present invention;

[0030] Figure 5 This is a top view of the deep trench structure distribution of the entire device provided in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram illustrating the preparation process of an oxide layer on a field plate according to an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the deposition of a polycrystalline silicon material provided in an embodiment of the present invention;

[0033] Figure 8 This is a top view schematic diagram illustrating the structure of the source electrode provided in an embodiment of the present invention;

[0034] Figure 9 It is along Figure 8 A schematic diagram of the cross-section intercepted by line segment MM in the diagram;

[0035] Figure 10 It is along Figure 8 A schematic diagram of the cross-section intercepted by line segment NN in the diagram;

[0036] Figure 11 This is a schematic diagram illustrating the fabrication of a gate polysilicon filling trench according to an embodiment of the present invention;

[0037] Figure 12 This is a schematic diagram illustrating the fabrication of a gate oxide layer according to an embodiment of the present invention;

[0038] Figure 13 This is a schematic diagram of the deposition process of a polycrystalline silicon layer provided in an embodiment of the present invention;

[0039] Figure 14 This is a schematic diagram illustrating the fabrication process of a gate and a floating polysilicon layer according to an embodiment of the present invention;

[0040] Figure 15 This is a schematic diagram of the injection process of a body injection layer and a source injection layer provided in an embodiment of the present invention;

[0041] Figure 16 This is a schematic diagram of the preparation process of a dielectric layer provided in an embodiment of the present invention;

[0042] Figure 17 This is a top view of the vertical projection position of each contact hole provided in an embodiment of the present invention;

[0043] Figure 18 It is along Figure 17 A cross-sectional view of line segment FF in the diagram;

[0044] Figure 19 It corresponds Figure 17 A cross-sectional view of the device with line segment FF in the diagram;

[0045] Figure 20 It corresponds Figure 17 A cross-sectional view of the device for line segment DD in the diagram;

[0046] Figure 21 It corresponds Figure 17 The cross-sectional view of the device for line segment EE in the diagram.

[0047] Explanation of reference numerals in the attached figures:

[0048] 1-N-type substrate; 2-Epipolar layer; 3-First oxide layer; 4-Silicon nitride layer; 5-Second oxide layer; 6-Deep trench structure; 7-Field plate oxide layer; 8-Field plate oxide layer trench; 9-Source; 10-Gate polysilicon filling trench; 11-Gate oxide layer; 12-Gate; 13-Bulk region implantation layer; 14-Source implantation layer; 15-Dielectric layer; 16-Contact hole; 17-Front side metal layer; 18-Back side metal layer; 19-Floating polysilicon layer; A-Unit cell region; B-Gate lead-out region; C-Source lead-out region. Detailed Implementation

[0049] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, an SGT MOSFET with ultra-low gate charge and its fabrication method according to the present invention.

[0050] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0051] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0052] Example 1

[0053] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for fabricating an SGT MOSFET with ultra-low gate charge according to an embodiment of the present invention. The fabrication method includes:

[0054] S1: Select an N-type substrate 1, and grow an epitaxial layer 2, a first oxide layer 3, a silicon nitride layer 4, and a second oxide layer 5 sequentially on the upper surface of the N-type substrate 1, wherein the first oxide layer 3, the silicon nitride layer 4, and the second oxide layer 5 constitute an ONO composite hard mask layer.

[0055] Specifically, firstly, a highly doped N-type substrate 1 is selected, and an epitaxial layer 2 is grown on the upper surface of the N-type substrate 1, such as... Figure 2 As shown. In this embodiment, both the N-type substrate 1 and the epitaxial layer 2 are doped silicon materials. The doping concentration of the N-type substrate 1 is higher than that of the epitaxial layer 2. The thickness of the epitaxial layer 2 is 5~15μm, serving as the drift region of the device. The resistivity of the N-type substrate 1 ranges from 0.0005~0.003Ω·cm, and its thickness is approximately 725μm. The resistivity of the epitaxial layer 2 ranges from 0.05~0.6Ω·cm.

[0056] Subsequently, a first oxide layer 3, a silicon nitride layer 4, and a second oxide layer 5 are sequentially grown on the upper surface of the epitaxial layer 2, as follows: Figure 3 As shown, the first oxide layer 3, the silicon nitride layer 4, and the second oxide layer 5 together constitute an ONO composite hard mask layer. In this embodiment, the thickness of the first oxide layer 3 is 100 mm. (Å), the thickness of silicon nitride layer 4 is 1500. The thickness of the second oxide layer 5 is 4000 mm. The ONO composite hard mask layer is used to control the etching verticality of the deep trench structure 6 in subsequent processes. In this embodiment, both the first oxide layer 3 and the second oxide layer 5 can be silicon dioxide.

[0057] S2: Using the ONO composite hard mask layer as a mask, a deep trench structure 6 extending from the upper surface of the second oxide layer 5 to the interior of the epitaxial layer 2 is etched.

[0058] Specifically, by irradiating with ultraviolet light, the pattern on the photomask is projected onto the photoresist coated on the surface of the ONO composite hard mask layer. The photochemical properties of the photoresist are used to form a patterned photoresist mask, which is then used to etch the ONO composite hard mask layer. After etching, a portion of the ONO composite hard mask layer is exposed, revealing the underlying epitaxial layer 2, forming an "etching window." Subsequently, the exposed epitaxial layer 2 beneath the ONO composite hard mask layer is etched to form a deep trench structure 6, such as... Figure 4 As shown.

[0059] It should be noted that, Figure 4 This is a cross-sectional view of a unit cell of the fabricated SGT MOSFET. Each unit cell includes a deep trench structure 6; however, the entire device surface is formed simultaneously during device fabrication. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a top view of the deep trench structure distribution of the entire device provided in an embodiment of the present invention. From Figure 5 As can be seen, the surface area of ​​the entire device can be divided into the central unit cell region A, the gate lead-out regions B on both sides of unit cell region A, and the source lead-out regions C on both sides of the corresponding gate lead-out regions B. The entire device includes multiple parallel deep trench structures 6, each deep trench structure 6 being elongated, extending from the outer edge of the source lead-out region C on the first side to the outer edge of the source lead-out region C on the second side. It should be noted that this top view is for schematic purposes only and does not represent the actual number and size relationships.

[0060] In this embodiment, the deep trench structure 6 has a depth of 8~10μm, a width of 2.8~4μm, and a depth-to-width ratio of 2.5:1~3.5:1.

[0061] S3: Using a wet oxidation process, a field plate oxide layer 7 is formed inside the deep trench structure 6, and a field plate oxide layer trench 8 is formed inside the field plate oxide layer 7.

[0062] In this embodiment, the thickness of the field plate oxide layer 7 is 0.75~1.1μm, used to improve the breakdown voltage and isolate the source and drain. It should be noted that the field plate oxide layer 7 covers the upper surface and edges of the deep trench structure 6, but does not completely cover the entire deep trench structure 6, thus forming a field plate oxide layer trench 8 inside the field plate oxide layer 7, such as... Figure 6 As shown, the oxide layer groove 8 of the field plate still appears as a long strip when viewed from the top view.

[0063] It should be noted that, in the actual fabrication process, a wet oxidation process is used to simultaneously form a field plate oxide layer 7 inside all the deep trench structures 6 of the entire device.

[0064] S4: Deposit polysilicon material inside the field plate oxide trench 8 to form source electrode 9 and remove ONO composite hard mask layer.

[0065] Step S4 in this embodiment specifically includes:

[0066] S4.1: Polycrystalline silicon material is simultaneously deposited on the upper surface of the ONO composite hard mask layer, the upper surface of the field oxide layer 7, and inside the field oxide layer trench 8.

[0067] Specifically, polysilicon material is deposited on the entire upper surface of the device, filling the interior of the entire field oxide trench 8 and covering the entire upper surface of the ONO composite hard mask layer and the field oxide layer 7, such as... Figure 7 As shown.

[0068] S4.2: Use etching process to remove the polysilicon material on the upper surface of the ONO composite hard mask layer and the upper surface of the field oxide layer 7, and etch the polysilicon material inside the field oxide trench 8 until it is flush with the upper surface of the epitaxial layer 2.

[0069] S4.3: The ONO composite hard mask layer is removed by photolithography and etching processes, and the polysilicon material inside the field plate oxide trench 8 located in the unit cell region A of the device is etched to a preset depth to form the source electrode 9.

[0070] Specifically, please see Figure 8 , Figure 8 This is a top view schematic diagram illustrating the distribution of the source electrodes provided in an embodiment of the present invention. Figure 9 It is along Figure 8 A cross-sectional view of line segment MM in the diagram; Figure 10 It is along Figure 8 The cross-sectional view of line segment NN in the diagram. The polysilicon material inside the field oxide trench 8 of the unit cell region A of the entire device is etched to a predetermined depth, such that the upper surface of the source 9 located in unit cell region A is lower than the upper surface of the epitaxial layer 2, as shown. Figure 10 As shown; the upper surface of the source 9, located at the gate lead-out region B and the source lead-out region C, is flush with the upper surface of the epitaxial layer 2, as shown. Figure 9 As shown. Therefore, the thickness of the source 9 in unit cell region A is less than the thickness of the source 9 at gate lead-out region B and source lead-out region C.

[0071] S5: A gate polysilicon filling trench 10 is formed on the left and right sides of the upper surface of the field plate oxide layer 7, and a gate oxide layer 11 is grown on the sidewall of the gate polysilicon filling trench 10 and the upper surface of the source electrode 9.

[0072] First, a predetermined depth is etched away on the left and right sides of the upper surface of the field oxide layer 7 using photolithography and etching processes, thereby forming a gate polysilicon filling trench 10 on the left and right sides of the upper surface of the field oxide layer 7, as shown below. Figure 11 As shown, the outer wall of each gate polysilicon filling trench 10 is an epitaxial layer 2, and the inner wall is an unetched field oxide layer 7, i.e., a residual field oxide layer, which separates it from the source electrode 9. Along the length of the field oxide layer 7, the gate polysilicon filling trench 10 extends from the outer edge of the source electrode exit region C on the first side to the outer edge of the source electrode exit region C on the second side, and the depth of the gate polysilicon filling trench 10 is equal in the unit cell region A, the gate exit region B, and the source electrode exit region C. It should be noted that... Figures 11 to 16 All are in Figure 10 The preparation process diagram is based on the cross-sectional view, which is the cross-sectional view of the protocell region A.

[0073] In this embodiment, the width of the gate polysilicon filling trench 10 is greater than or equal to 0.35 μm, and the depth is 0.65~1.5 μm; the residual field plate oxide layer serves as an isolation layer between the gate and the source, and its thickness is 0.4~0.7 μm. The width of the residual field plate oxide layer can be adjusted by selecting different photomasks during photolithography and etching, which can reduce the gate-source parasitic capacitance.

[0074] Subsequently, a gate oxide layer 11 is grown on the outer wall of the gate polysilicon filling trench 10, the upper surface of the epitaxial layer 2, and the upper surface of the source electrode 9, as follows: Figure 12 As shown, specifically, the gate oxide layer 11 covers the upper surface of the epitaxial layer 2, the outer wall of the gate polysilicon filling trench 10, and the upper surface of the source electrode 9. In this embodiment, the gate oxide layer 11 is made of silicon dioxide and is formed by oxidizing the epitaxial layer 2 and the source electrode 9. The thickness of the gate oxide layer 11 is 400~1200 mm. , used to isolate the gate polysilicon material and the epitaxial layer 2.

[0075] S6: Polysilicon material is deposited inside the gate polysilicon filling trench 10 to form the gate 12, and polysilicon material is deposited inside the field plate oxide trench 8 to form the floating polysilicon layer 19.

[0076] Specifically, firstly, polysilicon material is deposited on the entire upper surface of the device, such that the upper surface of the gate oxide layer 11, the interior of the gate polysilicon filling trench 10, the upper surface of the residual field oxide layer, and the interior of the field oxide trench 8 are all covered with a polysilicon layer, such as... Figure 13 As shown.

[0077] Subsequently, the polysilicon layer is etched using a predetermined mask, retaining only the polysilicon layers inside the gate polysilicon filling trench 10 and the field oxide trench 8. The height of the etched polysilicon layer is made slightly lower than the heights of the gate polysilicon filling trench 10 and the field oxide trench 8, so that the gate 12 is formed inside the gate polysilicon filling trench 10, and a floating polysilicon layer 19 is formed inside the field oxide trench 8. The floating polysilicon layer 19 is separated from the source 9 by the gate oxide layer 11. Figure 14 As shown. In this embodiment, the top of the etched gate 12 is 500~1500 mm below the upper surface of the epitaxial layer 2. .

[0078] It should be noted that the floating polycrystalline silicon layer 19 formed inside the field plate oxide trench 8 exists only in the unit cell region A.

[0079] S7: A body injection layer 13 and a source injection layer 14 are sequentially formed in the epitaxial layer 2 on both sides of the gate 12, such as Figure 15 As shown.

[0080] Preferably, in this embodiment, the implanted ions in the body implantation layer 13 are boron ions, and the implanted ions in the source implantation layer 14 are arsenic ions. The concentration of implanted ions and the depths of the formed body implantation layer 13 and source implantation layer 14 can be adjusted according to actual needs and are not limited here. In addition, after forming the body implantation layer 13 and source implantation layer 14, this embodiment performs a rapid thermal annealing (RTA) process at a temperature of 900~1050℃ for a time of 10~60 seconds to repair lattice damage caused by ion implantation.

[0081] S8: A dielectric layer 15 is deposited on the upper surface of the device, and a plurality of contact holes 16 are etched on the dielectric layer 15. The plurality of contact holes 16 extend downward to the body injection layer 13, the gate 12 or the source 9, respectively.

[0082] Specifically, firstly, a silicon dioxide material is deposited on the entire upper surface of the device to form a dielectric layer 15, such as... Figure 16 As shown. In this embodiment, the dielectric layer 15 is an insulating isolation layer (ILD) with a thickness of 4000~12000. .

[0083] Subsequently, using photolithography and etching processes, multiple contact holes 16 are formed at different locations on the dielectric layer 15. Please refer to... Figure 17 , Figure 17 This is a top view showing the vertical projection positions of each contact hole, such as... Figure 17As shown, contact holes 16 are etched at different positions on the dielectric layer 15 of the unit cell region A, gate lead-out region B, and source lead-out region C of the device. The contact hole 16 in unit cell region A is located above the body implantation layer 13 and the source implantation layer 14, and extends downward into the body implantation layer 13. Figure 18 As shown, it appears as a long strip when viewed from above. The contact holes 16 of the gate lead-out region B are located above the gates 12 on both the left and right sides, extending downwards into the interior of the gates 12, as shown... Figure 20 As shown. Further, one type of contact hole 16 in the source lead-out region C is formed above the body injection layer 13 and the source injection layer 14 on both the left and right sides and extends downward to the body injection layer 13; another type of contact hole 16 is formed above the source 9 and extends downward to the source 9, as shown. Figure 21 As shown.

[0084] Preferably, the aspect ratio of all contact holes 16 does not exceed 3:1.

[0085] S9: A front metal layer 17 is grown on the upper surface of the device, which fills all the contact holes 16 to contact the corresponding layers, and a back metal layer 18 is formed on the lower surface of the N-type substrate 1.

[0086] Specifically, a front-side metal layer 17 is grown on the entire upper surface of the device, such that the front-side metal layer 17 fills all the contact holes 16, thereby making the front-side metal layer 17 contact the unit cell region A, the bulk implantation layer 13, and the source implantation layer 14, as shown below. Figure 19 As shown; this makes the front metal layer 17 contact the gate 12 in the gate lead-out region B, as... Figure 20 As shown; this ensures that the front metal layer 17 simultaneously contacts the source electrode 9 in the source lead-out region C, and the source electrode 9 in the bulk implantation layer 13, as well as the source electrode implantation layer 14. Figure 21 As shown. Subsequently, a back metal layer 18 is formed on the lower surface of the N-type substrate 1.

[0087] Furthermore, a passivation layer (not shown in the figure) is also covered on the surface of the front metal layer 17. The passivation layer material is silicon nitride or polyimide, and the thickness is 0.5~10μm.

[0088] This invention provides an SGT MOSFET with ultra-low gate charge and its fabrication method. The width of the residual field plate oxide layer in the SGT MOSFET can be adjusted during photolithography by selecting different photomasks, which can reduce the gate-source parasitic capacitance. A floating polysilicon layer is formed above the source and spaced apart from the source. This floating polysilicon layer replaces the gate polysilicon or source polysilicon in the existing device structure, and has the function of shielding the original gate-source parasitic capacitance, which can significantly reduce the gate-source parasitic capacitance and achieve ultra-low gate charge characteristics. This effectively solves the problems of switching loss and driving efficiency caused by excessive gate charge in traditional SGT MOSFETs. Moreover, the fabrication process is easy to implement and has low cost.

[0089] Example 2

[0090] Please see also Figures 19 to 21 Based on Embodiment 1, this embodiment provides an SGT MOSFET with ultra-low gate charge, including an N-type substrate 1 and an epitaxial layer 2. The epitaxial layer 2 is disposed on the upper surface of the N-type substrate 1, and a deep trench structure 6 is formed on the upper surface of the epitaxial layer 2. The deep trench structure 6 is filled with a field oxide layer 7. The surface region of this SGT MOSFET device can be divided into a unit cell region A located in the middle, gate lead-out regions B located on both sides of the unit cell region A, and source lead-out regions C located on both sides of the corresponding gate lead-out regions B. The deep trench structure 6 extends from the outer edge of the first source lead-out region C to the outer edge of the second source lead-out region C. A field oxide layer trench 8 is formed along the length direction inside the field oxide layer 7, and a source 9 is disposed inside the field oxide layer trench 8. The height of the source 9 located in the unit cell region A is less than the height of the source 9 located in the gate lead-out region B and the source lead-out region C. Field oxide layer trenches 8 are formed on both sides of the upper surface of the field oxide layer 7. The device has a gate polysilicon filling trench 10, and a gate oxide layer 11 is disposed on the outer wall of the gate polysilicon filling trench 10 and the upper surface of the source electrode 9. A gate 12 is disposed inside the gate polysilicon filling trench 10, and a floating polysilicon layer 19 is disposed inside the field oxide trench 8. The floating polysilicon layer 19 is separated from the source electrode 9 by the gate oxide layer 11. A body injection layer 13 and a source injection layer 14 are sequentially formed in the epitaxial layers 2 on the left and right sides of the gate 12. A dielectric layer 15 is deposited on the upper surface of the device, and a plurality of contact holes 16 are formed on the dielectric layer 15. The plurality of contact holes 16 extend downward to the body injection layer 13, the gate 12 or the source electrode 9, respectively. A front metal layer 17 is grown on the upper surface of the device. The front metal layer 17 fills all the contact holes 16 to contact the corresponding layer. A back metal layer 18 is formed on the lower surface of the N-type substrate 1.

[0091] In this embodiment, the width of the gate polysilicon filling trench 10 is greater than or equal to 0.35 μm and the depth is 0.65~1.5 μm; the residual field plate oxide layer serves as an isolation layer between the gate 12 and the source 9, and its thickness is 0.4~0.7 μm.

[0092] In this embodiment, the width of the residual field plate oxide layer of the SGT MOSFET can be adjusted during photolithography by selecting different photomasks, which can reduce the gate-source parasitic capacitance. A floating polysilicon layer is formed above the source and spaced apart from the source. This floating polysilicon layer replaces the ordinary gate polysilicon or source polysilicon structure and has the function of shielding the original gate-source parasitic capacitance, which can significantly reduce the gate-source parasitic capacitance, achieve ultra-low gate charge characteristics, and effectively solve the switching loss and driving efficiency problems caused by excessive gate charge in traditional SGT MOSFETs.

[0093] This invention improves switching speed and response performance by reducing gate-source parasitic capacitance: it shortens turn-on / turn-off delay, increases switching speed, improves device dynamic response time, and reduces the risk of Miller plateau oscillation caused by resonance due to trace inductance; it reduces drive losses and device power consumption, reduces drive charge Qg requirements, and alleviates pressure on the drive chip; it optimizes thermal management and reliability, shortens turn-on / turn-off time, reduces switching losses, and reduces heat generated by turn-on losses, reducing MOSFET temperature rise and reducing the risk of increased parasitic conduction caused by excessively large gate-source capacitance coupling in dV / dT scenarios; it supports high-frequency and high-density designs, and the reduced turn-on / turn-off time allows for higher device switching frequencies, breaking frequency limitations, allowing the use of smaller gate resistors, and reducing board area footprint.

[0094] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0095] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0096] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an SGT MOSFET with ultra-low gate charge, characterized in that, include: S1: Select an N-type substrate, and sequentially grow an epitaxial layer, a first oxide layer, a silicon nitride layer, and a second oxide layer on the upper surface of the N-type substrate, wherein the first oxide layer, the silicon nitride layer, and the second oxide layer constitute an ONO composite hard mask layer. S2: Using the ONO composite hard mask layer as a mask, a deep trench structure extending from the upper surface of the second oxide layer to the interior of the epitaxial layer is etched. S3: A field plate oxide layer is grown inside the deep trench structure, and a field plate oxide layer trench is formed inside the field plate oxide layer. S4: Deposit polycrystalline silicon material inside the field plate oxide layer trench to form the source electrode, and remove the ONO composite hard mask layer; S5: Gate polysilicon filling trenches are formed on the left and right sides of the upper surface of the field plate oxide layer, and gate oxide layers are grown on the sidewalls of the gate polysilicon filling trenches and the upper surface of the source electrode. S6: Deposit polysilicon material inside the gate polysilicon filling trench to form a gate, and simultaneously deposit polysilicon material inside the field plate oxide trench to form a floating polysilicon layer. S7: A body region implantation layer and a source implantation layer are sequentially formed in the epitaxial layers on both sides of the gate; S8: Deposit a dielectric layer on the upper surface of the device, and etch a plurality of contact holes on the dielectric layer, wherein the plurality of contact holes extend downward to the body injection layer, the gate or the source, respectively; S9: A front metal layer is grown on the upper surface of the device, the front metal layer filling all contact holes, and a back metal layer is grown on the lower surface of the N-type substrate.

2. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 1, characterized in that, The entire SGT MOSFET device includes a central primitive cell region, gate lead-out regions on both sides of the primitive cell region, and source lead-out regions on both sides of the corresponding gate lead-out regions. The entire device has multiple parallel deep trench structures, each deep trench structure is long and narrow, and the length of each deep trench structure extends from the outer edge of the source lead-out area on the first side to the outer edge of the source lead-out area on the second side. The deep trench structure has a depth of 8~10μm, a width of 2.8~4μm, and a depth-to-width ratio of 2.5:1~3.5:

1.

3. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 2, characterized in that, S4 includes: S4.1: Deposit polycrystalline silicon material on the upper surface of the ONO composite hard mask layer, the upper surface of the field plate oxide layer, and inside the trenches of the field plate oxide layer; S4.2: Remove the polysilicon material from the upper surface of the ONO composite hard mask layer and the upper surface of the field oxide layer, and etch the polysilicon material inside the trench of the field oxide layer until it is flush with the upper surface of the epitaxial layer; S4.3: Remove the ONO composite hard mask layer and etch the polysilicon material located in the unit cell region inside the field plate oxide layer trench to a preset depth to form the source electrode.

4. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 3, characterized in that, The upper surface of the source electrode located in the unit cell region is lower than the upper surface of the epitaxial layer; the upper surface of the source electrode located in the gate lead-out region and the source lead-out region is flush with the upper surface of the epitaxial layer, such that the thickness of the source electrode located in the unit cell region is less than the thickness of the source electrode located in the gate lead-out region and the source lead-out region.

5. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 2, characterized in that, S5 includes: S5.1: The preset depths on the left and right sides of the upper surface of the field plate oxide layer are removed by photolithography and etching processes, so that a gate polysilicon filling trench is formed on both sides of the upper surface of the field plate oxide layer. The outer sidewall of the gate polysilicon filling trench is the epitaxial layer, the inner sidewall is the unetched residual field plate oxide layer, and the residual field plate oxide layer is separated from the source electrode. S5.2: A layer with a thickness of 400~1200 mm is grown on the outer wall of the gate polysilicon filling trench, the upper surface of the epitaxial layer, and the upper surface of the source. The gate oxide layer.

6. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 5, characterized in that, The width of the gate polysilicon filling trench is greater than or equal to 0.35 μm, and the depth is 0.65~1.5 μm; the thickness of the residual field plate oxide layer is 0.4~0.7 μm.

7. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 5, characterized in that, S6 includes: S6.1: Deposit polysilicon material on the upper surface of the device such that the upper surface of the gate oxide layer, the interior of the gate polysilicon filling trench, the upper surface of the residual field plate oxide layer, and the interior of the field plate oxide layer trench are all covered with a polysilicon layer. S6.2: Etch the polysilicon layer, retaining only the polysilicon layer inside the gate polysilicon filling trench and the polysilicon layer inside the field oxide trench, and make the height of the etched polysilicon layer slightly lower than the height of the gate polysilicon filling trench and the field oxide trench, so as to form a gate inside the gate polysilicon filling trench and a floating polysilicon layer inside the field oxide trench, wherein the floating polysilicon layer is separated from the source by the gate oxide layer.

8. The method for fabricating an SGT MOSFET with ultra-low gate charge according to claim 5, characterized in that, S7 includes: Contact holes are respectively formed at predetermined positions on the dielectric layer of the device cell region, gate lead-out region, and source lead-out region. The contact holes of the cell region are formed above the body injection layer and the source injection layer and extend downward into the body injection layer. The contact holes of the gate lead-out region are formed above the gate and extend downward into the gate. The first type of contact hole of the source lead-out region is formed above the body injection layer and the source injection layer and extends downward into the body injection layer. The second type of contact hole of the source lead-out region is formed above the source and extends downward into the source.

9. An SGT MOSFET with ultra-low gate charge, characterized in that, The SGT MOSFET is fabricated using the fabrication method according to any one of claims 1 to 8, and comprises an N-type substrate and an epitaxial layer, wherein... The epitaxial layer is disposed on the upper surface of the N-type substrate. A deep trench structure is formed on the upper surface of the epitaxial layer. A field plate oxide layer is disposed inside the deep trench structure. The surface region of the device is divided into a unit cell region, gate lead-out regions located on both sides of the unit cell region, and source lead-out regions located on both sides of the corresponding gate lead-out regions. The deep trench structure extends from the outer edge of the source lead-out region on the first side to the outer edge of the source lead-out region on the second side. The oxide layer of the field plate has grooves along its length, and a source electrode is disposed inside the grooves of the oxide layer of the field plate. Gate polysilicon filling trenches are formed on both sides of the upper surface of the field plate oxide layer, and gate oxide layers are formed on the sidewalls of the gate polysilicon filling trenches and the upper surface of the source electrode. A gate is disposed inside the gate polysilicon filling trench, and a floating polysilicon layer is disposed inside the field oxide trench. The floating polysilicon layer is separated from the source by the gate oxide layer. A body injection layer and a source injection layer are disposed sequentially in the epitaxial layers on both sides of the gate. A dielectric layer is deposited on the upper surface of the device, and a plurality of contact holes are formed on the dielectric layer. The plurality of contact holes extend downward to the body injection layer, the gate, or the source, respectively. A front metal layer is grown on the upper surface of the device, which fills all contact holes, and a back metal layer is formed on the lower surface of the N-type substrate.

10. The SGT MOSFET with ultra-low gate charge according to claim 9, characterized in that, The upper surface of the source electrode located in the unit cell region is lower than the upper surface of the epitaxial layer; the upper surface of the source electrode located in the gate lead-out region and the source lead-out region is flush with the upper surface of the epitaxial layer, such that the thickness of the source electrode located in the unit cell region is less than the thickness of the source electrode located in the gate lead-out region and the source lead-out region.

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