Integrated circuit testing method, electronic device, and storage medium

Abstract

The application relates to the technical field of computers, and provides a kind of integrated circuit test method, electronic equipment and storage medium, wherein the method comprises: constructing an address conversion model function based on the system architecture information of the integrated circuit to be tested;Based on the input address of each Master module in the integrated circuit to be tested and the address conversion model function, the standard address of each intermediate module and the standard address of each Slave module in the integrated circuit to be tested are generated;Based on the actual output address and standard address of each Slave module and the actual output address and standard address of each intermediate module, the routing test result of the integrated circuit to be tested is obtained.The application can accurately verify the correctness of all possible routing paths in the integrated circuit to be tested, and can more accurately and efficiently find out whether there is a routing error in the intermediate module of the integrated circuit to be tested, which can significantly improve the routing test efficiency, test coverage and integrity of the integrated circuit test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an integrated circuit testing method, electronic device, and storage medium. Background Technology

[0002] In a System-on-Chip (SoC) architecture, modules can be functionally divided into a request initiator (Master), a request receiver (Slave), and intermediate modules. The Master module actively initiates computation or storage requests; the Slave module receives requests and returns processing results; and the intermediate modules handle request routing, address resolution, data caching, or protocol conversion between the Master and Slave modules, ensuring requests are correctly delivered to the target module.

[0003] For integrated circuits that include multiple Master modules and multiple Slave modules, traditional integrated circuit testing methods in related technologies typically involve constructing a one-to-one communication scenario between different Master modules and Slave modules to check whether the transmission and response of requests in each Master-to-Slave module path are correct.

[0004] However, the traditional integrated circuit testing methods described above require constructing a large number of targeted test cases for all possible Master-to-Slave paths, resulting in low testing efficiency. Furthermore, these methods verify the correctness of the path from Master to Slave, lacking checks on the routing and forwarding behavior of intermediate modules. This means that potential routing errors in intermediate modules may go undetected, reducing the completeness and reliability of the integrated circuit testing. Summary of the Invention

[0005] This invention provides an integrated circuit testing method, electronic device, and storage medium to address the shortcomings of low testing efficiency, insufficient test integrity, and inadequate reliability in existing integrated circuit testing technologies, thereby improving the testing efficiency, test integrity, and test reliability of integrated circuit testing.

[0006] This invention provides an integrated circuit testing method, comprising the following steps.

[0007] Based on the system architecture information of the integrated circuit under test, an address translation model function corresponding to the integrated circuit under test is constructed. The integrated circuit under test includes multiple request initiating master modules and multiple request receiving slave modules.

[0008] Based on the input address of each Master module in the integrated circuit under test and the address translation model function corresponding to the integrated circuit under test, the standard address of each intermediate module and the standard address of each Slave module in the integrated circuit under test are generated.

[0009] Based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module, the routing test results of the integrated circuit under test are obtained.

[0010] According to an integrated circuit testing method provided by the present invention, the step of constructing an address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test includes: obtaining an address translation rule set corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test; and constructing an intermediate module address translation model function and a slave module address translation model function corresponding to the integrated circuit under test based on the address translation rule set, respectively, as the address translation model function corresponding to the integrated circuit under test.

[0011] According to an integrated circuit testing method provided by the present invention, the step of obtaining the address translation rule set corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test includes: obtaining each test routing path and the access attribute of each test routing path in the integrated circuit under test based on the system architecture information of the integrated circuit under test, wherein the starting point of the test routing path is the Master module and the ending point of the test routing path is the Slave module; obtaining the address processing logic corresponding to each test routing path based on the access attribute of each test routing path; and formalizing the address processing logic corresponding to each test routing path into bitwise operation rules to obtain the address translation rule set corresponding to the integrated circuit under test.

[0012] According to an integrated circuit testing method provided by the present invention, the step of constructing intermediate module address translation model functions and slave module address translation model functions corresponding to the integrated circuit under test based on the address translation rule set corresponding to the integrated circuit under test includes: performing functional modeling on the address translation rule set corresponding to the integrated circuit under test based on the SystemVerilog language to obtain the intermediate module address translation function and slave module address translation function corresponding to the integrated circuit under test.

[0013] According to an integrated circuit testing method provided by the present invention, the step of obtaining the routing test result of the integrated circuit under test based on the actual output address of each slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each slave module includes: when the actual output address of any slave module in the integrated circuit under test is different from the standard address, determining that the routing path under test ending at any slave module has a routing error and / or that any slave module has a defect, and then determining the identification information of the routing path under test ending at any slave module and the identification information of any slave module as the routing test result of the integrated circuit under test.

[0014] According to an integrated circuit testing method provided by the present invention, the step of obtaining the routing test result of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module includes: determining that any intermediate module has a defect when the hardware design code address of any intermediate module in the integrated circuit under test is different from the standard address, and then determining the identification information of any intermediate module as the routing test result of the integrated circuit under test.

[0015] This invention also provides an integrated circuit testing apparatus, comprising the following modules: a function construction module, used to construct an address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test, wherein the integrated circuit under test includes multiple request initiating master modules and multiple request receiving slave modules; an address generation module, used to generate a standard address for each intermediate module and a standard address for each slave module in the integrated circuit under test based on the input address of each master module and the address translation model function corresponding to the integrated circuit under test; and an address comparison module, used to obtain the routing test results of the integrated circuit under test based on the actual output address of each slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each slave module.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the integrated circuit testing method described above.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the integrated circuit testing method as described above.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the integrated circuit testing method described above.

[0019] The integrated circuit testing method, electronic device, and storage medium provided by this invention construct an address translation model function based on the system architecture information of the integrated circuit under test (ICD). This formalizes the complex inter-module address processing logic into an executable function. Then, based on the input address of the Master module and the aforementioned address translation model function, standard addresses for intermediate and Slave modules are generated. These addresses serve as the data basis for comparing the actual output address of the Slave module with the hardware design code address of the intermediate module. This method can accurately verify the correctness of all possible routing paths in the ICD under test and more accurately and efficiently identify intermediate modules with routing errors. It significantly improves the testing efficiency, coverage, and completeness of IC testing, reduces the computational resources required for IC testing and subsequent maintenance costs, and enhances the reusability of IC testing, thus possessing broad application prospects. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is one of the flowcharts of the integrated circuit testing method provided by the present invention.

[0022] Figure 2 This is the second flowchart of the integrated circuit testing method provided by the present invention.

[0023] Figure 3 This is a schematic diagram of the integrated circuit testing device provided by the present invention.

[0024] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0026] In the description of the invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] In the description of this application, the terms "first," "second," etc., are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the description of this application, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects have an "or" relationship.

[0028] It should be noted that in the SoC architecture of integrated circuits, the integrated circuit can be divided into multiple modules according to different functions, such as: computing cores (e.g., SPC (Streaming Processing Cluster)), image decompression module (Video_decode), image compression module (Video_encode), address translation module (TCU), L2 cache, die-to-die transfer module (D2D), external GPU request interaction module (P2P), system control module (System_ctrl), system memory interface module (HOST_ep), and high bandwidth memory (HBM), etc.

[0029] Of the modules mentioned above, those that actively generate and send requests belong to the Master module, such as: Video_decode, Video_encode, the Master side of the computing core (SPC_M), TCU, the Master side of the L2 cache (L2_M), D2D, P2P, System_ctrl, and HOST_ep. Those used to receive requests and return processing results belong to the Slave module, such as: the Slave side of the computing core (SPC_S), HBM, and the Slave side of the L2 cache (L2_S).

[0030] Therefore, in the SoC architecture of integrated circuits, the Master module and the Slave module interact through on-chip interconnects and intermediate modules, thereby enabling collaborative work among multiple modules.

[0031] For integrated circuits that include multiple Master modules and multiple Slave modules, testing such integrated circuits typically involves traversing and checking all possible paths between the Master and Slave modules.

[0032] Traditional integrated circuit testing methods in related technologies typically involve constructing one-to-one targeted test cases for each possible path between the Master module and the Slave module in the integrated circuit to verify whether the transmission and response of requests in each path from the Master module to the Slave module are correct.

[0033] However, for integrated circuits comprising multiple Master and Slave modules, the combination relationships between Master and Slave modules increase exponentially with the number of Master and Slave modules. Traditional integrated circuit testing methods, to ensure complete test coverage, require building individual test cases for every possible path between Master and Slave modules, incurring significant time costs and severely impacting testing efficiency. Furthermore, building individual test cases for every possible path between Master and Slave modules results in massive amounts of test data and lengthy verification cycles.

[0034] Furthermore, in the process of checking whether the transmission and response of requests in the path from the Master module to the Slave module are correct, traditional integrated circuit testing methods in related technologies usually rely on downloading simulation waveforms and performing manual visual analysis. This not only consumes a lot of manpower and time, but is also prone to omissions and misjudgments, which seriously affects the reliability of integrated circuit testing.

[0035] To improve the automation level of integrated circuit testing, traditional integrated circuit testing methods in related technologies introduce an address checker in the targeted test cases corresponding to each possible path between the Master module and the Slave module, which is used to compare the matching relationship between the request and the response.

[0036] However, since a checker needs to be introduced into the targeted test cases for each possible path between the Master module and the Slave module, the number of checkers will also increase dramatically as the number of Master modules and Slave modules increases. This results in a large amount of computing resources required during testing, as well as problems such as high maintenance costs and poor reusability.

[0037] More importantly, the traditional integrated circuit testing methods described above typically only verify the overall correctness of the request routing from the Master module to the Slave module, lacking checks on the routing and forwarding behavior of intermediate modules. In complex SoC architectures, intermediate modules often perform functions such as routing, address translation, caching, or protocol conversion. If only the overall correctness of the request routing from the Master module to the Slave module is considered, potential functional defects or errors in intermediate modules may go undetected, reducing the completeness and reliability of integrated circuit testing.

[0038] Therefore, traditional integrated circuit testing methods in related technologies have drawbacks such as low testing efficiency, high computational resource requirements, high maintenance costs, poor reusability, and insufficient test completeness and reliability.

[0039] To address this issue, the present invention provides an integrated circuit testing method. This method constructs an address translation model function based on the system architecture information of the integrated circuit under test (SoC), formalizing the complex inter-module address processing logic into an executable function model. This achieves the transformation from design specifications to verification tools, avoiding the inefficiency of manual calculation or writing of numerous targeted test cases in traditional techniques. It also significantly improves the automation level of testing, enabling comprehensive, accurate, and efficient verification of routing and address translation behavior under complex SoC architectures. This overcomes the shortcomings of traditional integrated circuit testing methods in terms of efficiency, coverage, and intermediate module verification, thereby enhancing the completeness, reliability, and automation level of integrated circuit testing.

[0040] The following is combined Figures 1-2 This invention describes the integrated circuit testing method provided by the present invention.

[0041] Figure 1 This is one of the flowcharts illustrating the integrated circuit testing method provided by the present invention, such as... Figure 1As shown, the method includes the following: Step 101: Based on the system architecture information of the integrated circuit under test, construct the address translation model function corresponding to the integrated circuit under test. The integrated circuit under test includes multiple Master modules and multiple Slave modules.

[0042] It should be noted that the execution subject of this embodiment of the invention is an integrated circuit testing device. The aforementioned integrated circuit testing device can be an electronic device such as a computer or server.

[0043] Specifically, the integrated circuit under test (ICD) is the test object of the IC testing method of this invention. The ICD's SoC includes multiple Master modules, multiple Slave modules, and multiple intermediate modules. Based on the IC testing method provided by this invention, the end-to-end routing correctness from each Master module to each Slave module on the ICD can be checked, as well as the routing correctness of the intermediate modules.

[0044] It is understood that the integrated circuit under test in the embodiments of the present invention can be determined based on actual needs. The embodiments of the present invention do not impose specific limitations on the integrated circuit under test.

[0045] It should be noted that the Master module in the IC under test (ICD) is the module in the ICD that can actively generate and send requests. For example, the Master module in the ICD may include, but is not limited to, Video_decode, Video_encode, the Master side of the computing core (SPC_M), TCU, the Master side of the L2 cache (L2_M), D2D, P2P, System_ctrl, and HOST_ep.

[0046] The slave module in the integrated circuit under test (ICD) can be a module used to receive requests and return processing results. For example, the slave module in the ICD can include, but is not limited to, the slave end of the computing core (SPC_S), HBM, and the slave end of the L2 cache (L2_S).

[0047] The intermediate modules in the integrated circuit under test (ICD) can be modules used for routing, address resolution, data caching, or protocol conversion of requests between the Master and Slave modules. For example, intermediate modules in the ICD may include, but are not limited to, interconnect bus modules, crossbars, network-on-chip (NoC) networks, L2 caches, and control modules for arbitration and data forwarding between the Master and Slave modules.

[0048] The system architecture information of the integrated circuit under test (ICD) includes descriptions of the division, configuration, and interconnection relationships of the various modules within the ICD. This system architecture information may include, but is not limited to, the functional roles of the modules, the interconnection relationships between modules, and the overall architecture layout.

[0049] The system architecture information of the integrated circuit under test (ICD) can be obtained by parsing its design documents. These design documents may include, but are not limited to, the ICD's SoC architecture specification, interconnect protocol definition documents, and interface specifications.

[0050] After obtaining the system architecture information of the integrated circuit under test, the address translation model function corresponding to the integrated circuit under test can be constructed based on the system architecture information of the integrated circuit under test through data extraction, numerical calculation, mathematical statistics or deep learning techniques.

[0051] As an optional embodiment, based on the system architecture information of the integrated circuit under test, an address translation model function corresponding to the integrated circuit under test is constructed, including: based on the system architecture information of the integrated circuit under test, obtaining the address translation rule set corresponding to the integrated circuit under test.

[0052] Specifically, the address translation rule set corresponding to the integrated circuit under test in the embodiments of the present invention can be used to describe the unified logical abstraction of address processing and mapping by the intermediate module and the Slave module during the process of the Master module in the integrated circuit under test initiating a request to the Slave module.

[0053] The address translation rule set corresponding to the integrated circuit under test can be a formalized set of rules, whose elements are the correspondence between "access attribute - address processing method". This correspondence can be expressed by bit operations, field concatenation, address masking or address field modification.

[0054] In this embodiment of the invention, based on the system architecture information of the integrated circuit under test, the address translation rule set corresponding to the integrated circuit under test can be obtained through path identification, attribute extraction, rule recording, and formal expression.

[0055] As an optional embodiment, based on the system architecture information of the integrated circuit under test, the address translation rule set corresponding to the integrated circuit under test is obtained, including: based on the system architecture information of the integrated circuit under test, obtaining each route path under test and the access attributes of each route path under test in the integrated circuit under test, wherein the starting point of the route path under test is the Master module and the ending point of the route path under test is the Slave module.

[0056] Specifically, in this embodiment of the invention, a directed graph can be constructed based on the system architecture information of the integrated circuit under test, the modules in the integrated circuit under test can be determined as graph nodes in the above directed graph, and the connections between modules can be determined as directed edges connecting graph nodes in the above directed graph.

[0057] For each Master module in the directed graph above, a depth-first search or a breadth-first search can be performed to traverse all Slave modules and obtain a route path that starts from each Master module and ends at a Slave module, which can then be used as the route path to be tested.

[0058] It should be noted that when any routing path is found that originates from any Master module and terminates at any Slave module, identification information corresponding to the routing path can be generated, and the module order within the routing path can be recorded. For example, for a module in the integrated circuit under test... Starting with the first Master module A route path can be used This indicates the above routing path; correspondingly, The first in the integrated circuit under test Starting with the first Master module The endpoint of the routing path is the first [number] node in the integrated circuit under test. The first Slave module, and sequentially through the first in the integrated circuit under test The first intermediate module and the first One intermediate module; , indicating that the first in the integrated circuit under test Starting with the first Master module The endpoint of the routing path is the first [number] node in the integrated circuit under test. The Slave module, and through the first Slave module in the integrated circuit under test. An intermediate module.

[0059] After obtaining each route path under test in the integrated circuit under test, the access request of each route path can be parsed based on the interface protocol definition, transaction transmission specification or module function description in the system architecture information of the integrated circuit under test, and the access attributes of each route path under test can be determined.

[0060] It should be noted that the access attribute of any route path under test in this embodiment of the invention can be either "copy" or "normal". "Copy" indicates the following processing method: when die0 accesses the second-level cache (L2_S) of die1, the data obtained from the access is cached in the L2_S at a symmetrical position to die0. This method allows a cache copy corresponding to the data accessed by die1 to be established in die0, thereby improving the efficiency of subsequent access to that data. Correspondingly, "normal" indicates another processing method: when die0 accesses the L2_S of die1, the data obtained from the access is not cached in the L2_S of die0. This method avoids invalid data copies occupying cache resources.

[0061] In the case of access attribute "Copy", the address translation rule is: only the 46th bit (bit

[46] ) of the source address needs to be set to zero, and the remaining address bits remain unchanged. Thus, the target address = the source address, and bit

[46] = 0. In the case of access attribute "Normal", the address translation rule is: delete the bit[13:9] field in the source address, and set the lower 8 bits (bit[7:0]) of the source address to zero, thereby obtaining the target address. That is, the target address is formed by concatenating the high-order part of the source address (excluding bit[13:9]) with the low-order bits that have been cleared.

[0062] Based on the access attributes of each route to be tested, obtain the address processing logic corresponding to each route to be tested.

[0063] Specifically, after obtaining the access attributes of each route path to be tested, the intermediate modules in each route path to be tested can be analyzed one by one, and the address processing logic of the intermediate modules in each route path to be tested and the address processing logic of the Slave module at the end of each route path to be tested can be extracted as the address processing logic corresponding to each route path to be tested.

[0064] The processing logic of the intermediate module may include, but is not limited to: address field removal, address field masking, forced assignment of address bits (e.g., fixing a bit to 0 or 1), and address field concatenation. For example, when the access attribute of any route to be tested is Copy, the intermediate module only performs a zeroing operation on bit

[46] , while the other bits remain unchanged; when the access attribute is Normal, the intermediate module performs the operation of deleting bit[13:9] and clearing bit[7:0] to zero.

[0065] The address processing logic corresponding to each route path under test is formalized into bitwise operation rules to obtain the address translation rule set corresponding to the integrated circuit under test.

[0066] Specifically, after obtaining the address processing logic corresponding to each route path to be tested, the address processing logic corresponding to each route path to be tested can be formalized into a unified rule description to support subsequent verification.

[0067] In this embodiment of the invention, bitwise expressions can be used to formalize the address processing logic corresponding to each route path under test into a unified rule description, thereby obtaining the address translation rules corresponding to each route path under test.

[0068] After obtaining the address translation rules corresponding to each route path to be tested, the rule set composed of the address translation rules corresponding to each route path to be tested can be determined as the address translation rule set corresponding to the integrated circuit under test.

[0069] Understandably, the address translation rule set corresponding to the integrated circuit under test includes a set of address translation rules involved in each route path under test in the integrated circuit under test under different access attributes.

[0070] Based on the address translation rule set corresponding to the integrated circuit under test, the intermediate module address translation model function and the Slave module address translation model function corresponding to the integrated circuit under test are constructed respectively, and used as the address translation model function corresponding to the integrated circuit under test.

[0071] Specifically, after obtaining the address translation rule set corresponding to the integrated circuit under test, the intermediate module address translation model function and the Slave module address translation model function corresponding to the integrated circuit under test can be constructed by numerical calculation, respectively, as the address translation model function corresponding to the integrated circuit under test.

[0072] It should be noted that the intermediate module address translation module function in the embodiments of the present invention can be used to obtain the standard (golden) address of each intermediate module based on the input address of each Master module.

[0073] The input address of the Master module can refer to the address used when the Master module initiates the request. The standard address of the intermediate module can be used to reflect the "correct value" to which the address should be converted or mapped when the access request passes through the intermediate module.

[0074] The Slave module address translation model function in this embodiment of the invention can be used to obtain the standard (golden) address of each Slave module based on the input address of each Master module. The standard address of the Slave module reflects the "expected address" that should be matched when the input address of the Master module reaches the Slave module after being processed step-by-step by all intermediate modules.

[0075] This invention constructs a directed graph based on the system architecture information of the integrated circuit under test, automatically identifying all test routes from the Master module to the Slave module. It also extracts access attributes by combining interface protocols and transaction specifications, avoiding the inefficient method of manually enumerating paths and achieving complete path coverage. By extracting the address processing logic of intermediate and Slave modules in each test path and formalizing it into bitwise operation rules, a unified address translation rule set is formed, thereby improving the reusability and maintainability of the rules. Furthermore, based on the address translation rule set, address translation model functions for intermediate and Slave modules are constructed, generating standard addresses for each intermediate and Slave module, providing a more accurate data foundation for subsequent route correctness verification.

[0076] As an optional embodiment, based on the address translation rule set corresponding to the integrated circuit under test, the intermediate module address translation function and the slave module address translation function corresponding to the integrated circuit under test are constructed respectively, including: performing functional modeling of the address translation rule set corresponding to the integrated circuit under test based on the SystemVerilog language to obtain the intermediate module address translation function and the slave module address translation function corresponding to the integrated circuit under test.

[0077] Specifically, after obtaining the address translation rule set corresponding to the integrated circuit under test, the address translation rule set can be parsed to convert the address translation rule corresponding to each route path under test into executable bit manipulation logic. This bit manipulation logic may include, but is not limited to, bit masking, bit clearing, bit field deletion, bit field concatenation, and field reconstruction.

[0078] Based on the System Verilog language, function interfaces are defined for each intermediate module and slave module. The function interface includes input and output parameters: the input parameters are the source address (Addr_src) and access attributes (Attribute); the output parameter is the target address (Addr_dst) after processing according to the module's rules.

[0079] Within the aforementioned function interface, the corresponding rule logic is invoked based on the access attribute, transforming the extracted formal rules into System Verilog bitwise operation statements. For example, when the access attribute is Copy, the function logic can be implemented to clear bit

[46] to zero; when the access attribute is Normal, the function logic can be implemented to delete the bit[13:9] field and clear bit[7:0] to zero.

[0080] The bitwise operation statements of System Verilog corresponding to the intermediate module and the bitwise operation statements of SystemVerilog corresponding to the slave module are encapsulated into two independent System Verilog functions to obtain the address translation model functions of the intermediate module and the slave module.

[0081] This invention establishes intermediate module address translation model functions and slave module address translation model functions that can be directly called in the verification environment through the functional modeling method of System Verilog language. Based on the above model functions, the standard address of each intermediate module and each slave module in the integrated circuit under test can be calculated, replacing the traditional manual calculation method, which can significantly improve the verification efficiency and accuracy.

[0082] Step 102: Based on the input address of each Master module in the integrated circuit under test and the address translation model function corresponding to the integrated circuit under test, generate the standard address of each intermediate module and the standard address of each Slave module in the integrated circuit under test.

[0083] Figure 2 This is the second flowchart illustrating the integrated circuit testing method provided by this invention. For example... Figure 2 As shown in the embodiment of the present invention, the input address of each Master module in the integrated circuit under test can be sampled and obtained.

[0084] After obtaining the input address of each Master module in the integrated circuit under test, the standard address of each intermediate module in the integrated circuit under test can be obtained based on the input address of each Master module and the intermediate module address conversion model function.

[0085] After obtaining the input address of each Master module in the integrated circuit under test, the standard address of each Slave module in the integrated circuit under test can also be obtained based on the input address of each Master module and the address conversion model function of the Slave module in the integrated circuit under test.

[0086] Step 103: Based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module, obtain the routing test results of the integrated circuit under test.

[0087] Specifically, in this embodiment of the invention, a monitor can be used in a test scenario to obtain the actual output address of each slave module in the integrated circuit under test.

[0088] It should be noted that the hardware design code address (RTL input address signal) of the intermediate module refers to the address signal defined in the RTL design code (such as Verilog / VHDL) of the integrated circuit under test, reflecting the input address received by the intermediate module during operation or the address signal output after processing by the module. The hardware design code address of the intermediate module comes directly from the hardware logic of the intermediate module and is the address used for routing requests in the actual design implementation.

[0089] In this embodiment of the invention, a monitor or interface proxy can be used in a test scenario to obtain the actual output address of each intermediate module in the integrated circuit under test.

[0090] As an optional embodiment, the actual output address of the intermediate module includes the address of the hardware design code of the intermediate module.

[0091] After obtaining the actual output address of each Slave module and the hardware design code address of each intermediate module in the integrated circuit under test, the routing test results of the integrated circuit under test can be obtained by comparing the actual output address of each Slave module with the standard address, and by comparing the hardware design code address of each intermediate module with the standard address.

[0092] In this embodiment of the invention, a standard address queue and an output address queue corresponding to each Slave module can be instantiated, and a standard address queue and a hardware design code address queue corresponding to each intermediate module can be instantiated.

[0093] After obtaining the standard address of each intermediate module, the standard address of each intermediate module can be sequentially written into the standard address queue corresponding to that intermediate module. Similarly, after obtaining the standard address of each slave module, the standard address of each slave module can be sequentially written into the standard address queue corresponding to that slave module.

[0094] After obtaining the hardware design code address of each intermediate module, the hardware design code address of each intermediate module can be sequentially written into the corresponding hardware design code address queue. After obtaining the actual output address of each Slave module, the actual output address of each Slave module can be sequentially written into the corresponding output address queue.

[0095] The standard address queue and hardware design code address queue corresponding to each intermediate module are compared in a loop, and the standard address queue and output address queue corresponding to each Slave module are compared in a loop. Based on the comparison results, the routing test results of the integrated circuit under test are obtained.

[0096] It should be noted that the routing test results of the integrated circuit under test in the embodiments of the present invention include at least one of the following: identification information of the routing path under test with routing errors, identification information of the defective Slave module, and identification information of the defective intermediate module.

[0097] As an optional embodiment, the routing test result of the integrated circuit under test is obtained based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module. This includes: if the actual output address of any Slave module in the integrated circuit under test is different from the standard address, determining that the routing path under test ending at any Slave module has a routing error and / or that any Slave module has a defect, and then determining the identification information of the routing path under test ending at any Slave module and the identification information of any Slave module as the routing test result of the integrated circuit under test.

[0098] In this embodiment of the invention, for each Slave module in the integrated circuit under test, a consistency comparison can be performed based on the actual output address of each Slave module and the standard address derived from the modeling function.

[0099] Specifically, the standard address of the Slave module is a theoretically correct value obtained through functional modeling based on the system architecture information of the integrated circuit under test, the path identification results, and the address translation rules under the corresponding access attributes. It can fully describe the "correct value" that the Slave module should return under ideal conditions.

[0100] During testing, if any Slave module's actual output address deviates from the standard address, it indicates a discrepancy in the address obtained by that Slave module after responding to the Master module's request and being routed through intermediate modules. This discrepancy signifies an error in the address resolution, translation, or transmission process of the routing path ending at that Slave module. This could stem from an unexpected implementation of the intermediate module's logic or a flaw in the Slave module's own processing logic.

[0101] Therefore, if the actual output address of any Slave module is found to be inconsistent with the standard address during the comparison process, it can be determined that the route under test with the Slave module as the endpoint has a routing error and / or the Slave module has a defect. The identification information of the route under test and the identification information of the Slave module can be output as the routing test result of the integrated circuit under test.

[0102] In this embodiment of the invention, when the actual output address of any Slave module in the integrated circuit under test differs from the standard address, the identification information of the route path under test ending at any Slave module and the identification information of any Slave module are used as the routing test result of the integrated circuit under test. This not only confirms the existence of errors but also locates the errors to specific path ranges, thereby achieving automated verification and accurate diagnosis of routing correctness in complex on-chip systems.

[0103] As an optional embodiment, the routing test result of the integrated circuit under test is obtained based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module. This includes: determining that any intermediate module has a defect when the hardware design code address of any intermediate module in the integrated circuit under test is different from the standard address, and then determining the identification information of any intermediate module as the routing test result of the integrated circuit under test.

[0104] In this embodiment of the invention, for intermediate modules in the integrated circuit under test, the addresses output by the signal ports of their hardware design code can be compared with the standard addresses derived from the modeling function. If the hardware design code address of any intermediate module is found to be inconsistent with the corresponding standard address, it indicates that there is a deviation in the address processing logic of that intermediate module.

[0105] Specifically, the standard address of the intermediate module is a theoretically correct value obtained through formal expression and functional modeling, based on the system architecture information of the integrated circuit under test, path identification results, and the address translation rule set corresponding to the access attributes of the intermediate module. The standard address of the intermediate module can fully characterize the address result that the intermediate module should output under ideal conditions.

[0106] Therefore, if the hardware design code address of any intermediate module differs from the standard address, it means that the intermediate module did not strictly follow the design specifications or conversion rules during implementation, and its address translation function is defective. This embodiment of the invention uses the identification information of the intermediate module as the routing test result of the integrated circuit under test to clearly locate the source of the defect.

[0107] This invention, by determining the identification information of any intermediate module as the routing test result of the integrated circuit under test when the hardware design code address of any intermediate module in the integrated circuit under test differs from the standard address, can achieve automated detection of the functional correctness of intermediate modules and precise path-level location. This avoids the limitation of difficulty in identifying the source of error when comparing only Slave modules, thereby improving testing efficiency and location accuracy.

[0108] This invention constructs an address translation model function based on the system architecture information of the integrated circuit under test (ICD), formalizing the complex inter-module address processing logic into an executable function. Then, based on the input address of the Master module and the aforementioned address translation model function, it generates standard addresses for intermediate and Slave modules. These addresses serve as the data basis for comparing the actual output address of the Slave module with the hardware design code address of the intermediate module. This accurately verifies the correctness of all possible routing paths in the ICD, more accurately and efficiently identifies defective intermediate modules, significantly improves the testing efficiency, coverage, and completeness of IC testing, reduces the computational resources and subsequent maintenance costs required for IC testing, and enhances the reusability of IC testing, demonstrating broad application prospects.

[0109] Figure 4 This is a schematic diagram of the integrated circuit testing device provided by the present invention. The following is in conjunction with… Figure 4 The integrated circuit testing apparatus provided by this invention will be described below. The integrated circuit testing apparatus described below can be referred to in correspondence with the integrated circuit testing method provided by this invention described above. For example... Figure 4 As shown, the device includes: a function construction module 401, an address generation module 402, and an address comparison module 403.

[0110] The function construction module 401 is used to construct the address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test. The integrated circuit under test includes multiple request initiating end Master modules and multiple request receiving end Slave modules.

[0111] Address generation module 402 is used to generate standard addresses for each intermediate module and each slave module in the integrated circuit under test based on the input address of each Master module in the integrated circuit under test and the address translation model function corresponding to the integrated circuit under test.

[0112] Address comparison module 403 is used to obtain the routing test results of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module.

[0113] Specifically, the function construction module 401, the address generation module 402, and the address comparison module 403 are electrically connected.

[0114] Optionally, the function construction module 401 constructs an address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test, including: obtaining the address translation rule set corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test; and constructing an intermediate module address translation model function and a Slave module address translation model function corresponding to the integrated circuit under test based on the address translation rule set corresponding to the integrated circuit under test, respectively, as the address translation model function corresponding to the integrated circuit under test.

[0115] Optionally, the function construction module 401 obtains the address translation rule set corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test, including: obtaining each route path under test and its access attributes in the integrated circuit under test based on the system architecture information of the integrated circuit under test, wherein the starting point of the route path under test is the Master module and the ending point is the Slave module; obtaining the address processing logic corresponding to each route path under test based on its access attributes; and formalizing the address processing logic corresponding to each route path under test into bitwise operation rules to obtain the address translation rule set corresponding to the integrated circuit under test.

[0116] Optionally, the function construction module 401 constructs intermediate module address translation model functions and slave module address translation model functions corresponding to the integrated circuit under test based on the address translation rule set corresponding to the integrated circuit under test, including: performing functional modeling of the address translation rule set corresponding to the integrated circuit under test based on the System Verilog language to obtain the intermediate module address translation function and slave module address translation function corresponding to the integrated circuit under test.

[0117] Optionally, the address comparison module 403 obtains the routing test results of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module. This includes: if the actual output address of any Slave module in the integrated circuit under test is different from the standard address, determining that the routing path under test ending at any Slave module has a routing error and / or that any Slave module has a defect, and then determining the identification information of the routing path under test ending at any Slave module and the identification information of any Slave module as the routing test results of the integrated circuit under test.

[0118] Optionally, the address comparison module 403 obtains the routing test results of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module. This includes: determining that any intermediate module has a defect when the hardware design code address of any intermediate module in the integrated circuit under test is different from the standard address, and then determining the identification information of any intermediate module as the routing test result of the integrated circuit under test.

[0119] The integrated circuit testing device in this embodiment of the invention constructs an address translation model function based on the system architecture information of the integrated circuit under test (ICD), formalizing the complex inter-module address processing logic into an executable function. Then, based on the input address of the Master module and the aforementioned address translation model function, it generates standard addresses for intermediate and Slave modules. These addresses serve as the data basis for comparing the actual output address of the Slave module with the hardware design code address of the intermediate module. This accurately verifies the correctness of all possible routing paths in the ICD, and more accurately and efficiently identifies intermediate modules with routing errors. It significantly improves the testing efficiency, coverage, and completeness of IC testing, reduces the computational resources and subsequent maintenance costs required for IC testing, and enhances the reusability of IC testing, demonstrating broad application prospects.

[0120] Figure 4 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440. The processor 410, communications interface 420, and memory 430 communicate with each other via the communication bus 440. The processor 410 can call logic instructions in the memory 430 to execute an integrated circuit testing method. This method includes: constructing an address translation model function corresponding to the integrated circuit under test (ICD) based on the system architecture information of the ICD; the ICD includes multiple request initiating master modules and multiple request receiving slave modules; generating standard addresses for each intermediate module and each slave module in the ICD based on the input address of each master module and the address translation model function corresponding to the ICD; and obtaining the routing test results of the ICD based on the actual output address of each slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each slave module.

[0121] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the integrated circuit testing method provided by the above methods. The method includes: constructing an address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test, wherein the integrated circuit under test includes multiple request initiating end Master modules and multiple request receiving end Slave modules; generating a standard address for each intermediate module and a standard address for each Slave module in the integrated circuit under test based on the input address of each Master module and the address translation model function corresponding to the integrated circuit under test; and obtaining the routing test result of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module.

[0123] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the integrated circuit testing method provided by the above methods. The method includes: constructing an address translation model function corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test, wherein the integrated circuit under test includes multiple request initiating master modules and multiple request receiving slave modules; generating a standard address for each intermediate module and a standard address for each slave module in the integrated circuit under test based on the input address of each master module and the address translation model function corresponding to the integrated circuit under test; and obtaining the routing test result of the integrated circuit under test based on the actual output address of each slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each slave module.

[0124] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing integrated circuits, characterized in that, include: Based on the system architecture information of the integrated circuit under test, an address translation model function corresponding to the integrated circuit under test is constructed. The integrated circuit under test includes multiple request initiating end Master modules and multiple request receiving end Slave modules. Based on the input address of each Master module in the integrated circuit under test and the address translation model function corresponding to the integrated circuit under test, the standard address of each intermediate module and the standard address of each Slave module in the integrated circuit under test are generated. Based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module, the routing test results of the integrated circuit under test are obtained.

2. The integrated circuit testing method according to claim 1, characterized in that, The construction of the address translation model function corresponding to the integrated circuit under test (ICD) based on the system architecture information of the ICD includes: Based on the system architecture information of the integrated circuit under test, obtain the address translation rule set corresponding to the integrated circuit under test; Based on the address translation rule set corresponding to the integrated circuit under test, an intermediate module address translation model function and a slave module address translation model function corresponding to the integrated circuit under test are constructed respectively, which serve as the address translation model function corresponding to the integrated circuit under test.

3. The integrated circuit testing method according to claim 2, characterized in that, The step of obtaining the address translation rule set corresponding to the integrated circuit under test based on the system architecture information of the integrated circuit under test includes: Based on the system architecture information of the integrated circuit under test, each route path under test and its access attributes are obtained in the integrated circuit under test. The starting point of the route path under test is the Master module, and the ending point of the route path under test is the Slave module. Based on the access attributes of each route to be tested, obtain the address processing logic corresponding to each route to be tested. The address processing logic corresponding to each route path under test is formalized into bitwise operation rules to obtain the address translation rule set corresponding to the integrated circuit under test.

4. The integrated circuit testing method according to claim 2, characterized in that, The step of constructing intermediate module address translation model functions and slave module address translation model functions corresponding to the integrated circuit under test based on the address translation rule set corresponding to the integrated circuit under test includes: Based on the SystemVerilog language, the address translation rule set corresponding to the integrated circuit under test is modeled functionally to obtain the intermediate module address translation function and the slave module address translation function corresponding to the integrated circuit under test.

5. The integrated circuit testing method according to claim 3, characterized in that, The process of obtaining the routing test results of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module includes: If the actual output address of any Slave module in the integrated circuit under test is different from the standard address, it is determined that the route under test ending at any Slave module has a routing error and / or that any Slave module has a defect. Then, the identification information of the route under test ending at any Slave module and the identification information of any Slave module are determined as the routing test result of the integrated circuit under test.

6. The integrated circuit testing method according to claim 3, characterized in that, The process of obtaining the routing test results of the integrated circuit under test based on the actual output address of each Slave module, the actual output address of each intermediate module, the standard address of each intermediate module, and the standard address of each Slave module includes: If the hardware design code address of any intermediate module in the integrated circuit under test is different from the standard address, it is determined that there is a routing error in the intermediate module, and then the identification information of the intermediate module is determined as the routing test result of the integrated circuit under test.

7. The integrated circuit testing method according to any one of claims 1 to 6, characterized in that, The actual output address of the intermediate module includes the address of the hardware design code of the intermediate module.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the integrated circuit testing method as described in any one of claims 1 to 7.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the integrated circuit testing method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the integrated circuit testing method as described in any one of claims 1 to 7.

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