Quick load configuration refresh imaging system

Abstract

The application relates to the field of imaging systems, in particular to a fast-loading configuration refreshing imaging system, which comprises a refreshing chip, an FPGA, a flash chip, a PROM chip, a power supply circuit and an imaging detector, the flash chip and the PROM chip are connected with the refreshing chip respectively, and the refreshing chip receives configuration data to be updated; the FPGA is connected with the refreshing chip, and the loading configuration process of the FPGA is controlled by the refreshing chip; the imaging detector is connected with the FPGA and is controlled by the FPGA; the power supply sequence provided by the power supply circuit is as follows: (1) power supply to the kernel of the FPGA; (2) power supply to the GTX interface and the auxiliary power supply of the FPGA; (3) power supply to the IO port of the FPGA and the refreshing chip at the same time; (4) power supply to the kernel of the refreshing chip. The power supply sequence guarantees the power-on sequence defined by the FPGA, so that the FPGA is ready when the refreshing chip starts loading configuration, and the influence of external potential access on the loading configuration is avoided.

Description

Technical Field

[0001] This invention belongs to the field of imaging system technology, and in particular relates to a fast-loading configuration refresh imaging system. Background Technology

[0002] In rapid-response satellite imaging systems, the system must be powered on and begin imaging tasks quickly upon receiving an imaging command. When multiple imaging modules of the system are powered on simultaneously, a huge surge current is generated on the power supply bus, which may cause the satellite bus current-limiting protection to malfunction. Repeated power-on may also damage the fuse.

[0003] To improve the reliability and stability of on-orbit applications, the imaging module uses a refresh chip for on-orbit refresh to reduce the probability of single-event upsets. If the refresh chip's built-in core power supply is used, when the external input power is low (especially the latent voltage caused by external potential paths), the loading configuration will be initiated. However, if the external FPGA loading configuration circuitry is not ready, the loading configuration will fail.

[0004] The existing solution is to set up an RC integral reset circuit for the I / O power supply of the refresh chip, ensuring the stability of each power supply before starting the configuration loading process, and ensuring that the RC integral reset circuit level is stable before starting the configuration loading process. However, this method increases the configuration loading time of the refresh chip, and if there is a large latency in the external FPGA configuration loading circuit, the RC integral reset circuit may fail, resulting in configuration loading failure. Summary of the Invention

[0005] In view of this, the present invention aims to provide a fast-loading configuration refresh imaging system to solve the problems of the impact of the through-circuit circuit on the loading configuration and the low loading configuration efficiency.

[0006] To achieve the above objectives, the technical solution created by this invention is implemented as follows: A fast-loading configuration refresh imaging system includes a refresh chip, an FPGA, a Flash chip, a PROM chip, a power supply circuit, and an imaging detector. The Flash chip and PROM chip are connected to the refresh chip, serving as data sources for the FPGA to load configuration data, receiving the configuration data to be updated under the control of the refresh chip. The FPGA is connected to the refresh chip and completes the configuration loading process under its control. The imaging detector is connected to and controlled by the FPGA. The power supply circuit supplies power to the refresh chip, FPGA, Flash chip, PROM chip, and imaging detector. The power supply sequence is as follows: (1) Powering the FPGA core; (2) Power supply to the FPGA's GTX interface and auxiliary power supply; (3) Power is supplied to the IO ports of the FPGA and the IO ports of the refresh chip at the same time; (4) Power the core of the refresh chip.

[0007] Furthermore, the power supply sequence provided by the power supply circuit is executed by using the preceding state signal of the power supply circuit as the subsequent enable signal of the power supply circuit; among them, the core power supply enable of the refresh chip adopts an integral delay power-on circuit composed of resistors and capacitors to ensure that the core power supply of the refresh chip starts after the rising edge of the FPGA internal initialization completion flag signal INIT_B.

[0008] Furthermore, the power supply circuit includes a power supply with controllable power-on rate to power the core of the refresh chip. The power supply with controllable power-on rate includes a power supply chip, a soft-start capacitor, a current-limiting resistor, and a load capacitor. The soft-start capacitor is connected to the power supply chip, and is charged by a constant current source circuit inside the power supply chip to adjust the rise time of the output voltage of the power supply chip, thereby adjusting the output voltage rate of the power supply chip. The current-limiting resistor is connected to the power supply chip and is used to limit the peak current output by the power supply chip. The load capacitor is connected to the core of the refresh chip and is used to filter the power supply chip and store energy for the core of the refresh chip.

[0009] Furthermore, determining the core power supply parameters for refreshing the chip includes the following steps: (i) Based on the final voltage value of the core of the refresh chip. V cint Threshold voltage value V th Delay time from threshold voltage to FPGA configuration loading and startup t th_delay Determine the rise time of the output voltage of the power supply chip in the preliminary design. t r Rising time t r The calculation formula is: ; (ii) Based on the timing margin of the design Determine the rise time of the output voltage of the final designed power supply chip. t r_design Rising time t r_design The calculation formula is: ; (iii) Based on the rise time of the output voltage of the final designed power supply chip tr_design Determine the capacitance value of the soft-start capacitor. C SS capacitance value C SS The calculation formula is: ; in, I SS This refers to the output current value of the soft-start circuit inside the power supply chip. V ref This is the reference voltage value for the soft-start circuit inside the power supply chip; (iv) Verify the average current value of the power supply chip during the power-on phase. I LOAD Average current value I LOAD The calculation formula is as follows: ; in, C LOAD This refers to the load capacitance value of the power supply chip. If the average current value I LOAD Exceeding the maximum output current value of the power supply chip I 0_MAX Then reduce the load capacitance value. C LOAD The size; if the load capacitance value C LOAD If the current value is already the minimum allowable value, then replace the current power supply chip with a power supply chip that outputs a larger current. (v) Verify the resistance value of the current-limiting resistor, and require that the current-limiting coefficient be... The following conditions must be met: .

[0010] Furthermore, both the Flash chip and the PROM chip adopt a daisy-chain structure.

[0011] Furthermore, the FPGA's I / O ports and the refresh chip's I / O ports are connected to the same power supply.

[0012] Compared with the prior art, the present invention can achieve the following beneficial effects: 1. In the power supply sequence, the FPGA is powered on first, and the core of the refresh chip is powered on last. This ensures that the FPGA is ready when the refresh chip starts loading configuration, avoiding the influence of external leakage current on the loading configuration. At the same time, the FPGA's I / O ports and the refresh chip's I / O ports are connected to the same power supply, which powers both the FPGA's I / O ports and the refresh chip's I / O ports simultaneously, avoiding leakage current between the FPGA's I / O ports and the refresh chip's I / O ports due to the difference in power supply sequence.

[0013] 2. The power supply sequence execution method ensures that the subsequent power supply work can only be started after the previous power supply is working normally, ensuring the correct power-on sequence and avoiding abnormally large currents during the loading and configuration process.

[0014] 3. The power supply for refreshing the chip core adopts a power supply with controllable power-up rate, which can ensure that the internal register values ​​read during startup and configuration are correct, and at the same time avoid the circuit from failing to work properly due to excessive load capacitance or unreasonable parameter settings causing current limiting protection. Attached Figure Description

[0015] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the logical structure of a fast-loading configuration refresh imaging system according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the logic structure of a power supply with controllable power-on rate according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the linear relationship between the output voltage and time of the power supply chip according to an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0017] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0018] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The invention will now be described in detail with reference to the figures and embodiments.

[0021] like Figure 1 As shown in the figure, the fast-loading configuration refresh imaging system provided by the present invention includes a refresh chip, an FPGA, a Flash chip, a PROM chip, a power supply circuit, and an imaging detector. The Flash chip and the PROM chip are respectively connected to the refresh chip, serving as data sources for the FPGA to load configuration data, and receiving configuration data to be updated under the control of the refresh chip. The FPGA is connected to the refresh chip, and under the control of the refresh chip, the FPGA completes the configuration loading process. The imaging detector is connected to and controlled by the FPGA. The power supply circuit provides power to the refresh chip, FPGA, Flash chip, PROM chip, and imaging detector.

[0022] Both Flash chips and PROM chips use a daisy-chain topology. When a refresh chip connects to multiple Flash chips, since there is only one set of pins connecting the refresh chip and the Flash chips, a single pin of the refresh chip can be connected to multiple Flash chip pins simultaneously. To avoid signal integrity issues caused by signal reflection during the connection process, Flash chips use a daisy-chain topology. The same logic applies to PROMs using a daisy-chain topology.

[0023] The power supply sequence provided by the power supply circuit is as follows: (1) Powering the FPGA core; (2) Power supply to the FPGA's GTX interface and auxiliary power supply; (3) Power is supplied to the IO ports of the FPGA and the IO ports of the refresh chip at the same time; (4) Power the core of the refresh chip.

[0024] In the above power supply sequence, the FPGA is powered on first, and the core of the refresh chip is powered on last. This ensures the power-on sequence specified by the FPGA, so that the FPGA is ready when the refresh chip starts loading the configuration, avoiding the impact of external leakage on the loading configuration.

[0025] The power supply circuit uses two power supplies: one is a conventional power supply with an uncontrollable power-up rate, and the other is a power supply with a controllable power-up rate. The power supply with an uncontrollable power-up rate supplies power to the FPGA core, GTX interface, IO ports, auxiliary power supply, and IO ports of the refresh chip, while the power supply with a controllable power-up rate supplies power to the core of the refresh chip.

[0026] The FPGA's I / O ports and the refresh chip's I / O ports are connected to the same power supply. This power supply simultaneously powers both the FPGA's I / O ports and the refresh chip's I / O ports, preventing latent power-on between them due to differences in power-on sequence.

[0027] The power supply sequence provided by the power supply circuit is as follows: the preceding status signal of the power supply circuit is used as the subsequent enable signal. For example, the FPGA core's power supply circuit can only start supplying power to the FPGA's GTX interface and auxiliary power supply after it provides a normal operating status indication signal. The FPGA core's power supply circuit uses the input power supply as the enable signal, and starts outputting voltage when the input power supply reaches a set threshold.

[0028] The core power supply enable of the refresh chip uses an integral delay power-on circuit composed of resistors and capacitors to ensure that the core power supply of the refresh chip starts after the rising edge of the FPGA internal initialization completion flag signal INIT_B.

[0029] The above-described power supply sequence ensures that subsequent power supply operations can only begin after the preceding power supply is functioning correctly, guaranteeing a correct power-on sequence and preventing abnormally high current during the configuration process.

[0030] like Figure 2 As shown, the structure of a power supply with controllable power-on rate includes a power supply chip, a soft-start capacitor, a current-limiting resistor, and a load capacitor; wherein, the soft-start capacitor is connected to the power supply chip, and the output voltage rate of the power supply chip is determined by the capacitance value of the soft-start capacitor. The system utilizes a constant current source circuit within the power supply chip to charge the soft-start capacitor, thereby adjusting the rise time of the power supply chip's output voltage and thus regulating its output voltage rate. A current-limiting resistor is connected to the power supply chip to limit its peak output current. When the output current exceeds the peak current, a current-limiting operation halving the output voltage is performed. The load capacitor and the refresh chip's core are both connected to the power supply chip's output. The load capacitor filters the power supply chip and stores energy in the refresh chip's core.

[0031] Determining the core power supply parameters for the refresh chip includes the following steps: (i) Based on the final voltage value of the core of the refresh chip. V cint Threshold voltage value V th Delay time from threshold voltage to FPGA configuration loading and startup t th_delay Determine the rise time of the output voltage of the power supply chip in the preliminary design. t r .

[0032] like Figure 3 As shown, taking the linear increase of output voltage with time as an example, other variation patterns can also be used in specific applications, such as the charging curve of an RC circuit. t th_delay The core voltage of the chip is constantly being refreshed and increased to... V cint ,exist t r The core voltage of the chip is constantly being refreshed and increased to... V cint The allowable rise time of the output voltage of the initially designed power supply chip is... t r for: .

[0033] Based on the final voltage value of the core of the refresh chip.V cint Threshold voltage value V th Delay time from threshold voltage to FPGA configuration loading and startup t th_delay This clarifies the time range for the output voltage rise of the power supply chip, ensuring that the core power supply voltage of the refresh chip has reached a stable state when the configuration is loaded and started, thus providing a basis for the correct reading of registers.

[0034] (ii) Based on the timing margin of the design Determine the rise time of the output voltage of the final designed power supply chip. t r_design Rising time t r_design The calculation formula is: .

[0035] Combined with timing margin Further optimize the rise time of the output voltage of the power supply chip, reserve sufficient voltage stability redundancy, and avoid abnormal loading configuration caused by timing deviation.

[0036] (iii) Based on the rise time of the output voltage of the final designed power supply chip t r_design Determine the capacitance value of the soft-start capacitor. C SS capacitance value C SS The calculation formula is: ; in, I SS This refers to the output current value of the soft-start circuit inside the power supply chip. V ref This is the reference voltage value for the soft-start circuit inside the power supply chip.

[0037] The capacitance value of the soft-start capacitor C SS The rate of rise of the core power supply voltage of the refresh chip is controlled (achieved by charging the constant current source circuit inside the power supply chip) to avoid the surge current generated by the rapid voltage rise, while ensuring a smooth voltage rise process.

[0038] (iv) Verify the average current value of the power supply chip during the power-on phase. I LOAD Average current value I LOAD The calculation formula is as follows: ; in, C LOAD This refers to the load capacitance value of the power supply chip. If the average current value I LOAD Exceeding the maximum output current value of the power supply chip I 0_MAX Then reduce the load capacitance value. C LOAD The size; if the load capacitance value C LOAD If the current value is already the minimum allowable value, then the current power supply chip will be replaced with a power supply chip that outputs a larger current.

[0039] Verify whether the average current value during the power-on phase exceeds the maximum output current value of the power supply chip. By adjusting the load capacitor or replacing the power supply chip, prevent the current limiting protection from being triggered due to overcurrent and ensure continuous and stable power supply.

[0040] (v) Verify the resistance value of the current-limiting resistor, and require that the current-limiting coefficient be... The following conditions must be met: .

[0041] Ensure flow restriction coefficient Meets preset conditions to avoid excessively high peak output current due to abnormal load, prevents the power supply circuit from performing a voltage-halving current-limiting operation, and ensures that the loading and configuration process is not affected by power supply fluctuations.

[0042] By designing the core power supply parameters of the refresh chip as described above, the following technical effects can be achieved: (1) Avoid the influence of leakage current: By using independent power supply and parameter control, ensure that the core power supply of the refresh chip is not affected by external leakage current voltage, and load configuration is only started after the external circuit (such as FPGA) is ready.

[0043] (2) Ensure correct register reading: By precisely controlling the rising edge time, ensure that the kernel power supply is stable when the configuration is loaded and the internal register values ​​are read accurately, thus avoiding configuration errors.

[0044] (3) Surge prevention and current limiting protection: The soft-start capacitor controls the voltage rise rate and reduces surge current; the current and current limiting resistor are checked to avoid the power supply circuit from triggering the protection mechanism due to abnormal current, and to ensure continuous loading configuration.

[0045] (4) Achieve rapid loading configuration: Under the premise of ensuring stability, the power supply preparation time is compressed by optimizing the rise time and timing margin to meet the "rapid response" requirement of the satellite imaging system.

[0046] In a specific example of the present invention, the refresh chip is JFMRS01RH from Shanghai Fudan Microelectronics Co., Ltd.; the FPGA is Xilinx FPGA xq5vfx100t; the Flash chip is JFM29LV641RH from Shanghai Fudan Microelectronics Co., Ltd.; the PROM chip is four Xilinx XQ17V16 chips; the imaging detector is Changguang Chenxin Co., Ltd.; and the power supply circuit is RSS0508HRH and RSW1101HRH from Beijing Shengyu Co., Ltd. The RSS0508HRH is used to power the core of the refresh chip, and the RSW1101HRH is used to power the core of the FPGA, the GTX interface, the IO port, the auxiliary power supply, and the IO port of the refresh chip.

[0047] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0048] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A fast-loading configuration refresh imaging system, characterized in that, The system includes a refresh chip, an FPGA, a Flash chip, a PROM chip, a power supply circuit, and an imaging detector. The Flash chip and PROM chip are connected to the refresh chip, serving as the data source for the FPGA to load configuration data, receiving the configuration data to be updated under the control of the refresh chip. The FPGA is connected to the refresh chip and, under its control, completes the configuration loading process. The imaging detector is connected to and controlled by the FPGA. The power supply circuit supplies power to the refresh chip, FPGA, Flash chip, PROM chip, and imaging detector. The power supply sequence is as follows: (1) Powering the FPGA core; (2) Power supply to the FPGA's GTX interface and auxiliary power supply; (3) Power is supplied to the IO ports of the FPGA and the IO ports of the refresh chip at the same time; (4) Powering the core of the refresh chip; The power supply circuit includes a power supply with controllable power-on rate to power the core of the refresh chip. This power supply includes a power supply chip, a soft-start capacitor, a current-limiting resistor, and a load capacitor. The soft-start capacitor is connected to the power supply chip, and is charged by a constant current source circuit inside the chip to adjust the rise time of the output voltage, thereby regulating the output voltage rate. The current-limiting resistor is also connected to the power supply chip and limits the peak current output by the chip. The load capacitor is connected to both the refresh chip's core and the power supply chip, filtering the power supply chip and storing energy in the refresh chip's core. Determining the core power supply parameters for the refresh chip includes the following steps: (i) Based on the final voltage value of the core of the refresh chip. V cint Threshold voltage value V th Delay time from threshold voltage to FPGA configuration loading and startup t th_delay Determine the rise time of the output voltage of the power supply chip in the preliminary design. t r Rising time t r The calculation formula is: ； (ii) Based on the timing margin of the design Determine the rise time of the output voltage of the final designed power supply chip. t r_design Rising time t r_design The calculation formula is: ； (iii) Based on the rise time of the output voltage of the final designed power supply chip t r_design Determine the capacitance value of the soft-start capacitor. C SS capacitance value C SS The calculation formula is: ； in, I SS This refers to the output current value of the soft-start circuit inside the power supply chip. V ref This is the reference voltage value for the soft-start circuit inside the power supply chip; (iv) Verify the average current value of the power supply chip during the power-on phase. I LOAD Average current value I LOAD The calculation formula is as follows: ； in, C LOAD This refers to the load capacitance value of the power supply chip. If the average current value I LOAD Exceeding the maximum output current value of the power supply chip I 0_MAX Then reduce the load capacitance value. C LOAD The size; if the load capacitance value C LOAD If the current value is already the minimum allowable value, then replace the current power supply chip with a power supply chip that outputs a larger current. (v) Verify the resistance value of the current-limiting resistor, and require that the current-limiting coefficient be... The following conditions must be met: 。 2. The fast-loading configuration refresh imaging system according to claim 1, characterized in that, The power supply sequence provided by the power supply circuit is executed by using the preceding state signal of the power supply circuit as the subsequent enable signal of the power supply circuit; among them, the core power supply enable of the refresh chip adopts an integral delay power-on circuit composed of resistors and capacitors to ensure that the core power supply of the refresh chip starts after the rising edge of the FPGA internal initialization completion flag signal INIT_B.

3. The fast-loading configuration refresh imaging system according to claim 1, characterized in that, Both Flash chips and PROM chips use a daisy-chain structure.

4. The fast-loading configuration refresh imaging system according to claim 1, characterized in that, The FPGA's I / O ports and the refresh chip's I / O ports are connected to the same power supply.

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