Frequency interleaving system and electronic device

Abstract

This invention provides a frequency interleaving system and electronic device, comprising: a sampling circuit that samples an input signal based on N sampling modules; the input signal is a continuous-time analog signal, and the output signal of the sampling circuit is a discrete-time analog signal; a frequency interleaver that decomposes the broadband signal output by the sampling circuit into N narrowband signals, each narrowband signal having a spectral bandwidth equal to a sub-band of the input signal's spectral bandwidth; and a signal processing circuit that reconstructs the output signal of the frequency interleaver based on a signal reconstruction unit; where N is a natural number greater than or equal to 2. The frequency interleaving system and electronic device of this invention directly samples the high-frequency analog input signal without mixing the high-frequency input signal to an intermediate frequency or baseband, and, combined with the frequency interleaver, achieves robustness against inter-channel errors; the system has low overhead, is simple to implement, and does not introduce frequency response mismatch.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and in particular to a frequency interleaving system and electronic device. Background Technology

[0002] With the development of science and technology and the ever-increasing demands for information transmission speed, modern electronic devices need to be able to efficiently and accurately process wider bandwidth signals (such as the current cutting-edge communication systems that require data rates of hundreds of Gb / s). When electronic devices receive high-speed analog signals from the outside world, single-channel structures often cannot meet the requirements for processing such high-speed signals. In this case, multi-channel parallel operation is a more realistic solution. Multi-channel systems decompose the information of the input high-frequency analog signal into multiple channels, each channel independently processing a portion of the original signal, and finally combining the information to obtain the processed original high-frequency signal. The most popular multi-channel system today is the time-interleaved system, which uses multiple channels to sequentially process time-domain sampling points, thereby proportionally reducing the operating speed of each channel. However, the biggest problem in time-interleaved systems is channel mismatch, especially the nonlinear timing error (i.e., the skew of sampling clocks and bandwidth mismatch between channels during sampling), which significantly reduces the performance of time-interleaved systems and becomes more severe as the frequency of the analog input signals to be processed increases. Mitigating timing errors generally requires the use of complex calibration techniques, which involve complex algorithms and large scale, thus consuming a lot of hardware resources.

[0003] The working principle of a frequency interleaving system based on continuous-time signal processing is as follows: The original broadband analog signal is divided into multiple narrowband signals using a front-end combination of an analog mixer and a filter. These signals are then downsampled to baseband and then sampled again. Since each channel samples a narrowband, low-speed signal, the impact of timing errors between channels is mitigated. However, because a frequency interleaving system based on continuous-time signal processing requires separate analog mixers and filters for each channel, this leads to increased system overhead and complexity. Furthermore, mismatches between analog mixers and filters can cause frequency response mismatches between channels, which are more serious problems and thus affect the system's performance.

[0004] Therefore, how to propose a hybrid signal processing system that can effectively suppress inter-channel mismatch without increasing system overhead and complexity or introducing frequency response mismatch has become one of the urgent problems to be solved by engineers in this field.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a frequency interleaving system and electronic device to solve the problems of high system overhead, high system implementation complexity, and introduction of other mismatches caused by overcoming the inter-channel mismatch problem in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a frequency interleaving system, the frequency interleaving system comprising at least:

[0008] Sampling circuit, frequency interleaver, and signal processing circuit;

[0009] The sampling circuit samples the input signal based on N sampling modules; wherein the input signal is a continuous-time analog signal, the output signal of the sampling circuit is a discrete-time analog signal, and N is a natural number greater than or equal to 2;

[0010] The frequency interleaver is connected to the output of the sampling circuit and decomposes the broadband signal output by the sampling circuit into N narrowband signals. The spectral bandwidth of each narrowband signal is a sub-band of the spectral bandwidth of the input signal.

[0011] The signal processing circuit is connected to the output of the frequency interleaver and performs signal reconstruction on the output signal of the frequency interleaver based on the signal reconstruction unit.

[0012] Optionally, the output signal of the frequency interleaver satisfies:

[0013]

[0014] Where Y[i] is the output signal of the i-th channel in the frequency interleaver; X i,j w is the sampled signal of the j-th sampling point in the i-th channel; j,i Let be the tap weight corresponding to the j-th sampled signal in the i-th channel; i = 1, 2, ..., N; j = 1, 2, ..., M; N is the number of channels, and M is the number of sampling points in a channel.

[0015] Alternatively, the frequency interleaver includes N channels, each channel including a multiplication unit and an addition unit.

[0016] Alternatively, when M is greater than N, WM×N The ranks are full. When the row is full rank, the output signal of the signal processing circuit satisfies:

[0017]

[0018] When N is greater than M Full rank, W M×N When the row is full rank, the output signal of the signal processing circuit satisfies:

[0019]

[0020] When M equals N

[0021] Wherein, S′ is the output signal of the signal processing circuit; Y is the output matrix of the frequency interleaver.

[0022] Alternatively, the input signal is a linear combination of sinusoidal signals.

[0023] Alternatively, when the input signal with gain and timing error is represented as hour,

[0024] If M is greater than N, then the energy error of the output signal of the signal processing circuit satisfies:

[0025]

[0026] If N is greater than M, then the energy error of the output signal of the signal processing circuit satisfies:

[0027]

[0028] If N equals M, then the energy error of the output signal of the signal processing circuit satisfies:

[0029]

[0030] in, fin is the signal input frequency; e FI The energy error is defined as diag(G); is the energy error expressed in terms of G. i G is a diagonal matrix with diagonal elements. i S is the gain factor of the i-th channel; S is the ideal input signal of the frequency interleaver. For A diagonal matrix with diagonal elements. Let C be the timing deviation of the i-th channel, and C be the cosine component of the input signal.

[0031] Alternatively, the signal reconstruction unit is based on a matrix. or matrix W M×N The inverse matrix implementation.

[0032] Alternatively, the signal processing circuit further includes a preprocessing unit connected to the input terminal of the signal reconstruction unit, which performs preset processing on the output signal of the frequency interleaver before sending it to the signal reconstruction unit.

[0033] Alternatively, the preprocessing unit may be one or a combination of at least two of a converter, an amplifier, and a filter.

[0034] To achieve the above and other related objectives, the present invention also provides an electronic device, which includes at least the frequency interleaving system described above.

[0035] As described above, the frequency interleaving system and electronic device of the present invention have the following beneficial effects:

[0036] 1. The frequency interleaving system and electronic device of the present invention directly face the broadband input signal during sampling. It cannot directly achieve robustness to timing errors at the sampling circuit. However, in the process of frequency interleaving calculation and reconstruction of discrete-time analog signals through frequency interleaving and subsequent signal processing, the sampling data of all channels are fused through linear transformation. This allows the reconstruction algorithm to average or partially cancel the errors between channels, thereby reducing the energy of timing errors and realizing the robustness of the system to timing deviations.

[0037] 2. The frequency interleaving system and electronic equipment of the present invention can relax the matching requirements between channels. Attached Figure Description

[0038] Figure 1 The diagram shown is a schematic representation of the frequency interleaving system of the present invention.

[0039] Figure 2 The diagram shown is a structural schematic of the sampling unit of the present invention.

[0040] Figure 3 The diagram shows the frequency response of each channel of the frequency interleaver of the present invention.

[0041] Figure 4 The diagram shown is a schematic representation of the frequency interleaver of this invention.

[0042] Figure 5 The diagram shown illustrates a structure of the multiplication and addition units of this invention.

[0043] Figure 6 The diagram shown is another structural schematic of the multiplication and addition units of the present invention.

[0044] Figure 7 The diagram shown is a schematic representation of the signal processing circuit of the present invention.

[0045] Figure 8 This diagram illustrates a comparison of the signal-to-noise ratio (SNR) between the frequency interleaving system (dashed line) of this invention and the existing time interleaving system (solid line).

[0046] Component designation explanation

[0047] 1. Frequency Interleaving System

[0048] 11 Sampling Circuit

[0049] 12 Frequency Interleaver

[0050] 13 Signal Processing Circuit

[0051] 131 Signal Reconstruction Unit

[0052] 132 Preprocessing Units Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] like Figure 1 The present invention provides a frequency interleaving system 1, the frequency interleaving system 1 comprising:

[0056] Sampling circuit 11, frequency interleaver 12 and signal processing circuit 13.

[0057] like Figure 1 As shown, the sampling circuit 11 samples the input signal x(t) based on N sampling modules; where the input signal x(t) is a continuous-time analog signal, the output signal of the sampling circuit 11 is a discrete-time analog signal, and N is a natural number greater than or equal to 2.

[0058] Specifically, each sampling module samples the input signal x(t) sequentially with a uniform phase difference within the sampling period, and each sampling module completes one sampling within one sampling period; each sampling module includes M sampling points, that is, each sampling module completes M samplings; thus, N×M discrete sampled signals can be obtained, where the sampled signal of the j-th sampling point in the i-th channel is denoted as X. i,j , i = 1, 2…N; j = 1, 2…M, where N is the number of channels and M is the number of sampling points in a channel.

[0059] In this embodiment, a typical sinusoidal input signal (any signal can be decomposed into a superposition of a series of sinusoidal signals) is taken as an example, that is, the input signal is a linear combination of sinusoidal signals; the sinusoidal input signal is affected by timing errors in the channel, thus exhibiting deviations in gain and timing: G×sin(2π×f in ×(t-Δt)), where fin is the signal input frequency, G is the gain factor of the channel, and Δt is the timing deviation caused by clock skew in the channel; assuming The error model formula is then expanded to obtain:

[0060]

[0061] Generally speaking, for relatively small clock deviations Formula (1) can be approximated as:

[0062]

[0063] In formula (2), This represents the ideal signal, while the rest represents the deviation introduced by non-ideal factors within the channel.

[0064] Therefore, the input signal x(t) of this invention has different mismatch factors in different channels, satisfying:

[0065]

[0066]

[0067] Among them, X N×M For system sampling models containing inter-channel mismatch, G is the sampled signal of the j-th sampling point of its i-th channel. i Let be the gain factor for the i-th channel. Let be the timing deviation of the i-th channel.

[0068] Specifically, in this embodiment, a sampling module is implemented based on at least one sampling unit. As an example, the sampling unit uses a switched capacitor. Figure 2As shown, each sampling unit includes a first capacitor C1 and a first switch K1; wherein, the lower plate of the first capacitor C1 is grounded, and the upper plate is connected to the input signal x(t) through the first switch K1; the first switch K1 is controlled by a sampling clock (not shown in the figure); the upper plate of the first capacitor C1 outputs the sampled discrete-time analog signal. In practical use, any circuit structure that can sample a continuous-time analog signal to obtain a discrete-time analog signal is applicable to the sampling module of the present invention, and is not limited to this embodiment.

[0069] It should be noted that the sampling signals output by each sampling module have the same bandwidth as the input signal x(t).

[0070] like Figure 1 As shown, the frequency interleaver 12 is connected to the output of the sampling circuit 11, decomposing the broadband signal output by the sampling circuit 11 into N narrowband signals. The spectral bandwidth of each narrowband signal is a sub-band of the spectral bandwidth of the input signal x(t). Typically, each narrowband signal has a different center frequency.

[0071] Specifically, the frequency interleaver 12 is a discrete-time system that processes analog sampled signals with continuous amplitude but discrete time. The narrowband signal output from each sampled channel after passing through the frequency interleaver 12 has a spectral bandwidth that is only a sub-band of the spectral bandwidth of the input signal x(t). In this example, the frequency response of each channel in the frequency interleaver 12 is represented by bandpass filters with different center frequencies, thereby achieving frequency interleaving. Figure 3 As shown, each sub-band is sequentially distributed across the spectral bandwidth of the input signal x(t), and the coefficients H1, H2…H of each bandpass filter are... N Let w be a matrix formed by the corresponding tap weights. j,i The tap weights corresponding to the j-th sampled signal in the i-th channel are used to weight the coefficients of the bandpass filter and the corresponding sampled signal, respectively, to obtain the desired frequency response. In this invention, the output signal of the frequency interleaver 12 satisfies:

[0072]

[0073] Where Y[i] is the output signal of the i-th channel in the frequency interleaver 12.

[0074] Specifically, such as Figure 4 As shown, in this embodiment, the frequency interleaver 12 includes N channels, each channel including a multiplication unit and an addition unit, used to implement the mathematical model of formula (4). It should be noted that... Figure 4The structure shown is a schematic diagram, not an actual circuit diagram. The multiplication and addition units can be constructed using various methods, including but not limited to implementations in the charge domain and current domain, which will not be elaborated upon here. As an example of a charge domain implementation, such as... Figure 5 As shown, the multiplication and addition units include a second capacitor C2, a third capacitor C3, and a second switch K2. The lower plates of the second capacitor C2 and the third capacitor C3 are grounded, and their upper plates are connected via the second switch K2. The charge on the second capacitor C2 is Q2 = C2 × V1, and the charge on the third capacitor C3 is Q3 = C3 × V2. The amount of charge stored in the capacitors can be changed by adjusting their sizes. The sizes of the capacitors (C2, C3) are the multiplication factors of the signals (V1, V2). For example, the corresponding tap weights can be obtained by adjusting the capacitor sizes. Finally, addition is achieved in the charge domain through charge sharing. When the second switch K2 is turned on, since the total charge remains constant, the voltage on the upper plate of the capacitors is ultimately established as follows:

[0075]

[0076] The frequency interleaver 12 of this invention can be implemented using multiple multiplication and addition units, which will not be described in detail here. As an example of a current-domain implementation, such as... Figure 6 As shown, the multiplication and addition units include a first transconductance amplifier gm1 and a second transconductance amplifier gm2. The first transconductance amplifier gm1 and the second transconductance amplifier gm2 receive signals V1 and V2 respectively, and their outputs are connected together. The output current of the first transconductance amplifier gm1 is I1 = gm1 × V1, and the output current of the second transconductance amplifier gm2 is I2 = gm2 × V2. The transconductances of the transconductance amplifiers (gm1, gm2) are the multiplication factors of the signals (V1, V2). According to Kirchhoff's current law (KCL), addition in the current domain only requires connecting the current traces together, and the output current satisfies:

[0077] I o =I1+I2=g m1 V1+g m2 V2 (7)

[0078] Similarly, the frequency interleaver 12 of the present invention can be implemented by multiple multiplication and addition units, which will not be described in detail here.

[0079] like Figure 1 As shown, the signal processing circuit 13 is connected to the output terminal of the frequency interleaver 12, and performs signal reconstruction on the output signal of the frequency interleaver based on the signal reconstruction unit 131.

[0080] Specifically, signal reconstruction is the inverse transformation of the output signal of frequency interleaver 12. In this embodiment, it is assumed that the ideal input signal S (i.e., X) of frequency interleaver 12 is... N×M The ideal signal satisfies: The cosine component C satisfies: but

[0081]

[0082] Among them, w i =[w 1,i w 2,i …w M,i ] T These are the filter coefficients for the i-th channel; ideally (without error), that is, G i =1, Then matrix X N×M Each line is S T The ideal output at this point is The ideal reconstructed signal is

[0083] When M is greater than N, where yes The pseudo-inverse (right inverse matrix) of the frequency interleaver 12 is obtained by applying the same inverse transform to the actual output signal Y of the frequency interleaver 12.

[0084]

[0085] because (W M×N The ranks are full. (If the row is full rank), then the output signal (reconstructed signal) of the signal processing circuit 13 can be obtained to satisfy:

[0086]

[0087] When N is greater than M, where yes The pseudo-inverse (left inverse matrix) is obtained, therefore, the same inverse transformation (i.e., formula (9)) is applied to the actual output signal Y, since Full rank, W M×N Since the row is full rank, the reconstructed signal satisfies:

[0088]

[0089] When M equals N Then, the reconstructed signal can be represented by formula (10) or formula (11). In this case, formula (10) and formula (11) are the same.

[0090] Where S′ is the output signal of signal processing circuit 13; Y is the output matrix of frequency interleaver 12.

[0091] As another implementation of the present invention, such as Figure 7 As shown, the signal processing circuit 13 also includes a preprocessing unit 132, which is connected to the input terminal of the signal reconstruction unit 131. The preprocessing unit 132 preprocesses the output signal of the frequency interleaver 12 and then sends it to the signal reconstruction unit 131 for signal reconstruction. The preprocessing unit 132 can be configured with corresponding functions according to actual needs, including but not limited to converters, amplifiers, and filters, which will not be described in detail here.

[0092] Specifically, since the signal reconstruction matrix in signal reconstruction unit 131 is the inverse of the tap weight matrix in frequency interleaver 12, signal reconstruction unit 131 can also be implemented based on multipliers and adders. If the signal processed by preprocessing unit 132 is still an analog signal, it can be implemented based on... Figure 5 or Figure 6 Multiplication and addition operations can be implemented in various ways, but are not limited to these two methods. If the signal processed by the preprocessing unit 132 is a digital signal, multiplication and addition operations can be implemented based on digital multiplication and digital addition circuits, which will not be elaborated here.

[0093] To demonstrate the advantage of the frequency interleaving system of this invention in terms of small timing error in the reconstructed signal, a comparison is made between the frequency interleaving system and the time interleaving system. Assume the channel gain deviation vector satisfies: G = [G1 G2…G…]. N ] T The timing deviation vector satisfies: Furthermore, the error variables are independent of each other.

[0094] Therefore, in a time-interleaved system, the sampled signal S containing timing errors... TI ,satisfy:

[0095] S TI =[X 1,1 X 2,2 … X N,N X 1,N+1 X 2,N+2 …] T The length is M(12).

[0096] Right now Where i[t] = ((t-1)modN)+1, t = 1, 2…M. The error signal of the time-interleaved system is:

[0097]

[0098] However, for the frequency interleaving system of the present invention, matrix G and matrix Combining formula (8), we get:

[0099]

[0100] Where, diag(G) is a function of G. i G is a diagonal matrix with diagonal elements. i Let be the gain factor for the i-th channel; For A diagonal matrix with diagonal elements. Let be the timing deviation of the i-th channel.

[0101] When M is greater than N, substituting formula (14) into formula (10) yields the reconstructed signal error:

[0102]

[0103] When N is greater than M, substituting formula (14) into formula (11) yields the reconstructed signal error:

[0104]

[0105] When M equals N, at this time The reconstructed signal error can be expressed as formula (17).

[0106]

[0107] The energy error of the reconstructed signal S′ in the frequency interleaving system of the present invention is less than or equal to the energy error of the time interleaving system S′. TI The error energy is reduced because the frequency interleaving structure proposed in this invention fuses the sampled data of all channels through linear transformation, allowing the reconstruction algorithm to average or partially cancel the errors between channels, which can effectively suppress the mismatch between channels.

[0108] In one example, assume the filter coefficient matrix W M×N Given the Fourier transform algorithm and M = N, then the reconstructed matrix... Then use the inverse Fourier transform algorithm, such as Figure 8 As shown, under the same timing deviation, the signal-to-noise ratio of the reconstructed signal after frequency interleaving is represented by the dashed line in the figure, while the signal-to-noise ratio of the sampled signal in the time interleaving system is represented by the solid line in the figure. It can be seen that, compared with the time interleaving system, the frequency interleaving system of the present invention has higher robustness to timing deviation. This characteristic has been verified by behavioral-level simulations of timing skew and bandwidth mismatch.

[0109] The present invention also provides an electronic device, which includes at least the frequency interleaving system of the present invention. This electronic device can be any communication system or analog signal processing system, including but not limited to OFDM communication receivers, Fourier transform spectrometers, and FMCW radars, which will not be elaborated upon here.

[0110] In summary, this invention provides a frequency interleaving system and electronic device, comprising: a sampling circuit, a frequency interleaver, and a signal processing circuit; the sampling circuit samples the input signal based on N sampling modules; wherein the input signal is a continuous-time analog signal, the output signal of the sampling circuit is a discrete-time analog signal, and N is a natural number greater than or equal to 2; the frequency interleaver is connected to the output of the sampling circuit, decomposing the broadband signal output by the sampling circuit into N narrowband signals, the spectral bandwidth of each narrowband signal being a sub-band of the spectral bandwidth of the input signal; the signal processing circuit is connected to the output of the frequency interleaver, and reconstructs the output signal of the frequency interleaver based on a signal reconstruction unit. The frequency interleaving system and electronic device of this invention directly samples the high-frequency analog input signal without mixing the high-frequency input signal to the intermediate frequency or baseband, and achieves robustness against inter-channel errors by combining the frequency interleaver; the system has low overhead, is simple, and does not introduce frequency response mismatch. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A frequency interleaving system, characterized in that, The frequency interleaving system includes at least: Sampling circuit, frequency interleaver, and signal processing circuit; The sampling circuit samples the input signal based on N sampling modules; wherein the input signal is a continuous-time analog signal, and the output signal of the sampling circuit is a discrete-time analog signal; The frequency interleaver is connected to the output of the sampling circuit and decomposes the broadband signal output by the sampling circuit into N narrowband signals. The spectral bandwidth of each narrowband signal is a sub-band of the spectral bandwidth of the input signal. The signal processing circuit is connected to the output of the frequency interleaver and performs signal reconstruction on the output signal of the frequency interleaver based on the signal reconstruction unit. The output signal of the frequency interleaver satisfies: ； ； Where N is a natural number greater than or equal to 2; The output signal of the i-th channel in the frequency interleaver; This refers to the sampled signal at the j-th sampling point in the i-th channel; Let be the tap weight corresponding to the j-th sampled signal in the i-th channel; Let N be the tap weight matrix for N×M sampled signals; i=1,2…N; j=1,2…M; N is the number of channels, and M is the number of sampling points in one channel.

2. The frequency interleaving system according to claim 1, characterized in that: The frequency interleaver includes N channels, and each channel includes a multiplication unit and an addition unit.

3. The frequency interleaving system according to any one of claims 1-2, characterized in that: When M is greater than N , The ranks are full. When the row is full rank, the output signal of the signal processing circuit satisfies: ； When N is greater than M , The ranks are full. When the row is full rank, the output signal of the signal processing circuit satisfies: ； in, This is the output signal of the signal processing circuit; This is the output matrix of the frequency interleaver; When M equals N .

4. The frequency interleaving system according to claim 3, characterized in that: The input signal is a linear combination of sinusoidal signals.

5. The frequency interleaving system according to claim 4, characterized in that: When the input signal with gain and timing error is represented as hour, If M is greater than N, then the energy error of the output signal of the signal processing circuit satisfies: ； If N is greater than M, then the energy error of the output signal of the signal processing circuit satisfies: ； If N equals M, then the energy error of the output signal of the signal processing circuit satisfies: ； Where G is the gain factor for the corresponding channel; , fin is the signal input frequency; The energy error; For A diagonal matrix with diagonal elements. S is the gain factor of the i-th channel; S is the ideal input signal of the frequency interleaver. For A diagonal matrix with diagonal elements. Let C be the timing deviation of the i-th channel, and C be the cosine component of the input signal.

6. The frequency interleaving system according to claim 3, characterized in that: The signal reconstruction unit is based on a matrix. or matrix The inverse matrix implementation.

7. The frequency interleaving system according to claim 6, characterized in that: The signal processing circuit further includes a preprocessing unit connected to the input terminal of the signal reconstruction unit, which preprocesses the output signal of the frequency interleaver before sending it to the signal reconstruction unit.

8. The frequency interleaving system according to claim 7, characterized in that: The preprocessing unit is one or a combination of at least two of the following: a converter, an amplifier, and a filter.

9. An electronic device, characterized in that, The electronic device includes at least the frequency interleaving system as described in any one of claims 1-8.

Images