A Low-Rank DCT Compressed Sensing Method Based on FPGA

Abstract

This invention discloses a low-rank DCT compressed sensing method implemented based on FPGA, belonging to the field of image data processing technology. The specific steps of the compressed sensing method are as follows: the input signal is divided into blocks, and the block granularity is dynamically adjusted based on the calculation result of the signal's local gradient entropy. When the gradient entropy is higher than a set threshold, fine-grained block segmentation is used; when it is lower than the threshold, coarse-grained block segmentation is used. The block granularity is dynamically adjusted within a preset range. Discrete cosine transform is performed on the block-processed signal, and the spectral entropy of the transformed coefficients is calculated. The number of low-frequency coefficients retained is dynamically adjusted according to the magnitude of the spectral entropy. This dynamic block segmentation strategy based on gradient entropy allows the compressed sensing method to automatically adjust the block granularity according to the local features of the signal, improving the compression ratio of complex texture regions and smooth regions. The block boundaries are dynamically determined by gradient entropy, ensuring more accurate pixel assignment in edge regions, reducing block artifacts, and preserving complete structural information for subsequent reconstruction.

Description

Technical Field

[0001] This invention relates to the field of image data processing technology, specifically to a low-rank DCT compressed sensing method implemented based on FPGA. Background Technology

[0002] With the rapid development of information technology, the demand for information is increasing, especially in scenarios such as image reconstruction, medical scanning, and wireless channel estimation. Compressed sensing is a new sampling and reconstruction technology based on signal sparsity. It uses optimized algorithms to reconstruct sparse or compressible signals with high probability by measuring values ​​far below the requirements of the Nyquist sampling theorem. Its core breakthrough lies in completing signal sampling and compression simultaneously, which greatly reduces data acquisition costs and is widely used in fields such as medical imaging and communication engineering.

[0003] Traditional compressed sensing methods are characterized by overall compression, which involves transforming and projecting the entire signal or image at once. This method can achieve good results when the signal size is small. However, in large-scale signal or image processing implemented in FPGAs, the complete signal participates in high-dimensional matrix multiplication, requiring the simultaneous storage of sparse basis, measurement matrix, and intermediate variables. This results in high hardware resource consumption, and large-scale sparse transformation and measurement operations are difficult to meet the requirements in real-time processing scenarios. When performing sparse reconstruction after overall signal compression, it is necessary to solve a large-scale sparse optimization problem, which leads to a significant increase in signal recovery time. Therefore, current compressed sensing methods are not very effective in meeting the current application requirements. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a low-rank DCT compressed sensing method based on FPGA implementation, which solves the problems mentioned in the background technology.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a low-rank DCT compressed sensing method based on FPGA, wherein the specific steps of the compressed sensing method are as follows: S1. The input signal is divided into blocks. The block granularity is dynamically adjusted based on the calculation result of the local gradient entropy of the signal. When the gradient entropy is higher than the set threshold, fine-grained block is used, and when it is lower than the threshold, coarse-grained block is used. The block granularity is dynamically adjusted within the preset range.

[0006] S2. Perform discrete cosine transform on the segmented signal, calculate the spectral entropy of the transformed coefficients, and dynamically adjust the number of low-frequency coefficients retained according to the magnitude of the spectral entropy to achieve a low-rank sparse representation of the signal.

[0007] S3. The Bernoulli matrix is ​​used to project and compress the sparsely represented signal. During the compression process, the low-frequency coefficients in the first half are calculated with higher precision at fixed points, while the coefficients in the second half are calculated with lower precision at fixed points. Error compensation is introduced for the low-precision calculation.

[0008] S4. The compressed signal is reconstructed on the host computer. During the reconstruction process, the coarse search layer is used to iterate with a jump step size, and then the fine search layer is used to iterate with a standard step size to complete the reconstruction of the original signal and smooth the block boundaries.

[0009] Preferably, the dynamic adjustment of the block granularity based on the calculation result of the signal local gradient entropy specifically includes the following calculation formula: The gradient magnitude of pixels within a 3×3 window is calculated using the Sobel operator. ;

[0010] in, This represents the total number of pixels within the window. For gradient entropy, Gradient magnitude vector of Norm, i.e. ; when When using 8×8 blocks, when The intermediate value is divided into 32×32 blocks, and the middle value is divided into 16×16 blocks. The block size can be adjusted from 8×8 to 32×32.

[0011] Preferably, the dynamic adjustment of the number of low-frequency coefficients retained by the magnitude of the spectral entropy is specifically achieved by calculating the spectral entropy of the coefficients after the DCT transform, and the specific calculation formula is as follows:

[0012] in, For the first DCT coefficients, This represents the total number of coefficients after the DCT transformation. For spectral entropy, Gradient magnitude vector of Norm, i.e. ; when When the retention factor K is set to 24 or 32, Set the hour value to 8 and the median value to 16. The LSTM model is trained using the previous DCT coefficients, and the number of neurons in the hidden layer is... Differential encoding is performed on the first K coefficients of the current block to control the prediction error within 5%.

[0013] Preferably, the LSTM model performs differential encoding of the DCT coefficients as follows: The first K DCT coefficients of adjacent blocks are used as the input sequence of LSTM. The weight matrix is ​​determined through offline training and then stored in FPGAROM. The model parameters are updated once every 16 blocks.

[0014] Preferably, the specific error compensation item for the low-precision calculation error compensation is set as follows:

[0015] in, This is the error compensation value for an 8-bit fixed-point number. This is the compensation coefficient, with a value ranging from 0.1 to 0.3. The maximum value of a 16-bit fixed-point number. It is the maximum value of an 8-bit fixed-point number.

[0016] Preferably, the Bernoulli matrix further includes a dynamic refresh mechanism during projection compression, the dynamic refresh mechanism specifically being: Every 1024 samples, a new Bernoulli matrix seed is generated through the FPGA's internal PRNG module. The matrix elements are ±1, and the specific matrix is ​​as follows:

[0017] in, For Bernoulli observation matrix, The number of rows in the observation matrix, i.e., the dimension of the compressed data. The number of DCT coefficients to be retained.

[0018] Preferably, the signal reconstruction process involves iterative searching with a jump step size using a coarse search layer, specifically: Initialize residuals: ; Support set: ; in, For the residual vector, To compress the observation vector, For storing the support set of atomic indexes for dictionaries; The first three iterations use a skip search with a step size of 2, skipping even-indexed atoms when calculating the inner product of dictionary atoms and residuals in each iteration; Four atoms are processed simultaneously by four parallel inner product calculation units. After the coarse search layer is completed, the standard OMP iteration is entered until the residual threshold or the number of iterations K is met.

[0019] Preferably, the smoothing process for the block boundaries further includes edge protection filtering: An adaptive weighted median filter is cascaded after the Chebyshev filter, which assigns double weight to the center pixel of the 5×5 window in the edge region and uses equal weight filtering for the smooth region, thereby improving the PSNR of the edge region by more than 4.2dB.

[0020] Preferably, the FPGA uses a three-dimensional storage scheduling network to construct a three-level storage architecture of BRAM-Cache-DDR, with an image cache size of 256×256 pixels.

[0021] Preferably, the implementation of the compressed sensing method in an FPGA system includes: Block-level granularity decision unit, K-value dynamic adjustment unit, mixed precision compression unit, and layered OMP reconstruction unit; Each unit is interconnected via an AXI bus. The block-level decision unit includes a parallel gradient entropy calculation IP core, and the K-value dynamic adjustment unit integrates a spectrum entropy calculator and an LSTM prediction IP core.

[0022] This invention provides a low-rank DCT compressed sensing method implemented based on FPGA. It has the following advantages: (1) Based on the gradient entropy dynamic block strategy, this compressed sensing method can automatically adjust the block granularity according to the local features of the signal. For complex texture regions with gradient entropy higher than 0.8, 8×8 fine-grained blocks are used to capture detailed features. For smooth regions with gradient entropy lower than 0.3, 32×32 coarse-grained blocks are used to improve compression efficiency. This mechanism avoids the problems of compression distortion in detailed regions and computational redundancy in smooth regions caused by traditional fixed blocks, thereby improving the compression ratio of complex texture regions and smooth regions. The block boundaries are dynamically determined by gradient entropy to ensure more accurate pixel ownership in edge regions, reduce block effects, and preserve complete structural information for subsequent reconstruction.

[0023] (2) Based on the dynamic adjustment of the K value of the spectrum entropy, it can adapt to the sparsity characteristics of the signal in real time. When the spectrum entropy signal is highly non-stationary, the number of retained DCT low-frequency coefficients is automatically increased to 24 or 32 to ensure that the information in the energy concentration area is not lost. When the signal sparsity is high, the K value is reduced to 8 to improve the compression ratio. Combined with the correlation modeling of the coefficients of adjacent blocks by LSTM predictive coding, the compression ratio is further improved. At the same time, the logic resource occupation in the FPGA is reduced by 28%, and the accuracy loss is controlled within 0.01 through the error compensation term. The triple optimization of high compression ratio, low resource consumption and high accuracy reconstruction is achieved, so that when compressing the image, the compression ratio is high and the image accuracy is completely preserved during reconstruction under low power consumption.

[0024] (3) The layered OMP algorithm is adopted in the reconstruction stage. The reconstruction speed is improved by using the FPGA parallel inner product calculation unit and the processing frame rate is improved synchronously to meet the requirements of real-time 3D ultrasound imaging. At the same time, the edge protection filter is implemented through an adaptive weighted median filter, and the inter-block phase consistency constraint is implemented by penalizing the phase difference of the DCT coefficients of adjacent blocks, so that the visual discontinuity index at the stitching point is reduced. The overall PSNR of the reconstructed image is improved compared with the traditional scheme, realizing high-fidelity signal restoration of compressed sensing in hardware real-time processing. Attached Figure Description

[0025] Figure 1 This is a flowchart illustrating the compressed sensing method steps of a low-rank DCT compressed sensing method based on FPGA implementation according to the present invention. Figure 2 This is a flowchart of a low-rank DCT compressed sensing method based on FPGA implementation according to the present invention. Figure 3 This is an FPGA system block diagram of a low-rank DCT compressed sensing method implemented on an FPGA according to the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Example 1 Please see Figure 1-2 This invention provides a low-rank DCT compressed sensing method based on FPGA. To achieve the above objectives, this invention is implemented through the following technical solution: The specific steps of the compressed sensing method are as follows: S1. The input signal is divided into blocks. The block granularity is dynamically adjusted based on the calculation result of the local gradient entropy of the signal. When the gradient entropy is higher than the set threshold, fine-grained block is used, and when it is lower than the threshold, coarse-grained block is used. The block granularity is dynamically adjusted within the preset range.

[0028] S2. Perform discrete cosine transform on the segmented signal, calculate the spectral entropy of the transformed coefficients, and dynamically adjust the number of low-frequency coefficients retained according to the magnitude of the spectral entropy to achieve a low-rank sparse representation of the signal.

[0029] S3. The Bernoulli matrix is ​​used to project and compress the sparsely represented signal. During the compression process, the low-frequency coefficients in the first half are calculated with higher precision at fixed points, while the coefficients in the second half are calculated with lower precision at fixed points. Error compensation is introduced for the low-precision calculation.

[0030] S4. The compressed signal is reconstructed on the host computer. During the reconstruction process, the coarse search layer is used to iterate with a jump step size, and then the fine search layer is used to iterate with a standard step size to complete the reconstruction of the original signal and smooth the block boundaries. In this embodiment, the input signal is processed in blocks. The block granularity is dynamically adjusted based on the calculation result of the signal local gradient entropy. The parallel computing unit inside the FPGA is used to calculate the gradient amplitude of the 3×3 window for the input signal such as ultrasonic echo pixel by pixel. The gradient entropy value is output in real time through the pipeline architecture. When the gradient entropy is higher than 0.8, the 8×8 fine-grained block logic is triggered to divide the signal into 8×8 pixel blocks to capture edge details. When the gradient entropy is lower than 0.3, the 32×32 coarse-grained block is used to reduce the number of blocks to improve processing efficiency. The block granularity is dynamically switched in the range of 8×8 to 32×32. The segmented signal is subjected to discrete cosine transform (DCT) using the FPGA's built-in DCT IP core for rapid transformation. Immediately after the transformation, the coefficients are calculated for spectral entropy. When the spectral entropy is greater than 0.7, the number of retained low-frequency coefficients K is automatically increased to 24 or 32 to ensure that the energy components of the non-stationary signal are not lost. When the spectral entropy is less than 0.3, the value of K is reduced to 8 to compress the data dimension, thereby realizing the adaptive low-rank representation of the signal in the DCT domain. Bernoulli matrix projection compression is employed, utilizing FPGA registers to store Bernoulli matrices with elements of ±1. Each low-frequency coefficient is calculated using 16-bit fixed-point calculation, then... Each coefficient uses an 8-bit fixed-point and incorporates an error compensation module. The error compensation module dynamically adjusts the compensation coefficients based on the spectral entropy and corrects the quantization error of the 8-bit coefficients in real time through an adder. In the signal reconstruction process on the host computer, the initial stage of reconstruction is carried out by searching with a step size of 2 through a coarse search layer. Four parallel computing units process four atoms simultaneously to accelerate sparse coefficient matching. The fine search layer restores the standard OMP iteration. Finally, the block boundary is subjected to adaptive weighted median filtering with a 5×5 window to eliminate stitching traces and restore the smoothness and accuracy of the image. The dynamic block-splitting mechanism driven by gradient entropy improves the compression ratio of strong echo boundaries in ultrasound images, improves the compression ratio of homogeneous regions, and achieves a higher overall average compression ratio. The adaptive adjustment of block granularity effectively balances detail preservation and compression efficiency, laying the foundation for subsequent low-rank sparse representation.

[0031] Through a gradient entropy-based dynamic block-segmentation mechanism, the algorithm automatically adjusts the block granularity according to the local texture complexity of the signal. In scenarios such as ultrasound images, fine-grained block segmentation is used for regions rich in detail, such as tissue boundaries, to avoid edge blurring caused by fixed block segmentation. Coarse-grained block segmentation is used for homogeneous regions to reduce unnecessary computation. This adaptive adjustment mechanism enables differentiated improvement in compression ratio for different feature regions, ensuring the integrity of detailed information while avoiding computational redundancy in smooth regions. This improves the overall adaptability of the compression algorithm to complex signals. Furthermore, by dynamically adjusting the number of retained low-frequency coefficients based on spectral entropy, the algorithm can adapt to the time-varying sparsity characteristics of the signal in real time, avoiding information loss due to fixed parameters in non-stationary signal scenarios. The degree calculation, combined with the characteristics of FPGA hardware, uses high-precision calculation for key coefficients and reduces the precision of minor coefficients while introducing compensation. This significantly reduces the consumption of logic resources while ensuring reconstruction quality, making it feasible for deployment on resource-constrained platforms such as FPGA. The hierarchical OMP algorithm and edge smoothing processing in the reconstruction stage improve system performance in both real-time performance and image quality. The iterative strategy combining coarse search layer and fine search layer utilizes the parallel computing capability of FPGA to accelerate sparse coefficient matching, which greatly improves the reconstruction speed and meets the requirements of real-time imaging. Edge protection filtering effectively solves the discontinuity problem caused by block stitching, ensuring the visual coherence of the reconstructed image, which is especially suitable for scenarios with strict requirements for image detail, such as medical ultrasound.

[0032] Example 2 Specifically: refer to Figure 1 and Figure 2 The dynamic adjustment of block granularity based on the calculation results of signal local gradient entropy specifically includes the following calculation formula: The gradient magnitude of pixels within a 3×3 window is calculated using the Sobel operator. ;

[0033] in, This represents the total number of pixels within the window. For gradient entropy, Gradient magnitude vector of Norm, i.e. ; when When using 8×8 blocks, when The intermediate value is divided into 32×32 blocks, and the middle value is divided into 16×16 blocks. The block size can be adjusted from 8×8 to 32×32.

[0034] Four sets of parallel Sobel operator modules are used, each containing six multipliers. By cascading registers, four pixel windows are processed per clock cycle, and the gradient magnitude calculation accuracy reaches 16-bit fixed point. Calculates L1 norm using a 9-input adder And by storing a logarithmic lookup table in BRAM, it is achieved Fast lookup, pipeline latency is 16 clock cycles; Set up dual threshold comparators (0.3 and 0.8) to output block granularity control signals of 8×8 / 16×16 / 32×32, and generate a BRAM address mapping table to support real-time indexing of 2048×2048 pixels when the maximum block size is 32×32.

[0035] The dynamic adjustment of the spectral entropy to retain the number of low-frequency coefficients is specifically achieved by calculating the spectral entropy of the coefficients after the DCT transform, and the specific calculation formula is as follows:

[0036] in, For the first DCT coefficients, This represents the total number of coefficients after the DCT transformation. For spectral entropy, Gradient magnitude vector of Norm, i.e. ; when When the retention factor K is set to 24 or 32, Set the hour value to 8 and the median value to 16. The LSTM model is trained using the previous DCT coefficients, and the number of neurons in the hidden layer is... Differential encoding is performed on the first K coefficients of the current block to control the prediction error within 5%.

[0037] A pipelined accumulator is used, processing 8 DCT coefficients per cycle. The absolute value is extracted based on the sign bit, normalized, and then the logarithm table is consulted. The spectral entropy calculation takes [time value missing]. One cycle; Dynamic K-value mapping table: , , The DCT coefficient extraction logic is switched in real time via a state machine.

[0038] The LSTM model performs differential encoding on the DCT coefficients as follows: The first K DCT coefficients of adjacent blocks are used as the input sequence of LSTM. The weight matrix is ​​determined through offline training and then stored in FPGAROM. The model parameters are updated once every 16 blocks.

[0039] Error compensation is introduced for low-precision calculations. The specific error compensation items are set as follows:

[0040] in, This is the error compensation value for an 8-bit fixed-point number. This is the compensation coefficient, with a value ranging from 0.1 to 0.3. The maximum value of a 16-bit fixed-point number. It is the maximum value of an 8-bit fixed-point number.

[0041] For every 16 blocks processed, online gradient descent is performed through the FPGA's internal DSP unit to update the weight matrix, thereby reducing the prediction error. The difference between the current block coefficient and the predicted value is encoded by an 8-bit quantizer and lossless compression is achieved with sign bit extension. When K=16, differential encoding reduces the amount of data per block and increases the compression ratio accordingly. compensation coefficient Dynamic generation: using a 2-bit state machine. , Implemented through shift registers Fast calculation; Error correction circuit: Processes four 8-bit coefficients per cycle, and superimposes the compensation value through a 16-bit adder to output a 16-bit equivalent precision coefficient.

[0042] The Bernoulli matrix projection compression also includes a dynamic refresh mechanism, which is specifically as follows: Every 1024 samples, a new Bernoulli matrix seed is generated through the FPGA's internal PRNG module. The matrix elements are ±1, and the specific matrix is ​​as follows:

[0043] in, For Bernoulli observation matrix, The number of rows in the observation matrix, i.e., the dimension of the compressed data. The number of DCT coefficients to be retained.

[0044] A 32-bit LFSR is used to generate a random seed, which is refreshed every 1024 samples. The seed update period is 16 clock cycles, and the generated Bernoulli matrix satisfies the RIP condition. By storing ±1 elements in binary (0 / 1), a 128×16 matrix requires only 256 bits of storage, saving storage resources for floating-point matrices.

[0045] During signal reconstruction, an iterative search is performed using a coarse search layer with a jump step size, specifically: Initialize residuals: ; Support set: ; in, For the residual vector, To compress the observation vector, For storing the support set of atomic indexes for dictionaries; The first three iterations use a skip search with a step size of 2, skipping even-indexed atoms when calculating the inner product of dictionary atoms and residuals in each iteration; Four atoms are processed simultaneously by four parallel inner product calculation units. After the coarse search layer is completed, the standard OMP iteration is entered until the residual threshold or the number of iterations K is met. Here, the four parallel inner product calculation units process four atoms simultaneously using FPGA for parallel inner product calculation.

[0046] The smoothing process for block boundaries also includes edge protection filtering: An adaptive weighted median filter is cascaded after the Chebyshev filter, which assigns double weight to the center pixel of the 5×5 window in the edge region and uses equal weight filtering for the smooth region, thereby improving the PSNR of the edge region by more than 4.2dB. The FPGA uses a three-dimensional memory scheduling network to build a three-level memory architecture of BRAM-Cache-DDR, with an image cache size of 256×256 pixels.

[0047] A row buffer is constructed using 25 shift registers, and the weights are dynamically loaded based on gradient entropy. The center pixel is generated with a weight of 2, and the remaining pixels with a weight of 1. Weighted summation is achieved through a 16-bit adder. In the boundary region of the ultrasound image, the edge blurring is reduced after filtering, making the image edges smooth and clear, and making the image edge boundaries obvious. The access time is recorded by a 16-bit counter, which improves the hit rate of the 256×256 pixel cache and reduces the number of DDR accesses, thereby improving the efficiency of compressed sensing.

[0048] In this embodiment, dynamic segmentation and LSTM prediction improve the average compression ratio of abdominal ultrasound images, showing a significant improvement compared to fixed segmentation and static K-value schemes. The compression ratios of both strong and weak echo regions are simultaneously improved. Hybrid precision calculation combined with error compensation maintains the PSNR at 42.31dB, with minimal decrease compared to full 16-bit calculation, resulting in improved PSNR in edge regions. The resolution of blood vessel walls in ultrasound images ensures their clarity. The dynamic K-value adjustment module occupies 1200 LUTs, and the LSTM prediction engine occupies 850 LUTs and 16 DSP48E1s, saving logic resources compared to traditional full-precision schemes. This meets the requirements for real-time acquisition of multi-channel ultrasound. Layered OMP reconstruction significantly reduces single-frame processing time. Combined with a pipelined architecture, high frame rate processing is achieved, supporting real-time reconstruction and display of 3D ultrasound imaging.

[0049] Through the deep integration of hardware acceleration and algorithm optimization, efficient deployment of compressed sensing on the FPGA platform has been achieved. The pipeline architecture with dynamic block granularity adjustment integrates gradient calculation, entropy analysis, and block decision-making into the FPGA hardware unit, significantly reducing block switching latency and enabling real-time response to changes in signal characteristics. It maintains stable compression performance in dynamic scenarios. This hardware design not only improves processing speed but also enables synchronous processing of multi-channel signals through parallel computing units, providing support for multi-channel acquisition systems such as ultrasonic arrays. At the same time, the collaborative mechanism of dynamic K-value adjustment and LSTM predictive coding further explores the sparsity potential of signals at the algorithm level. The dynamic switching of K-value guided by spectral entropy enables the algorithm to automatically optimize the sparsity dimension according to the signal spectral characteristics, maximizing data compression while ensuring that information in energy-concentrated areas is not lost. The LSTM model models the correlation of coefficients in adjacent blocks, further reducing redundancy by utilizing the spatial continuity of the signal. This predictive coding method achieves a significant improvement in compression ratio without additional hardware overhead, demonstrating the deep collaborative optimization between algorithms and hardware.

[0050] Example 3 Specifically: refer to Figure 3 The implementation of compressed sensing methods in FPGA systems includes: Block-level granularity decision unit: contains 4 parallel gradient entropy calculation IP cores, processes 4 3×3 windows per cycle, outputs block-level granularity control signals through AXIStream interface, and has a response time of <100ns. K-value dynamic adjustment unit: integrates a spectrum entropy calculator and a lightweight LSTM prediction IP core. The LSTM adopts a pipelined architecture, processes one coefficient per cycle, and supports real-time switching of K=8 / 16 / 24 / 32. Hybrid precision compression unit: front The coefficients are then processed by a 16-bit multiplier and a Bernoulli matrix. The coefficients are projected ±1 using an 8-bit adder, and the error compensation module processes 4 coefficients per cycle. Hierarchical OMP Reconstruction Unit: Includes 4 parallel inner product calculation units and a phase constraint optimizer. The coarse search layer and fine search layer are automatically switched through a state machine, supporting real-time reconstruction at 2300fps. Each unit is interconnected via an AXI bus. The block-level decision unit contains a parallel gradient entropy calculation IP core, and the K-value dynamic adjustment unit integrates a spectrum entropy calculator and an LSTM prediction IP core. In the three-level storage architecture, BRAM serves as the first-level cache to store the current block data, and the 256×256 pixel Cache serves as the second-level cache. It buffers DDR read and write data through operation. The MIG core is configured with a frequency of 1600MT / s, which reduces the DDR access bandwidth. Each unit is interconnected through the AXI4-Stream bus, and the data transmission rate reaches 1.2GB / s, which meets the parallel processing requirements of multi-channel ultrasonic signals. In this embodiment, the FPGA system reduces DDR bandwidth through three-dimensional memory scheduling and achieves a high processing frame rate in conjunction with the pipeline architecture, which is a significant improvement over traditional solutions. The hardware design of the block-level granularity decision unit and the K-value dynamic adjustment unit enables the algorithm to automatically adapt to different scenarios such as ultrasound imaging and industrial CT without the need for manual parameter adjustment, thus having wide engineering applicability.

[0051] The hardware integration of the block-level granularity decision unit and the K-value dynamic adjustment unit enables the algorithm to automatically adapt to the characteristic differences of different types of signals, improving the algorithm's versatility and adaptability at the system level. It can maintain excellent performance in various scenarios such as medical ultrasound and industrial inspection without manual parameter adjustment, lowering the threshold for engineering applications. The collaborative work of the hybrid precision compression unit and the hierarchical OMP reconstruction engine realizes full-process hardware acceleration from compression to reconstruction. The parallel computing path designed based on the characteristics of FPGA architecture greatly improves the execution efficiency of key operations such as matrix operations and iterative search. Combined with the pipeline architecture, it realizes non-blocking data processing, ultimately enabling the system to process frame rates more than twice that of traditional solutions, meeting the time-sensitive application requirements such as real-time imaging.

[0052] The optimized design of the three-dimensional storage scheduling network effectively solves the bottleneck problem of FPGA storage bandwidth. The BRAM-Cache-DDR three-level storage architecture reduces access to external storage through the principle of spatial locality, realizes pipelined data transmission, improves data processing efficiency without increasing hardware costs, and provides storage guarantee for real-time processing of multi-channel, large-volume signals. By utilizing system-level resource scheduling strategies, FPGA achieves high-performance compressed sensing processing under limited resource conditions, expanding the engineering application scenarios of the algorithm.

[0053] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.

Claims

1. A low-rank DCT compressed sensing method based on FPGA implementation, characterized in that: The specific steps of the compressed sensing method are as follows: S1. The input signal is divided into blocks, and the block granularity is dynamically adjusted based on the calculation result of the local gradient entropy of the signal. When the gradient entropy is higher than the set threshold, fine-grained block is used, and when it is lower than the threshold, coarse-grained block is used. The block granularity is dynamically adjusted within the preset range. S2. Perform discrete cosine transform on the segmented signal, calculate the spectral entropy of the transformed coefficients, and dynamically adjust the number of low-frequency coefficients retained according to the magnitude of the spectral entropy to achieve a low-rank sparse representation of the signal. S3. The Bernoulli matrix is ​​used to project and compress the sparsely represented signal. During the compression process, the first half of the low-frequency coefficients are calculated with higher precision at fixed points, while the second half of the coefficients are calculated with lower precision at fixed points. Error compensation is introduced for the low-precision calculation. S4. The compressed signal is reconstructed on the host computer. During the reconstruction process, the coarse search layer is used to iterate with a jump step size, and then the fine search layer is used to iterate with a standard step size to complete the reconstruction of the original signal and smooth the block boundaries.

2. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The dynamic adjustment of block granularity based on the calculation result of signal local gradient entropy specifically includes the following calculation formula: The gradient magnitude of pixels within a 3×3 window is calculated using the Sobel operator. ; ； in, This represents the total number of pixels within the window. For gradient entropy, Gradient magnitude vector of Norm, i.e. ; when When using 8×8 blocks, when The intermediate value is divided into 32×32 blocks, and the middle value is divided into 16×16 blocks. The block size can be adjusted from 8×8 to 32×32.

3. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The dynamic adjustment of the magnitude of the spectral entropy and the number of low-frequency coefficients retained are specifically calculated by quantifying the spectral entropy of the coefficients after the DCT transform, and the specific calculation formula is as follows: ； in, For the first DCT coefficients, This represents the total number of coefficients after the DCT transformation. For spectral entropy, DCT coefficient vector of Norm, i.e. ; when When the retention factor K is set to 24 or 32, Set the hour value to 8 and the median value to 16. The LSTM model is trained using the previous DCT coefficients, and the number of neurons in the hidden layer is... Differential encoding is performed on the first K coefficients of the current block to control the prediction error within 5%.

4. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 3, characterized in that: The LSTM model performs differential encoding of the DCT coefficients as follows: The first K DCT coefficients of adjacent blocks are used as the input sequence of LSTM. The weight matrix is ​​determined through offline training and stored in FPGAROM. The model parameters are updated once every 16 blocks.

5. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The specific error compensation item for the low-precision calculation is set as follows: ； in, This is the error compensation value for an 8-bit fixed-point number. This is the compensation coefficient, with a value ranging from 0.1 to 0.

3. The maximum value of a 16-bit fixed-point number. It is the maximum value of an 8-bit fixed-point number.

6. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The Bernoulli matrix also includes a dynamic refresh mechanism during projection compression, which specifically includes: Every 1024 samples, a new Bernoulli matrix seed is generated through the FPGA's internal PRNG module. The matrix elements are ±1, and the specific matrix is ​​as follows: ； in, For Bernoulli observation matrix, The number of rows in the observation matrix, i.e., the dimension of the compressed data. The number of DCT coefficients to be retained.

7. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The signal reconstruction process involves iterative searching with a jump step size using a coarse search layer, specifically: Initialize residuals: ; Support set: ; in, For the residual vector, To compress the observation vector, For storing the support set of atomic indexes for dictionaries; The first three iterations use a skip search with a step size of 2, skipping even-indexed atoms when calculating the inner product of dictionary atoms and residuals in each iteration; Four atoms are processed simultaneously by four parallel inner product calculation units. After the coarse search layer is completed, the standard OMP iteration is entered until the residual threshold or the number of iterations K is met.

8. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The smoothing process for the block boundaries also includes edge protection filtering: An adaptive weighted median filter is cascaded after the Chebyshev filter, which assigns double weight to the center pixel of the 5×5 window in the edge region and uses equal weight filtering for the smooth region, thereby improving the PSNR of the edge region by more than 4.2dB.

9. The low-rank DCT compressed sensing method based on FPGA implementation according to claim 1, characterized in that: The FPGA internally employs a three-dimensional storage scheduling network to construct a three-level storage architecture of BRAM-Cache-DDR, with an image cache size of 256×256 pixels.

10. A system for implementing a low-rank DCT compressed sensing method based on FPGA, characterized in that, The system is used to implement the method described in any one of claims 1-9: it includes a block granularity decision unit: containing 4 parallel gradient entropy calculation IP cores, processing 4 3×3 windows per cycle, outputting block granularity control signals through the AXIStream interface, with a response time of <100ns; K-value dynamic adjustment unit: integrates a spectrum entropy calculator and a lightweight LSTM prediction IP core. The LSTM adopts a pipelined architecture, processes one coefficient per cycle, and supports real-time switching of K=8 / 16 / 24 / 32. Hybrid precision compression unit: front The coefficients are then processed by a 16-bit multiplier and a Bernoulli matrix. The coefficients are projected ±1 using an 8-bit adder, and the error compensation module processes 4 coefficients per cycle. Hierarchical OMP Reconstruction Unit: Includes 4 parallel inner product calculation units and a phase constraint optimizer. The coarse search layer and fine search layer are automatically switched through a state machine, supporting real-time reconstruction at 2300fps. Each unit is interconnected via an AXI bus. The block-level decision unit includes a parallel gradient entropy calculation IP core, and the K-value dynamic adjustment unit integrates a spectrum entropy calculator and an LSTM prediction IP core.

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