Silicon wafer evaluation method, manufacturing method, device, storage medium, and electronic device

Abstract

The application provides a silicon wafer evaluation method, a manufacturing method, a device, a storage medium and an electronic equipment, and the silicon wafer evaluation method comprises the following steps: obtaining an edge contour of a silicon wafer to be evaluated, the edge contour comprising a first contour corresponding to a main surface of the silicon wafer to be evaluated; performing linear fitting processing on the first contour to obtain a first straight line; rotating the first straight line clockwise by a target angle and performing translation processing to obtain a reference straight line of the edge contour, the target angle being greater than 0, and the reference straight line not intersecting with the edge contour; determining a position closest to the reference straight line in the edge contour as a target position, and intercepting the contour on both sides of the target position in the edge contour to obtain an intercepted contour; performing circular fitting processing on the intercepted contour to obtain a fitting circle, and determining an evaluation result according to the radius of the fitting circle, the evaluation result being used for evaluating the edge shape of the thickness direction section of the silicon wafer to be evaluated. The application can effectively evaluate the edge shape of the silicon wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a silicon wafer evaluation method, manufacturing method, apparatus, storage medium, and electronic device. Background Technology

[0002] In the semiconductor silicon wafer manufacturing process, the geometry of the wafer edge has a significant impact on subsequent processes and device performance. Typically, the transition region between the wafer surface and the edge is designed with a sharp-cornered structure to optimize the stability of processes such as thin film deposition and photolithography alignment.

[0003] However, in actual processing, after the silicon wafer is chamfered, it still needs to undergo subsequent processes such as double-side polishing (DSP) and selective etching (SE). The mechanical or chemical effects of these processes will cause the originally designed sharp corners to be eroded, forming a rounded corner structure of a certain size. There is currently no accurate measurement method for this rounded corner structure, which makes it impossible to effectively evaluate the edge shape of the silicon wafer. Summary of the Invention

[0004] In view of this, the present invention aims to provide a silicon wafer evaluation method, manufacturing method, apparatus, storage medium, and electronic device to solve the problem that the edge shape of silicon wafers cannot be effectively evaluated in the prior art.

[0005] This invention provides a silicon wafer evaluation method, the method comprising:

[0006] Obtain the edge contour of the silicon wafer to be evaluated, wherein the edge contour includes a first contour corresponding to the main surface of the silicon wafer to be evaluated;

[0007] The first contour is fitted with a straight line to obtain a first straight line;

[0008] After rotating the first straight line clockwise by the target angle and translating it, a reference straight line for the edge contour is obtained. The target angle is greater than 0, and the reference straight line does not intersect the edge contour.

[0009] The position closest to the reference line in the edge contour is determined as the target position, and the contours on both sides of the target position in the edge contour are cropped to obtain the cropped contour.

[0010] The extracted contour is subjected to circle fitting to obtain a fitted circle, and the evaluation result is determined based on the radius of the fitted circle. The evaluation result is used to evaluate the edge shape of the thickness direction section of the silicon wafer to be evaluated.

[0011] In one embodiment, the edge contour further includes a second contour corresponding to the chamfered surface of the silicon wafer to be evaluated, the chamfered surface being adjacent to the main surface, and the method further includes:

[0012] The angle between the acute angle formed by the first line and the second line is determined as the reference angle;

[0013] The target angle is determined based on the reference angle, and the target angle is smaller than the reference angle.

[0014] In one embodiment, determining the target angle based on the reference angle includes:

[0015] The target angle is determined by half of the reference angle.

[0016] In one embodiment, the method further includes:

[0017] The second straight line is rotated counterclockwise by the target angle to obtain the reference straight line.

[0018] In one embodiment, rotating the first straight line clockwise by a target angle to obtain a reference straight line for the edge contour includes:

[0019] The first straight line is rotated clockwise by the target angle and then translated vertically until the reference straight line does not intersect with the edge contour, thus obtaining the reference straight line;

[0020] After rotating the second straight line counterclockwise by the target angle and performing a translation, the reference straight line is obtained, including:

[0021] The second straight line is rotated clockwise by the target angle and then translated horizontally until the reference straight line does not intersect with the edge contour, thus obtaining the reference straight line.

[0022] In one embodiment, the step of cropping the contours on both sides of the target position in the edge contour to obtain the cropped contour includes:

[0023] With the target position as the center, the contours on both sides of the target position in the edge contour are smoothed to obtain the smoothed third contour and fourth contour.

[0024] The third and fourth contours are cut off according to a preset cutting distance to obtain the cut-off contours.

[0025] In one embodiment, the step of smoothing the contours on both sides of the target position in the edge contour, centered on the target position, to obtain smoothed third and fourth contours, includes:

[0026] The contour to the left of the target position is smoothed by first-order processing to obtain the third contour;

[0027] The fourth contour is obtained by performing second-order smoothing on the contour to the right of the target position.

[0028] In one embodiment, obtaining the edge contour of the silicon wafer to be evaluated includes:

[0029] Obtain a cross-sectional view of the silicon wafer to be evaluated in the width direction;

[0030] The cross-sectional image is binarized, and the binarized cross-sectional image is then subjected to contour extraction to obtain the edge contour.

[0031] In one embodiment, the contour extraction process performed on the binarized cross-sectional image to obtain the edge contour includes:

[0032] The binarized cross-sectional image is subjected to contour extraction processing to obtain the initial edge contour in the pixel coordinate system;

[0033] The initial edge contour is subjected to subpixel correction processing, and the initial edge contour after subpixel correction processing is transformed to the size coordinate system to obtain the edge contour.

[0034] In one embodiment, the sub-pixel correction processing of the initial edge contour includes:

[0035] If discontinuous points are detected in the initial edge contour, then multiple edge sub-contours are determined from the initial edge contour based on the discontinuous points;

[0036] The edge sub-contour with the largest contour length among the plurality of edge sub-contours is determined as the initial edge sub-contour;

[0037] If it is determined that the initial edge sub-contour includes the contour corresponding to the main surface and the contour corresponding to the chamfered surface, then the initial edge sub-contour is determined as the target edge sub-contour, and sub-pixel correction processing is performed on the target edge sub-contour.

[0038] In one embodiment, before transforming the initial edge contour after subpixel correction processing to a size coordinate system to obtain the edge contour, the method further includes:

[0039] The initial edge contour after the subpixel correction process is then encrypted.

[0040] In one embodiment, the data encryption processing of the initial edge contour after the sub-pixel correction process includes:

[0041] A specified number of pixels are inserted between every two adjacent pixels in the initial edge contour after the subpixel correction process.

[0042] In one embodiment, prior to binarizing the cross-sectional view, the method further includes:

[0043] The cross-sectional image is then subjected to Gaussian smoothing.

[0044] In one embodiment, transforming the initial edge contour after subpixel correction processing to a size coordinate system to obtain the edge contour includes:

[0045] The initial edge contour after subpixel correction is transformed to the size coordinate system to obtain the transformed initial edge contour;

[0046] The transformed initial edge contour is homogenized to obtain the edge contour.

[0047] In one embodiment, the transformed initial edge contour is homogenized to obtain the edge contour, including:

[0048] The horizontal distance between any two adjacent data points in the converted initial edge contour is adjusted to a specified distance to obtain the edge contour.

[0049] Another aspect of the present invention provides a method for manufacturing a silicon wafer, the method comprising:

[0050] Obtain a target cross-sectional view of the fabricated silicon wafer in the width direction;

[0051] The target cross-sectional image is evaluated using the silicon wafer evaluation method described above to obtain the evaluation result corresponding to the target cross-sectional image.

[0052] If the evaluation result does not meet the preset manufacturing requirements, the process parameters of the manufacturing process corresponding to the manufactured silicon wafer are adjusted according to the evaluation result corresponding to the target cross-sectional diagram, so as to manufacture the silicon wafer based on the adjusted manufacturing process.

[0053] In another aspect, the present invention provides a silicon wafer evaluation apparatus, the silicon wafer evaluation apparatus comprising:

[0054] The contour acquisition module is used to acquire the edge contour of the silicon wafer to be evaluated, wherein the edge contour includes a first contour corresponding to the main surface of the silicon wafer to be evaluated.

[0055] The line fitting module is used to perform line fitting on the first contour to obtain a first straight line;

[0056] The rotation processing module is used to rotate the first straight line clockwise by a target angle and perform translation processing to obtain a reference straight line of the edge contour. The target angle is greater than 0, and the reference straight line does not intersect with the edge contour.

[0057] The cropping module is used to determine the position in the edge contour that is closest to the reference line as the target position, and to crop the contours on both sides of the target position in the edge contour to obtain the cropped contour.

[0058] The result determination module is used to perform circle fitting processing on the intercepted contour to obtain a fitted circle, and to determine the evaluation result by setting the radius of the fitted circle. The evaluation result is used to evaluate the edge shape of the cross section in the thickness direction of the silicon wafer to be evaluated.

[0059] In another aspect, the present invention provides a silicon wafer manufacturing apparatus, the silicon wafer manufacturing apparatus comprising:

[0060] The image acquisition module is used to acquire a target cross-sectional view of the manufactured silicon wafer in the width direction;

[0061] The evaluation module is used to evaluate the target cross-sectional image using the silicon wafer evaluation method described above, and to obtain the evaluation result corresponding to the target cross-sectional image.

[0062] The process adjustment module is used to adjust the process parameters of the manufacturing process corresponding to the manufactured silicon wafer according to the evaluation result corresponding to the target cross-sectional diagram if the evaluation result does not meet the preset manufacturing requirements, so as to manufacture the silicon wafer based on the adjusted manufacturing process.

[0063] In another aspect, the present invention provides a computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement the silicon wafer evaluation method as described in any of the above embodiments.

[0064] In another aspect, the present invention provides an electronic device, the electronic device comprising:

[0065] processor;

[0066] Memory used to store the processor's executable instructions;

[0067] The processor is used to execute the silicon wafer evaluation method described in any of the above embodiments.

[0068] Compared with related technologies, the silicon wafer evaluation method provided by this invention has the following advantages:

[0069] The silicon wafer evaluation method provided by this invention obtains the edge contour of the silicon wafer to be evaluated, wherein the edge contour includes a first contour corresponding to the main surface of the silicon wafer to be evaluated; and performs straight line fitting processing on the first contour to obtain a first straight line; then, rotates the first straight line clockwise by a target angle and performs translation processing to obtain a reference straight line of the edge contour, wherein the target angle is greater than 0 and the reference straight line does not intersect the edge contour, so that the reference straight line roughly parallel to the tangent of the sharp corner point on the edge contour can be quickly obtained using the target angle, so as to effectively locate the area where the sharp corner point of the edge contour is located using the reference straight line; then, the position in the edge contour closest to the reference straight line is determined as the target position, so that the target position corresponding to the sharp corner point can be accurately found from the edge contour by the distance distribution between the edge contour and the reference straight line. Then, the contours on both sides of the target position in the edge contour are truncated to obtain the truncated contour. Finally, the truncated contour is subjected to circle fitting to obtain a fitted circle, and the evaluation result is determined based on the radius of the fitted circle. This evaluation result is used to evaluate the edge shape of the cross-section in the thickness direction of the silicon wafer under evaluation. Thus, by using the target position corresponding to the sharp corner point, the rounded corner area on the edge contour can be accurately located, and the radius of the rounded corner is used as the evaluation result. It can be seen that this method automatically locks the rounded corner by utilizing the geometric relationships existing in the edge contour. Compared with direct manual measurement, this method can effectively eliminate positioning errors, improve the measurement accuracy of the rounded corner, and thus achieve effective evaluation of the edge shape of the silicon wafer. Attached Figure Description

[0070] Figure 1 The figure shown is a cross-sectional view of a silicon wafer in the width direction according to an embodiment of the present invention.

[0071] Figure 2 The diagram shown is a schematic flowchart of a silicon wafer evaluation method provided in an embodiment of the present invention.

[0072] Figure 3 The image shown is a cross-sectional view after binarization according to an embodiment of the present invention.

[0073] Figure 4 The image shown is a cropped image from a cross-sectional view after binarization processing, provided in an embodiment of the present invention.

[0074] Figure 5 The image shown is an initial edge contour diagram provided in an embodiment of the present invention.

[0075] Figure 6 The image shown is another initial edge contour diagram provided by an embodiment of the present invention.

[0076] Figure 7 The image shown is an initial edge contour map after subpixel correction and data encryption provided in an embodiment of the present invention.

[0077] Figure 8 The image shown is an edge contour diagram provided in an embodiment of the present invention.

[0078] Figure 9 The diagram shown is a schematic representation of the distribution of the first and second contours according to an embodiment of the present invention.

[0079] Figure 10 The diagram shows the positional relationship between a reference line, a first line, and a second line according to an embodiment of the present invention.

[0080] Figure 11 The diagram shown is a schematic representation of the distance distribution relationship between the edge contour and the reference line according to an embodiment of the present invention.

[0081] Figure 12 The diagram shown is a schematic diagram of the process iteration for the cusp position provided in an embodiment of the present invention.

[0082] Figure 13 The diagram shown is a schematic representation of the distribution of the third and fourth contours according to an embodiment of the present invention.

[0083] Figure 14 The diagram shown is a schematic representation of the positional relationship between the fitted circle and the edge contour provided in an embodiment of the present invention.

[0084] Figure 15 The diagram shown is a schematic flow chart of a silicon wafer manufacturing method according to an embodiment of the present invention.

[0085] Figure 16 The diagram shown is a schematic block diagram of a silicon wafer evaluation device provided in an embodiment of the present invention.

[0086] Figure 17 The diagram shown is a schematic block diagram of a silicon wafer manufacturing apparatus provided in an embodiment of the present invention.

[0087] Figure 18 The diagram shown is a block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0088] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0089] like Figure 1As shown, a silicon wafer typically includes a main surface, a chamfered surface (hereinafter also called a chamfered face), rounded corners (hereinafter also called rounded corners), and edge ends. The main surface refers to the flat area on the front or back of the silicon wafer, used for device manufacturing. The chamfered surface is the inclined transition surface between the edge end and the main surface, formed by mechanical chamfering to reduce the risk of edge chipping. The edge ends are the outermost inactive areas of the silicon wafer, not involved in device manufacturing, used to prevent edge defects from affecting the performance of chips manufactured from this silicon wafer.

[0090] In silicon wafer fabrication, the transition corners from the wafer surface to the edge are typically machined into sharp corners. Ideally, the junction between the main surface and the chamfered surface should be a sharp corner (hereinafter referred to as a point). However, this sharp corner can be affected by subsequent processes after chamfering. For example, due to polishing, etching, and other processes, the sharp corner may degenerate into a rounded corner, creating a rounded transition area between the beveled surface and the main surface—an unintended rounded corner. Fluctuations in the size and shape of this rounded corner can significantly affect the client's process yield. For instance, film peeling may occur. Specifically, changes in the curvature of the rounded corner area affect the stress distribution of the film, leading to a decrease in local film adhesion and peeling during subsequent heat treatment or chemical treatment. Another example is film residue. Specifically, rounded corners may cause uneven film deposition, resulting in residue in the edge area, affecting the device's electrical performance or causing a short circuit risk. For example, there may be a decrease in process stability. Specifically, the randomness of the rounded corners causes differences in the edge morphology of different batches of silicon wafers, affecting the repeatability and yield of the customer's process.

[0091] However, while the current Semiconductor Equipment and Materials International (SEMI) standard provides measurement specifications for the rounded corner morphology of the transition region at the edge of silicon wafers, the measurement accuracy is still insufficient, making it impossible to effectively evaluate the edge shape of silicon wafers and thus failing to guarantee the process yield of silicon wafer manufacturing.

[0092] In view of the above problems, one embodiment of the present invention provides a silicon wafer evaluation method, which can be executed by a computer device (e.g., a server or a user terminal). Figure 2 As shown, the silicon wafer evaluation method may include:

[0093] 110. Obtain the edge contour of the silicon wafer to be evaluated, wherein the edge contour includes the first contour corresponding to the main surface of the silicon wafer to be evaluated.

[0094] Here, the edge profile can refer to the profile formed by the edges of the silicon wafer to be rated in a cross-sectional image (hereinafter referred to as the cross-sectional image) in its width direction. Optionally, the edge profile can be specifically represented by a set of coordinates in the cross-sectional image, and the computer device can obtain the edge profile by receiving the set of coordinates corresponding to the edge profile.

[0095] It is understandable that in the above cross-sectional view, the main surface, chamfered surface, and transition fillet of the silicon wafer to be rated correspond to parts of the edge contour.

[0096] In some implementations, the specific implementation of "obtaining the edge contour of the silicon wafer to be evaluated" in step 110 may include:

[0097] 111. Obtain a cross-sectional view of the silicon wafer to be evaluated in the width direction.

[0098] In some embodiments, the cross-sectional image may be an image obtained by taking a cross-section of the silicon wafer to be evaluated in the width direction using a microscope. Optionally, the acquired cross-sectional image may be sent to the aforementioned computer device and stored.

[0099] 112. Perform binarization on the cross-sectional image, and then perform contour extraction on the binarized cross-sectional image to obtain the edge contour.

[0100] In some implementations, there may be multiple cross-sectional images of the silicon wafer to be evaluated. Before binarizing the cross-sectional images, the clarity of the multiple cross-sectional images can be compared. Based on the comparison results, the cross-sectional image with the highest clarity among the multiple cross-sectional images can be binarized, thereby improving the accuracy of edge contour extraction.

[0101] In some implementations, a dual-threshold binarization method can be used when binarizing the cross-sectional image. Specifically, the first threshold can be 127, and the second threshold can be 255. For each pixel in the cross-sectional image, if the pixel value is less than 127, the pixel value can be set to 0 (i.e., black); if the pixel value is greater than or equal to 127 and less than or equal to 255, the pixel value can be set to 255 (i.e., white), thereby accurately dividing the area corresponding to the silicon wafer to be evaluated in the cross-sectional image. For example, the binarized cross-sectional image can be as follows: Figure 3 As shown, in Figure 3 The black area in the image represents the region corresponding to the silicon wafer to be evaluated.

[0102] In this embodiment, by binarizing the cross-sectional image, the silicon wafer to be evaluated can be segmented from the background of the cross-sectional image, so that the edge contour of the silicon wafer to be evaluated can be extracted more accurately in the subsequent process.

[0103] In some implementations, to improve the efficiency and accuracy of analyzing the rounded corners of the silicon wafer under evaluation, an edge contour extraction can be performed by extracting a region containing only the chamfered edges of the silicon wafer under evaluation from the binarized cross-sectional image. For example, the region extracted from the binarized cross-sectional image can be as follows: Figure 4 As shown, this area includes a portion of the main surface, a portion of the chamfered surface, and the fillet between the portion of the main surface and the portion of the chamfered surface.

[0104] In some implementations, the specific implementation of "performing contour extraction processing on the binarized cross-sectional image to obtain the edge contour" in step 112 may include:

[0105] 1121. Perform contour extraction on the binarized cross-sectional image to obtain the initial edge contour in the pixel coordinate system.

[0106] In some implementations, the binarized cross-sectional image can be processed by edge tracking algorithm and adjacent point search algorithm to extract the contour and obtain the initial edge contour in pixel coordinate system.

[0107] Considering that noise may cause edge breaks or false edges in a binarized image, in this embodiment, isolated noise points can be identified and excluded from the contour through neighbor point search. In addition, edge tracking can ensure the continuity of the edge contour. Even if the edge is weak or discontinuous, the connection point can be found through neighbor point search, thereby restoring the complete contour and ensuring the quality of the extracted initial edge contour.

[0108] As an example, by performing contour extraction on the binarized cross-sectional image, the initial edge contour in the pixel coordinate system can be obtained as follows: Figure 5 As shown, since the region used for edge contour extraction is extracted from the binarized cross-sectional image, therefore... Figure 5 In this context, the origin of the pixel coordinate system is not (0,0), but (300,500).

[0109] 1122. Perform subpixel correction processing on the initial edge contour, and transform the initial edge contour after subpixel correction processing to the size coordinate system to obtain the edge contour.

[0110] In some implementations, the initial edge contour can be processed using a preset sub-pixel correction algorithm to obtain the sub-pixel corrected initial edge contour. Optionally, the preset sub-pixel correction algorithm can be a pixel gradient-based algorithm.

[0111] In some implementations, the specific implementation of "performing sub-pixel correction processing on the initial edge contour" in step 1122 may include:

[0112] If discontinuous points are detected in the initial edge contour, multiple edge sub-contours are determined from the initial edge contour based on the discontinuous points.

[0113] The edge sub-contour with the largest contour length among multiple edge sub-contours is determined as the initial edge sub-contour.

[0114] If the initial edge sub-contour is determined to include the contour corresponding to the main surface and the contour corresponding to the chamfered surface, then the initial edge sub-contour is determined as the target edge sub-contour, and sub-pixel correction processing is performed on the target edge sub-contour.

[0115] Discontinuities can refer to anomalous points in the edge contour data of a silicon wafer that disrupt the geometric continuity of the edge contour. These discontinuities may be caused by foreign matter adhering to the silicon wafer being evaluated, forming particulate contamination, or by process defects (such as polishing residue, uneven etching, etc.).

[0116] In some implementations, discontinuous points can be detected by detecting whether there is a sudden change in the distance between two adjacent points in the initial edge contour. For example, if the distance between a first position point and a second position point adjacent to each other in the initial edge contour is greater than or equal to a distance threshold, the first position point can be determined as a discontinuous point.

[0117] As an example, such as Figure 6 As shown, Figure 6 An initial edge profile is shown, in which a discontinuity point is detected at the position corresponding to the edge end of the silicon wafer to be evaluated. This discontinuity point divides the initial edge profile into edge sub-profile 1 and edge sub-profile 2.

[0118] Then, the first contour length of edge sub-contour 1 and the second contour length of edge sub-contour 2 can be obtained. The first and second contour lengths are then compared. If the first contour length is greater than the second contour length, it can be checked whether edge sub-contour 1 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface. If edge sub-contour 1 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface, it indicates that edge sub-contour 1 includes a rounded corner of the silicon wafer to be evaluated, thus edge sub-contour 1 can be identified as the target edge sub-contour. If edge sub-contour 1 does not include the contour corresponding to the main surface and the contour corresponding to the chamfer surface, it indicates that edge sub-contour 1 does not include the rounded corner of the silicon wafer to be evaluated, thus rounded corner evaluation cannot be performed. In this case, it can be further checked whether edge sub-contour 2 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface.

[0119] If the length of the second contour is greater than the length of the first contour, it can be detected whether the edge sub-contour 2 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface. If the edge sub-contour 2 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface, it indicates that the edge sub-contour 2 includes a rounded corner of the silicon wafer to be evaluated, and thus the edge sub-contour 2 can be determined as the target edge sub-contour. If the edge sub-contour 2 does not include the contour corresponding to the main surface and the contour corresponding to the chamfer surface, it can be detected again whether the edge sub-contour 2 includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface.

[0120] If the length of the first contour is equal to the length of the second contour, then any one of the edge sub-contours, edge sub-contour 1 and edge sub-contour 2, can be selected to detect whether the edge sub-contour includes the contour corresponding to the main surface and the contour corresponding to the chamfer surface. If it does, then the edge sub-contour can be determined as the target edge sub-contour.

[0121] In this embodiment, by detecting discontinuous points in the initial edge contour, and selecting the edge sub-contour with the largest contour length for subsequent evaluation when discontinuous points exist in the initial edge contour, it can be ensured that the evaluation results are not affected by discontinuous points, thereby improving the accuracy of the evaluation results.

[0122] In some implementations, before the step of "transforming the initial edge contour after subpixel correction to a size coordinate system to obtain the edge contour", the method may further include:

[0123] The initial edge contour after subpixel correction is encrypted to obtain an encrypted initial edge contour, which contains a higher density of data points compared to the initial edge contour after subpixel correction.

[0124] In some implementations, the specific implementation of the step "data encryption processing of the initial edge contour after subpixel correction" may include:

[0125] A specified number of pixels are inserted between every two adjacent pixels in the initial edge contour after subpixel correction.

[0126] In some implementations, the subpixel correction processing and data encryption processing described above can be performed simultaneously. For example, the Sobel operator (a commonly used edge detection algorithm) can be used to calculate the above... Figure 5 The pixel gradients of the contour points in the initial edge contour shown are located in the x-axis and y-axis directions of the pixel coordinate system. These pixel gradients are used to perform sub-pixel correction on the initial edge contour.

[0127] Then, the pixel data in the initial edge contour is encrypted using an encryption factor of 5, meaning 5 data points are inserted between every two data points in the original initial edge contour, resulting in an encrypted initial edge contour. Next, each data point in the encrypted initial edge contour is corrected using the aforementioned pixel gradient, thus obtaining a sub-pixel corrected and encrypted initial edge contour. The coordinates of the added pixel data can be represented as (sub_x, sub_y), where:

[0128] sub_x=(1-t)*x1+t*x2+gx / magnitude*0.5;

[0129] sub_y=(1-t)*y1+t*y2+gy / magnitude*0.5;

[0130] Where t represents the nth data point to be encrypted, gx represents the Sobel gradient component along the x-axis in the pixel coordinate system, gy represents the Sobel gradient component along the y-axis in the pixel coordinate system, magnitude represents the gradient magnitude, and (x1,y1) and (x2,y2) are the two pixel data points to be encrypted.

[0131] Following the example above, Figure 5 The initial edge contour shown is processed by subpixel correction and data encryption to obtain the subpixel corrected and data encrypted initial edge contour, as shown below. Figure 7 As shown.

[0132] Following the example above, by... Figure 5 Subpixel correction processing of the initial edge contour shown yields a subpixel-corrected and encrypted initial edge contour. Figure 7 and Figure 5 The comparison shows that the initial edge contour after subpixel correction and data encryption has improved pixel accuracy and has a higher data density compared to the initial edge contour. Therefore, a higher quality edge contour can be obtained based on the initial edge contour after subpixel correction and data encryption.

[0133] Continuing with the example above, we can... Figure 7 Transforming the subpixel-corrected and encrypted initial edge contour to a dimension coordinate system, as shown, yields the following: Figure 8 The edge contour shown is in Figure 8 In the diagram, each point on the edge contour is represented by coordinates in micrometers (μm).

[0134] In some implementations, the method may further include the following steps before the step of "binarizing the cross-sectional view":

[0135] Apply Gaussian smoothing to the cross-sectional image.

[0136] For example, the cross-sectional image can be Gaussian smoothed based on a 5×5 Gaussian kernel to smooth noise while preserving realistic edges to the maximum extent, and to provide stable input data for subsequent subpixel correction operations. The 5×5 Gaussian kernel prevents over-smoothing from blurring edge contours.

[0137] In some implementations, the specific implementation of the step "transforming the initial edge contour after subpixel correction to a size coordinate system to obtain the edge contour" may include:

[0138] The initial edge contour after subpixel correction is transformed to the size coordinate system to obtain the transformed initial edge contour.

[0139] The initial edge contour after conversion is homogenized to obtain the edge contour.

[0140] For example, linear interpolation can be used to homogenize the transformed initial edge contour so that the resulting edge contour can be effectively fitted with a straight line and a circle.

[0141] Optionally, after homogenizing the converted initial edge contour, the homogenized initial edge contour can be further processed using a smoother with a window size of 21 to obtain the edge contour.

[0142] Optionally, to reduce the amount of data processed by homogenization, a portion of the contour can be extracted from the converted initial edge contour and homogenized. For example, using... Figure 8 Taking the dimensional coordinate system shown as an example, a cutoff region can be defined within the dimensional coordinate system. The minimum x-coordinate of this cutoff region is x11, and the maximum x-coordinate is x12. The minimum y-coordinate of this cutoff region is y11, and the maximum y-coordinate is y12. Here, the maximum x-coordinate x12 is the x-coordinate of the rightmost end of the transformed initial edge contour, and the maximum y-coordinate y12 is the y-coordinate of the topmost point of the transformed initial edge contour. The minimum y-coordinate is y11 = (y12 - 300 μm), and the minimum x-coordinate is x11 = (x12 - 1200 μm). Then, the contour within the cutoff region of the transformed initial edge contour is retained and homogenized to obtain the edge contour.

[0143] In some implementations, the specific implementation of the step "to homogenize the converted initial edge contour to obtain the edge contour" may include:

[0144] The horizontal distance between any two adjacent data points in the converted initial edge contour is adjusted to a specified distance to obtain the edge contour.

[0145] For example, the specified distance can be 1.8 μm. By uniformizing the converted initial edge contour, the x-coordinates of every two adjacent data points in the obtained edge contour can be made to differ by 1.8 μm.

[0146] 120. Perform straight line fitting on the first contour to obtain the first straight line.

[0147] For example, such as Figure 9 As shown, the edge contour includes the first contour corresponding to the main surface. By performing least-squares straight-line fitting on the first contour, the first straight line can be obtained, and the first slope k1 of the first straight line can be determined in the dimension coordinate system.

[0148] Optionally, please refer to [the relevant document / reference]. Figure 9 To reduce the amount of data required for line fitting and to ensure that the first straight line more closely approximates the flatness of the main surface of the silicon wafer being evaluated, a portion of the first contour can be selected for line fitting to obtain the first straight line. For example, the portion of the first contour between x23 and x22 can be selected for line fitting. Figure 9 In the figure, x21 is the x-coordinate of the right end of the edge profile, x22 = (x21 - 600 μm), x23 = (x21 - 1200 μm).

[0149] 130. After rotating the first straight line clockwise by the target angle and performing translation, a reference straight line for the edge contour is obtained. The target angle is greater than 0, and the reference straight line does not intersect with the edge contour.

[0150] For example, such as Figure 10 As shown, taking a target angle of β as an example, the first straight line is rotated clockwise by the target angle and then translated to obtain a reference straight line. The acute angle between the reference straight line and the extension of the first straight line is β. Specifically, the second slope k2 of the reference straight line can be calculated based on the first slope k1 and the target angle. Then, the initial straight line with a slope of k2 passing through the left endpoint of the edge contour is solved by point-slope method, and the intercept b of the initial straight line on the y-axis in the size coordinate system is determined. The intercept b is added to a specified distance (such as 1000μm) to obtain the target intercept b1. Finally, based on the second slope k2 and the target intercept b1, the expression of the reference straight line can be determined as y = k2*x + b1.

[0151] The target angle is used to determine a reference straight line that can locate the sharp corner of the silicon wafer to be evaluated. This target angle can be set according to the actual situation. For example, different target angles can be set for silicon wafers of different sizes to be evaluated.

[0152] In some implementations, the target angle can be determined empirically; for example, for most common silicon wafers, the target angle can be 10°.

[0153] In some implementations, the target angle can be determined by a pre-trained machine learning model, which can be trained using sample angles, sample evaluation results, and data such as the size parameters and model of the sample silicon wafer. For example, the model of the silicon wafer to be evaluated can be input into the trained machine learning model, and the target angle output by the machine learning model can be obtained.

[0154] In some embodiments, the edge contour further includes a second contour corresponding to the chamfered surface of the silicon wafer to be evaluated, the chamfered surface being adjacent to the body surface. The method may also include:

[0155] S1. Determine the angle of the acute angle formed between the first and second lines as the reference angle.

[0156] S2. Determine the target angle based on the reference angle. The target angle is smaller than the reference angle.

[0157] For example, please refer again Figure 10 The acute angle formed between the first and second lines is β1. Therefore, β1 can be determined as the reference angle. Then, a target angle can be determined within the range of β1, such that the target angle β is less than the reference angle β1.

[0158] In this embodiment, by making the target angle smaller than the reference angle, it can be ensured that the reference line is not parallel to the first line and not parallel to the second line, thereby allowing for more accurate positioning of the sharp corner point using the reference line.

[0159] In some implementations, the specific implementation of "determining the target angle based on the reference angle" in step S2 may include:

[0160] The target angle is determined by half of the reference angle.

[0161] For example, please refer again Figure 10 The target angle can be determined by half the reference angle, β2. Since the contours of the rounded corners on the silicon wafer being evaluated are often symmetrical on both sides of the sharp corner, determining half the reference angle as the target angle makes the reference line roughly parallel to the tangent line on the edge contour passing through the sharp corner. Thus, the sharp corner can be accurately located using the distance distribution between the reference line and the edge contour.

[0162] In some embodiments, the silicon wafer evaluation method may further include:

[0163] A1. Rotate the second straight line counterclockwise by the target angle to obtain the reference straight line.

[0164] Since the target angle is half the acute angle between the first line and the second line, based on the symmetry between the first line and the second line, in this embodiment, the reference line is obtained by rotating the second line counterclockwise by the target angle, thereby determining the reference line more flexibly.

[0165] In some embodiments, the specific implementation of "rotating the first straight line clockwise by the target angle and translating it to obtain a reference straight line for the edge contour" in step 130 may include:

[0166] The first straight line is rotated clockwise by the target angle and then translated vertically until the reference straight line no longer intersects the edge contour, thus obtaining the reference straight line. Specifically, the first straight line can be translated along the positive y-axis in the dimension coordinate system.

[0167] In step A1, the second straight line is rotated counterclockwise by the target angle and then translated to obtain the reference straight line, including:

[0168] The second straight line is rotated clockwise by the target angle and then translated horizontally until the reference straight line no longer intersects with the edge contour, thus obtaining the reference straight line. Specifically, the second straight line can be translated along the positive x-axis in the dimension coordinate system.

[0169] 140. Determine the position in the edge contour that is closest to the reference line as the target position, and cut off the contours on both sides of the target position in the edge contour to obtain the cut-off contour.

[0170] In some implementations, the distance from each point on the edge profile to the reference line can be calculated to obtain the distance distribution relationship between the edge profile and the reference line. For example, this distance distribution relationship can be as follows: Figure 11 As shown, in Figure 11 In this coordinate system, the horizontal axis is the same as the horizontal axis in the aforementioned dimensional coordinate system, and the vertical axis is the distance between the edge profile and the reference line. Figure 11 It can be seen that the distance between the point with x0 on the edge contour and the reference line is the smallest. Therefore, the point with x0 on the edge contour can be determined as the target position.

[0171] In some embodiments, such as Figure 12 As shown, if the set target angle deviates, the target position (hereinafter referred to as the cusp position or sharp angle position) will be found inaccurately. Therefore, the accurate position of the cusp can be found through iteration. A specific implementation method is as follows:

[0172] After obtaining the cusp position based on the minimum distance in step 140, mark the coordinates of this point as P0. Take a point a certain distance to the left (e.g., 18 μm), denoted as Pl, and a point a certain distance to the right (e.g., 18 μm), denoted as Pr. Connect Pl and Pr to obtain the straight line L0. Calculate the distance from each point on the contour to the straight line L0, and mark the point with the largest distance as Pm (e.g., ...). Figure 12 (As shown). The radii of curvature of the two contours at both ends of Pl-Pm and Pm-Pr are fitted using the least squares method and denoted as Rl and Rr, respectively, with delta = Rl - Rr. The point P0 is adjusted according to the sign of delta. When delta is positive, point P0 is moved one point to the right; when delta is negative, point P0 is moved one point to the left. The new P0 is denoted as P1, and the next iteration begins. The iteration ends when the difference between delta of two iterations is less than the difference threshold (e.g., 10 μm). When oscillations occur during iteration, i.e., the delta values ​​of two consecutive iterations have opposite signs and the convergence threshold is not reached, it is necessary to adjust the magnitude of the movement of point P0 each time. Each adjustment is based on the previous movement amount plus a specified movement amount (for example, the specified movement amount can be 1), and the movement amount after adding the movement amount does not exceed the upper limit of the movement amount. For example, the movement amount can be adjusted from point 1 to a maximum of point 5. If the iteration continues to oscillate, the iteration ends and the position is regarded as the accurate position of the final cusp. If the iteration diverges for 5 consecutive iterations, the position before divergence is regarded as the accurate position of the final cusp.

[0173] In some implementations, the specific implementation of "cutting the contours on both sides of the target position in the edge contour to obtain the cut contour" in step 140 may include:

[0174] 141. Taking the target position as the center, smooth the contours on both sides of the target position in the edge contour to obtain the smoothed third contour and fourth contour.

[0175] 142. Cut the third and fourth contours according to the preset cutting distance to obtain the cut contours.

[0176] For example, such as Figure 13 As shown, the target position with the horizontal coordinate x0 can be marked as P0. Then, according to the preset interception distance, the two position points on both sides of P0 are marked as P1 and P2, respectively. The distance between P1 and P0 is the preset interception distance, and the distance between P2 and P0 is also the preset interception distance. Optionally, the preset interception distance can be 18μm.

[0177] In some implementations, the specific implementation of "smoothing the contours on both sides of the target position in the edge contour with the target position as the center to obtain the smoothed third contour and fourth contour" in step 141 may include:

[0178] The contour to the left of the target position is smoothed by first-order processing to obtain the third contour; the contour to the right of the target position is smoothed by second-order processing to obtain the fourth contour.

[0179] Please refer again to the example above. Figure 13 The contours between p1 and p0 can be smoothed using a first-order method to obtain the third contour; the contours between p2 and p0 can be smoothed using a second-order method to obtain the fourth contour. Optionally, a Savitzky-Golay filter can be used to smooth both the contours between p1 and p0 and the contours between p2 and p0. For first-order smoothing, the smoothing window size can be 31; for second-order smoothing, the smoothing window size can be 11.

[0180] In this embodiment, a third contour is obtained by performing first-order smoothing on the contour to the left of the target position; a fourth contour is obtained by performing second-order smoothing on the contour to the right of the target position, thereby improving the fitting effect when performing circle fitting based on the third and fourth contours.

[0181] 150. Perform circle fitting on the cut contour to obtain a fitted circle, and determine the evaluation result based on the radius of the fitted circle. The evaluation result is used to evaluate the edge shape of the cross section in the thickness direction of the silicon wafer to be evaluated.

[0182] For example, it is possible to... Figure 13 The edge contours between p1 and p2 in the image are fitted with circles to obtain the following: Figure 14 The fitted circle is then used, and its radius is the radius of curvature of the fillet of the silicon wafer to be evaluated. This radius of curvature is then determined as the evaluation result. Specifically, in Figure 14 The calculated radius of curvature is 99.29 μm, which is named the angular radius (AR) of the silicon wafer to be evaluated.

[0183] As can be seen, in this embodiment, by acquiring the edge contour of the silicon wafer to be evaluated, wherein the edge contour includes a first contour corresponding to the main surface of the silicon wafer to be evaluated; and performing straight line fitting processing on the first contour to obtain a first straight line; then, rotating the first straight line clockwise by a target angle and performing translation processing to obtain a reference straight line of the edge contour, wherein the target angle is greater than 0 and the reference straight line does not intersect with the edge contour, so that a reference straight line roughly parallel to the tangent of the sharp corner point on the edge contour can be quickly obtained using the target angle, so as to effectively locate the area where the sharp corner point of the edge contour is located using the reference straight line; then, the position in the edge contour closest to the reference straight line is determined as the target position, so that the target position corresponding to the sharp corner point can be accurately found from the edge contour by the distance distribution between the edge contour and the reference straight line. Then, the contours on both sides of the target position in the edge contour are truncated to obtain the truncated contour. Finally, the truncated contour is subjected to circle fitting to obtain a fitted circle, and the evaluation result is determined based on the radius of the fitted circle. This evaluation result is used to evaluate the edge shape of the cross-section in the thickness direction of the silicon wafer under evaluation. Thus, by using the target position corresponding to the sharp corner point, the rounded corner area on the edge contour can be accurately located, and the radius of the rounded corner is used as the evaluation result. It is evident that this method automatically locks the rounded corner by utilizing the geometric relationships existing in the edge contour. Compared to direct manual measurement, this method can effectively eliminate positioning errors, improve the measurement accuracy of the rounded corner, and achieve effective evaluation of the edge shape of the silicon wafer.

[0184] Furthermore, the silicon wafer evaluation method of this embodiment establishes a standardized rounded corner evaluation process based on mathematical fitting, which can directly output quantitative parameters (such as rounded corner radius). Compared with the SEMI standard, it can significantly improve the measurement accuracy of the rounded corner morphology of the silicon wafer edge transition region. In addition, the silicon wafer evaluation method of this embodiment avoids the interference of slight deformation or noise on the silicon wafer surface on the measurement results through linear fitting and reference line rotation, and has strong anti-interference ability. Moreover, the silicon wafer evaluation method of this embodiment is applicable to silicon wafers of different sizes and various edge designs (such as different chamfer angles), and only the target angle parameter needs to be adjusted to adapt, which has strong compatibility.

[0185] One embodiment of the present invention provides a silicon wafer manufacturing method, which can be executed by computer equipment (e.g., a server or user terminal). Figure 15 As shown, the silicon wafer manufacturing method may include:

[0186] 210. Obtain a target cross-sectional view of the width direction of the manufactured silicon wafer.

[0187] 220. For the target cross-sectional view, the evaluation process is carried out using the silicon wafer evaluation method described above to obtain the evaluation result corresponding to the target cross-sectional view.

[0188] 230. If the evaluation result does not meet the preset manufacturing requirements, adjusting the process parameters of the manufacturing process corresponding to the manufactured wafer according to the evaluation result corresponding to the target cross-sectional view, so as to manufacture the wafer based on the adjusted manufacturing process.

[0189] For example, the measured radius of curvature is R. If the specification requires R to be less than R0, the wafer is determined to be qualified; if R is greater than R0, feedback is sent to the DSP process to reduce the polishing pressure, so as to achieve the purpose of reducing the radius of curvature. For another example, when the radius of curvature is smaller than the specified radius of curvature, the purpose of increasing the radius of curvature can be achieved by adjusting the removal amount during automatic beveling of edge polishing (Edge Polish, EP).

[0190] It can be seen that the wafer manufacturing method in this embodiment can control the radius of curvature of the rounded corner within a reasonable range, optimize the film stress distribution, and reduce the risk of peeling; meanwhile, it reduces edge residues and avoids short circuit or leakage problems. Stable rounded corner morphology can improve client lithography alignment accuracy and film deposition uniformity, and ultimately improve chip manufacturing yield.

[0191] Figure 16 is a block diagram of a wafer evaluation apparatus provided by an embodiment of the present invention. As Figure 16 shown, the wafer evaluation apparatus 300 includes:

[0192] a profile acquisition module 310, configured to acquire an edge profile of a wafer to be evaluated, where the edge profile includes a first profile corresponding to a main surface of the wafer to be evaluated;

[0193] a straight line fitting module 320, configured to perform straight line fitting processing on the first profile to obtain a first straight line;

[0194] a rotation processing module 330, configured to rotate the first straight line clockwise by a target angle and perform translation processing to obtain a reference straight line of the edge profile, wherein the target angle is greater than 0, and the reference straight line does not intersect the edge profile;

[0195] a clipping module 340, configured to determine a position closest to the reference straight line in the edge profile as a target position, and clip the profiles on both sides of the target position in the edge profile to obtain a clipped profile;

[0196] a result determination module 350, configured to perform circle fitting processing on the clipped profile to obtain a fitted circle, and determine the radius of the fitted circle as an evaluation result, where the evaluation result is used to evaluate the edge shape of the thickness-direction cross-section of the wafer to be evaluated.

[0197] In some embodiments, the edge profile further includes a second profile corresponding to a chamfered surface of the wafer to be evaluated, the chamfered surface is adjacent to the main surface, and the apparatus 300 further includes an angle determination module configured to:

[0198] The angle between the acute angle formed by the first line and the second line is determined as the reference angle;

[0199] Determine the target angle based on the reference angle; the target angle is smaller than the reference angle.

[0200] In some implementations, the angle determination module is specifically used for:

[0201] The target angle is determined by half of the reference angle.

[0202] In some embodiments, the rotation processing module 330 is also used for:

[0203] The reference line is obtained by rotating the second line counterclockwise by the target angle and then translating it.

[0204] In some embodiments, the rotation processing module 330 is further used for:

[0205] Rotate the first straight line clockwise by the target angle and then translate it vertically until the reference straight line does not intersect with the edge contour to obtain the reference straight line;

[0206] The second straight line is rotated clockwise by the target angle and then translated horizontally until the reference straight line does not intersect with the edge contour, thus obtaining the reference straight line.

[0207] In some implementations, the interception module 340 is specifically used for:

[0208] With the target position as the center, the contours on both sides of the target position in the edge contour are smoothed to obtain the smoothed third and fourth contours.

[0209] The third and fourth contours are cut off according to the preset cutting distance to obtain the cut contours.

[0210] In some implementations, the interception module 340 is further used for:

[0211] The contour to the left of the target position is smoothed by first-order processing to obtain the third contour;

[0212] The fourth contour is obtained by performing second-order smoothing on the contour to the right of the target position.

[0213] In some implementations, the contour acquisition module 310 is specifically used for:

[0214] Obtain a cross-sectional view of the silicon wafer to be evaluated in the width direction;

[0215] The cross-sectional image is binarized, and the binarized cross-sectional image is then subjected to contour extraction to obtain the edge contour.

[0216] In some embodiments, the contour acquisition module 310 is further used for:

[0217] The binarized cross-sectional image is subjected to contour extraction processing to obtain the initial edge contour in the pixel coordinate system;

[0218] The initial edge contour is subjected to subpixel correction processing, and the initial edge contour after subpixel correction processing is transformed to the dimension coordinate system to obtain the edge contour.

[0219] In some embodiments, the contour acquisition module 310 is further used for:

[0220] If discontinuous points are detected in the initial edge contour, multiple edge sub-contours are determined from the initial edge contour based on the discontinuous points.

[0221] The edge sub-contour with the largest contour length among multiple edge sub-contours is determined as the initial edge sub-contour;

[0222] If the initial edge sub-contour is determined to include the contour corresponding to the main surface and the contour corresponding to the chamfered surface, then the initial edge sub-contour is determined as the target edge sub-contour, and sub-pixel correction processing is performed on the target edge sub-contour.

[0223] In some embodiments, the contour acquisition module 310 is further used for:

[0224] The initial edge contour after subpixel correction is encrypted.

[0225] In some implementations, the initial edge contour after subpixel correction is subjected to data encryption processing, including:

[0226] A specified number of pixels are inserted between every two adjacent pixels in the initial edge contour after subpixel correction.

[0227] In some embodiments, the contour acquisition module 310 is further used for:

[0228] Apply Gaussian smoothing to the cross-sectional image.

[0229] In some embodiments, the contour acquisition module 310 is further used for:

[0230] The initial edge contour after subpixel correction is transformed to the size coordinate system to obtain the transformed initial edge contour;

[0231] The initial edge contour after conversion is homogenized to obtain the edge contour.

[0232] In some embodiments, the contour acquisition module 310 is further used for:

[0233] The horizontal distance between any two adjacent data points in the converted initial edge contour is adjusted to a specified distance to obtain the edge contour.

[0234] Figure 17 The diagram shown is a block diagram of a silicon wafer manufacturing apparatus according to an embodiment of the present invention. Figure 17 As shown, the silicon wafer manufacturing apparatus 400 may include:

[0235] Image acquisition module 410 is used to acquire a target cross-sectional view of the width direction of the manufactured silicon wafer.

[0236] Evaluation module 420 is used to evaluate the target cross-sectional image using the silicon wafer evaluation method described above, and obtain the evaluation result corresponding to the target cross-sectional image.

[0237] The process adjustment module 430 is used to adjust the process parameters of the manufacturing process corresponding to the manufactured silicon wafer according to the evaluation results corresponding to the target cross-sectional diagram if the evaluation results do not meet the preset manufacturing requirements, so as to manufacture the silicon wafer based on the adjusted manufacturing process.

[0238] The specific implementation process of the functions and roles of each module in the above-mentioned device can be found in the implementation process of the corresponding steps of the silicon wafer evaluation method in the above embodiments, and will not be repeated here.

[0239] Figure 18 The diagram shown is a block diagram of an electronic device 500 provided in an embodiment of the present invention.

[0240] Reference Figure 18 The electronic device 500 includes a processing component 510, which further includes one or more processors, and memory resources represented by memory 520 for storing instructions, such as application programs, that can be executed by the processing component 510. The application programs stored in memory 520 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 510 is configured to execute instructions to perform the aforementioned silicon wafer evaluation method.

[0241] Electronic device 500 may also include a power supply component configured to perform power management of electronic device 500, a wired or wireless network interface configured to connect electronic device 500 to a network, and an input / output (I / O) interface. Electronic device 500 may operate on an operating system stored in memory 520, such as Windows Server™, Mac OSX™, Unix™, Linux™, FreeBSD™, or similar.

[0242] A non-transitory computer-readable storage medium, wherein when the instructions in the storage medium are executed by the processor of the aforementioned electronic device 500, the electronic device 500 is able to perform the aforementioned silicon wafer evaluation method.

[0243] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0244] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0245] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0246] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0247] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0248] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program verification codes.

[0249] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.

[0250] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.

[0251] It should be understood that the terms "first," "second," etc., mentioned in the embodiments of the present invention are merely for the purpose of more clearly describing the use of the technical solutions in the embodiments of the present invention, and are not intended to limit the scope of protection of the present invention.

[0252] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for evaluating a silicon wafer, characterized by, include: Obtain the edge contour of the silicon wafer to be evaluated, the edge contour including a first contour corresponding to the main surface of the silicon wafer to be evaluated; the edge contour also includes a second contour corresponding to the chamfered surface of the silicon wafer to be evaluated, the chamfered surface being adjacent to the main surface; The first contour is fitted with a straight line to obtain a first straight line, and the second contour is fitted with a straight line to obtain a second straight line. The angle between the acute angle formed by the first line and the second line is determined as the reference angle; The target angle is determined as half of the reference angle. The reference line is obtained by rotating the first straight line clockwise by the target angle and then translating it vertically until the reference line does not intersect with the edge contour. Alternatively, the reference line is obtained by rotating the second straight line clockwise by the target angle and then translating it horizontally until the reference line does not intersect with the edge contour. The position closest to the reference line in the edge contour is determined as the target position, and the contours on both sides of the target position in the edge contour are smoothed with the target position as the center to obtain the smoothed third contour and fourth contour. The third and fourth contours are cut off according to the preset cutting distance to obtain the cut contours; The extracted contour is subjected to circle fitting to obtain a fitted circle, and the evaluation result is determined based on the radius of the fitted circle. The evaluation result is used to evaluate the edge shape of the thickness direction section of the silicon wafer to be evaluated.

2. The method of claim 1, wherein, The step of smoothing the contours on both sides of the target position in the edge contour with the target position as the center to obtain the smoothed third contour and fourth contour includes: The contour to the left of the target position is smoothed by first-order processing to obtain the third contour; The fourth contour is obtained by performing second-order smoothing on the contour to the right of the target position.

3. The method according to claim 1 or 2, characterized in that, The process of obtaining the edge contour of the silicon wafer to be evaluated includes: Obtain a cross-sectional view of the silicon wafer to be evaluated in the width direction; The cross-sectional image is binarized, and the binarized cross-sectional image is then subjected to contour extraction to obtain the edge contour.

4. The method of claim 3, wherein, The process of extracting the contour from the binarized cross-sectional image to obtain the edge contour includes: The binarized cross-sectional image is subjected to contour extraction processing to obtain the initial edge contour in the pixel coordinate system; The initial edge contour is subjected to subpixel correction processing, and the initial edge contour after subpixel correction processing is transformed to the size coordinate system to obtain the edge contour.

5. The method of claim 4, wherein, The sub-pixel correction process for the initial edge contour includes: If discontinuous points are detected in the initial edge contour, then multiple edge sub-contours are determined from the initial edge contour based on the discontinuous points; The edge sub-contour with the largest contour length among the plurality of edge sub-contours is determined as the initial edge sub-contour; If it is determined that the initial edge sub-contour includes the contour corresponding to the main surface and the contour corresponding to the chamfered surface, then the initial edge sub-contour is determined as the target edge sub-contour, and sub-pixel correction processing is performed on the target edge sub-contour.

6. The method of claim 5, wherein, Before transforming the initial edge contour after subpixel correction processing to a size coordinate system to obtain the edge contour, the method further includes: The initial edge contour after the subpixel correction process is then encrypted.

7. The method of claim 6, wherein, The step of encrypting the initial edge contour after sub-pixel correction includes: A specified number of pixels are inserted between every two adjacent pixels in the initial edge contour after the subpixel correction process.

8. The method of claim 3, wherein, Before performing binarization processing on the cross-sectional view, the method further includes: The cross-sectional image is then subjected to Gaussian smoothing.

9. The method according to claim 3, characterized in that, Transforming the initial edge contour after subpixel correction processing to a size coordinate system to obtain the edge contour includes: The initial edge contour after subpixel correction is transformed to the size coordinate system to obtain the transformed initial edge contour; The transformed initial edge contour is homogenized to obtain the edge contour.

10. The method of claim 9, wherein, The process of homogenizing the converted initial edge contour to obtain the edge contour includes: The horizontal distance between any two adjacent data points in the converted initial edge contour is adjusted to a specified distance to obtain the edge contour.

11. A method of manufacturing a silicon wafer, characterized by, include: Obtain a target cross-sectional view of the fabricated silicon wafer in the width direction; The target cross-sectional image is evaluated using the silicon wafer evaluation method as described in any one of claims 1 to 10 to obtain the evaluation result corresponding to the target cross-sectional image. If the evaluation result does not meet the preset manufacturing requirements, the process parameters of the manufacturing process corresponding to the manufactured silicon wafer are adjusted according to the evaluation result corresponding to the target cross-sectional diagram, so as to manufacture the silicon wafer based on the adjusted manufacturing process.

12. A silicon wafer manufacturing apparatus characterized by comprising: include: The image acquisition module is used to acquire a target cross-sectional view of the manufactured silicon wafer in the width direction; The evaluation module is used to evaluate the target cross-sectional view using the silicon wafer evaluation method as described in any one of claims 1 to 10, and obtain the evaluation result corresponding to the target cross-sectional view. The process adjustment module is used to adjust the process parameters of the manufacturing process corresponding to the manufactured silicon wafer according to the evaluation result corresponding to the target cross-sectional diagram if the evaluation result does not meet the preset manufacturing requirements, so as to manufacture the silicon wafer based on the adjusted manufacturing process.

13. A computer-readable storage medium having stored thereon computer- executable instructions, wherein, When the executable instructions are executed by the processor, they implement the silicon wafer evaluation method as described in any one of claims 1 to 10.

14. An electronic device, comprising: The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is used to execute the silicon wafer evaluation method according to any one of claims 1 to 10.

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