An exception handling method and related device

Abstract

The application discloses an abnormality processing method and related equipment, comprising: an upper computer acquires a control signal sent by a lower computer to a semiconductor process equipment, the control signal is used for controlling the semiconductor process equipment to execute corresponding operation, according to the correspondence between the pre-stored abnormality trigger signal and the preset abnormality, it is determined whether the control signal is the abnormality trigger signal corresponding to any preset abnormality, if the control signal is the abnormality trigger signal corresponding to any preset abnormality, the abnormality trigger operation corresponding to the preset abnormality is executed, so that the lower computer is in the abnormality scene corresponding to the preset abnormality, and the abnormality scene is processed, so that the automatic test of the abnormality processing capability of the lower computer is carried out.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to an anomaly handling method and related equipment. Background Technology

[0002] In the process of developing software for the lower-level control unit of semiconductor process equipment, it is crucial to focus not only on its ability to control the process flow but also on its ability to handle anomalies. These anomalies can range from abnormal process temperatures, pressures, or gas flow rates exceeding normal limits to equipment malfunctions. If the lower-level control unit cannot handle these anomalies promptly, it can lead to production accidents and quality problems, and may even pose hazards to personnel and the environment. Therefore, testing and improving the anomaly handling capabilities of the lower-level control unit has become a key focus for software developers working on semiconductor process equipment. Summary of the Invention

[0003] This invention discloses an anomaly handling method and related equipment for automatically testing the anomaly handling capability of the lower-level machine of semiconductor process equipment.

[0004] In a first aspect, the present invention discloses an exception handling method, which is applied to a host computer of a semiconductor process equipment. The exception handling method includes: acquiring a control signal sent by a slave computer of the semiconductor process equipment to the semiconductor process equipment; the control signal being used to control the semiconductor process equipment to perform a corresponding operation; determining whether the control signal is an exception trigger signal corresponding to any preset exception based on a pre-stored correspondence between exception trigger signals and preset exceptions; if the control signal is an exception trigger signal corresponding to any preset exception, then executing an exception trigger operation corresponding to the preset exception, so that the slave computer is in an exception scenario corresponding to the preset exception, and processing the exception scenario.

[0005] In some embodiments, the execution of the exception triggering operation corresponding to the preset exception includes: performing an operation to modify the value of the control signal sent by the lower-level machine to the semiconductor process equipment to a first exception value corresponding to the preset exception, so that the lower-level machine is in a lower-level machine exception scenario corresponding to the first exception value.

[0006] In some embodiments, the execution of the exception triggering operation corresponding to the preset exception includes: performing an operation to modify the value of the signal fed back to the lower-level machine by the semiconductor process equipment in response to the control signal to a second exception value corresponding to the preset exception, so that the lower-level machine is in a semiconductor process equipment exception scenario corresponding to the second exception value.

[0007] In some embodiments, after obtaining the control signal sent by the lower-level machine of the semiconductor process equipment to the semiconductor process equipment, the method further includes: determining whether the current value of the control signal is the same as its historical value; if they are different, determining whether the control signal is an abnormal trigger signal corresponding to any preset abnormality based on the pre-stored correspondence between abnormal trigger signals and preset abnormalities.

[0008] In some embodiments, determining whether the control signal is an abnormal trigger signal corresponding to any preset abnormality based on the pre-stored correspondence between abnormal trigger signals and preset abnormalities includes: if the current value of the control signal is the same as the preset expected value of any preset abnormality in the pre-stored correspondence between abnormal trigger signals and preset abnormalities, and the signal identifier of the control signal is the same as the signal identifier of the abnormal trigger signal corresponding to the preset abnormality, then the control signal is determined to be an abnormal trigger signal corresponding to the preset abnormality.

[0009] In some embodiments, the method further includes: obtaining the processing result of the lower-level machine for any of the preset abnormal scenarios.

[0010] Secondly, the present invention discloses an exception handling method, which is applied to the lower-level machine of the semiconductor process equipment. The exception handling method includes: sending a control signal sent to the semiconductor process equipment to the upper-level machine of the semiconductor process equipment, so that the upper-level machine determines whether the control signal is an exception trigger signal corresponding to any preset exception based on a pre-stored correspondence between exception trigger signals and preset exceptions; the control signal is used to control the semiconductor process equipment to perform corresponding operations; if the control signal is an exception trigger signal corresponding to any preset exception, in response to the exception trigger operation corresponding to the preset exception performed by the upper-level machine, the equipment is placed in an exception scenario corresponding to the preset exception, and the exception scenario is processed.

[0011] In some embodiments, the abnormal scenario corresponding to the preset abnormality, which is triggered by the host computer, includes: in response to the host computer's operation of modifying the value of the control signal sent by the slave device to the semiconductor process equipment to a first abnormal value corresponding to the preset abnormality, the slave device is in an abnormal scenario corresponding to the first abnormal value.

[0012] In some embodiments, the abnormal scenario corresponding to the preset abnormality, which is triggered by the host computer, includes: modifying the value of the signal fed back to the slave computer by the semiconductor process equipment in response to the control signal to the slave computer to a second abnormal value corresponding to the preset abnormality, which is executed by the host computer, and being in an abnormal scenario of the semiconductor process equipment corresponding to the second abnormal value.

[0013] In some embodiments, the method further includes sending the processing result of the abnormal scenario corresponding to any of the preset abnormalities to the host computer.

[0014] Thirdly, the present invention discloses a host computer for semiconductor process equipment, including a memory and a processor; the memory is used to store a computer program; the processor is used to execute the exception handling method as described in any of the preceding claims according to the computer program stored in the memory.

[0015] Fourthly, the present invention discloses a lower-level machine for a semiconductor process apparatus, comprising a memory and a processor; the memory is used to store a computer program; the processor is used to execute the exception handling method described in any of the preceding claims according to the computer program stored in the memory.

[0016] Fifthly, the present invention discloses a computer-readable storage medium on which a computer program is stored, the computer program being executed by a processor to perform the exception handling method as described in any of the preceding claims.

[0017] The present invention discloses an anomaly handling method and related equipment. The host computer obtains the control signal sent by the slave computer to the semiconductor process equipment. Based on the pre-stored correspondence between anomaly trigger signals and preset anomalies, it determines whether the control signal is an anomaly trigger signal corresponding to any preset anomaly. If the control signal is an anomaly trigger signal corresponding to any preset anomaly, the anomaly trigger operation corresponding to the preset anomaly is executed to put the slave computer in an anomaly scenario corresponding to the preset anomaly and process the anomaly scenario. This enables automatic testing of the anomaly handling capability of the slave computer, thereby improving the software development efficiency of the slave computer. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0019] Figure 1 This is a flowchart of an exception handling method disclosed in an embodiment of the present invention.

[0020] Figure 2This is a flowchart of another exception handling method disclosed in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of a host computer for a semiconductor process equipment disclosed in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] During the testing of the lower-level machine's software, it is necessary to test the lower-level machine's ability to handle anomalies by simulating semiconductor process equipment anomalies. Currently, software developers determine when to simulate an anomaly by viewing the monitoring data displayed by the lower-level machine's interface debugging tools (such as Debugger), and then simulate anomalies by manually modifying the values ​​of the signals fed back to the lower-level machine from the semiconductor process equipment. This places the lower-level machine in the corresponding abnormal scenario, enabling it to handle the simulated anomaly.

[0024] For example, after a software developer discovers that the lower-level machine sends a valve control signal to the semiconductor process equipment to close the valve, it determines that it is the time to simulate a valve malfunction. After the semiconductor process equipment responds to the valve control signal to close the valve and feeds back a valve closure success signal to the lower-level machine, the software developer needs to modify the value of the valve closure success signal to the value of valve closure failure before the lower-level machine uses the valve closure success signal, in order to simulate a valve malfunction.

[0025] However, because the lower-level machine's software runs relatively quickly, while human reaction speed is relatively slow, software developers often miss the optimal time to simulate anomalies and make manual modifications, leading to unsuccessful anomaly simulation and impacting the lower-level machine's software development efficiency. Furthermore, human error can also cause modification mistakes, further affecting the lower-level machine's software development efficiency.

[0026] Based on this, the present invention discloses an exception handling scheme in which the host computer of the semiconductor process equipment determines the timing of the simulated exception and executes the exception triggering operation of the simulated exception, so as to improve the software development efficiency of the lower computer.

[0027] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses an exception handling method applied to the host computer of the semiconductor process equipment. This exception handling method is used to test the exception handling capability of the slave computer of the semiconductor process equipment. Figure 1 As shown, Figure 1 This is a flowchart of an exception handling method disclosed in an embodiment of the present invention. The method includes:

[0028] S101: Obtain the control signals sent to the semiconductor process equipment by the lower-level machine.

[0029] In this embodiment of the invention, the semiconductor process equipment includes, but is not limited to, equipment for performing processes such as etching or deposition on wafers. The lower-level machine of the semiconductor process equipment includes at least a transfer module control (TMC) and a process module control (PMC). The transfer module control is used to control the transfer of the robotic arm within the semiconductor process equipment, and the process module control is used to control the processes within the process chambers of the semiconductor process equipment.

[0030] The control signals are used to control semiconductor process equipment to perform corresponding operations. For example, the control signal can be a control signal sent from the transfer controller to the robot to control the robot to perform operations such as transferring wafers. The control signal can also be a control signal sent from the process controller to the process chamber to control the process chamber to perform operations such as adjusting the process gas flow rate or the process temperature. Specifically, the process gas flow rate in the process chamber can be adjusted by regulating the opening of the valve controlling the process gas flow rate within the process chamber using the control signal; the process temperature in the process chamber can be adjusted by regulating the power of the heating devices within the process chamber using the control signal.

[0031] In some embodiments, the host computer can be a lower-level interface debugging tool, which can be an interface debugging tool based on IAP (Industrial Automation Package) running on the Linux operating system. This tool can acquire control signals using the subscription mechanism provided by IAP. However, the invention is not limited to this. In other embodiments, the host computer can be a computer device that interacts with semiconductor process equipment and sends task instructions such as processing or transmission to the lower-level computer based on the interaction results.

[0032] S102: Based on the pre-stored correspondence between abnormal trigger signals and preset abnormalities, determine whether the control signal is an abnormal trigger signal corresponding to any preset abnormality.

[0033] In this embodiment of the invention, the abnormality to be simulated, i.e., the preset abnormality, can be preset. A correspondence between the abnormality triggering signal and the preset abnormality can be preset, and the correspondence between the abnormality triggering signal and the preset abnormality can be preset and stored in the host computer. For example, a mapping table between the abnormality triggering signal and the preset abnormality can be preset and stored. The abnormality triggering signal is the signal that triggers the corresponding preset abnormality.

[0034] Based on this, after the host computer receives the control signal sent to the semiconductor process equipment by the slave computer, it can determine whether the control signal is an exception trigger signal corresponding to any preset exception based on the pre-stored correspondence between exception trigger signals and preset exceptions. In other words, the host computer determines whether it is time to simulate any preset exception by determining whether the control signal is an exception trigger signal corresponding to any preset exception.

[0035] Among these features, exceptions can be preset according to the testing requirements of the lower-level machine. Furthermore, multiple exceptions can be preset to test the exception handling capability of the lower-level machine, that is, the correspondence between multiple exception trigger signals and multiple preset exceptions can be stored in advance.

[0036] S103: If the control signal is an exception trigger signal corresponding to any preset exception, then execute the exception trigger operation corresponding to the preset exception to put the lower-level machine into the exception scenario corresponding to the preset exception and process the exception scenario.

[0037] If the control signal is an exception trigger signal corresponding to any preset exception, the host computer executes the exception trigger operation corresponding to the preset exception. That is, the host computer performs an operation simulating the preset exception to put the slave computer in the exception scenario corresponding to the preset exception and processes the exception scenario to test the slave computer's exception handling capability. If the control signal is not an exception trigger signal corresponding to any preset exception, the host computer does not execute the exception trigger operation.

[0038] Since the determination of whether the control signal is an exception trigger signal corresponding to any preset exception and the execution of the exception trigger operation corresponding to the preset exception are both performed by the host computer, that is, the determination of whether it is the right time to simulate any preset exception and the operation of simulating the preset exception are both performed by the host computer, it is faster and more accurate than manually determining the timing and executing the operation of simulating the exception. Therefore, it can realize the automatic testing of the exception handling capability of the lower computer, thereby improving the software development efficiency of the lower computer.

[0039] In some embodiments, performing an exception triggering operation corresponding to a preset exception includes: performing an operation to modify the value of a signal fed back to the lower-level machine by the semiconductor process equipment in response to a control signal to a second exception value corresponding to a preset exception, so that the lower-level machine is in a semiconductor process equipment exception scenario corresponding to the second exception value.

[0040] Taking a valve control signal sent from a lower-level machine to a semiconductor process equipment to close a valve as an example, this valve can be a valve controlling the gas flow rate within the process chamber. When the lower-level machine sends the valve control signal to the semiconductor process equipment, the upper-level machine also receives this valve control signal and, based on the pre-stored correspondence between abnormal trigger signals and preset abnormalities, determines that the valve control signal is the abnormal trigger signal corresponding to a preset valve abnormality. The semiconductor process equipment responds to this valve control signal by closing the valve and sends a signal indicating successful valve closure back to the lower-level machine. The upper-level machine then modifies the value of the signal indicating successful valve closure to a value indicating failed valve closure, thus placing the lower-level machine in a semiconductor process equipment abnormality scenario. This allows the lower-level machine to process the abnormal scenario and test its ability to handle valve abnormalities. The value indicating failed valve closure is the second abnormal value corresponding to the preset valve abnormality.

[0041] Assuming that a signal value of "1" from the semiconductor process equipment to the lower-level machine indicates that the valve has closed successfully, and a signal value of "0" indicates that the valve has failed to close, the upper-level machine can change the value of the signal indicating that the valve has closed successfully to the value indicating that the valve has failed to close by changing the value of the signal from "1" to "0".

[0042] It should be noted that the signal that the semiconductor process equipment feeds back to the lower-level computer in response to the control signal can be a single signal (such as a signal indicating that the valve failed to close) or multiple signals (such as a signal indicating that the valve failed to close and a gas pressure signal in the process chamber). The upper-level computer can modify the value of one or more signals that the semiconductor process equipment feeds back to the lower-level computer in response to the control signal to put the lower-level computer into the corresponding abnormal scenario of the semiconductor process equipment.

[0043] It is understandable that the above-mentioned abnormal triggering operation simulates the abnormal situation of semiconductor process equipment. However, in actual applications, there may also be abnormal situations of the lower-level machine, such as abnormal control signals sent by the lower-level machine to the semiconductor process equipment. Therefore, lower-level machine abnormalities can also be simulated to test the abnormal handling capability of the lower-level machine.

[0044] Based on this, in some other embodiments, performing the exception triggering operation corresponding to the preset exception includes: performing an operation to modify the value of the control signal sent by the lower-level machine to the semiconductor process equipment to a first exception value corresponding to the preset exception, so that the lower-level machine is in a lower-level machine exception scenario corresponding to the first exception value.

[0045] Taking the example of a valve control signal sent from the lower-level machine to the semiconductor process equipment to close a valve, the upper-level machine first acquires the valve control signal and determines, based on the pre-stored correspondence between abnormal trigger signals and preset abnormalities, that the valve control signal to close the valve corresponds to a preset valve abnormality. Then, the upper-level machine modifies the value of the valve control signal to close the valve to open the valve, ensuring that the control signal sent from the lower-level machine to the semiconductor process equipment is the valve control signal to open the valve. The semiconductor process equipment responds to this valve control signal by opening the valve and sends a successful valve opening signal back to the lower-level machine. The feedback signal received by the lower-level machine is now the valve-open signal. At this point, the lower-level machine is in a scenario where the valve control signal is abnormal, allowing it to process this abnormal scenario and test its ability to handle such abnormalities. The value of the valve control signal to open the valve is the first abnormal value corresponding to the preset valve control signal abnormality.

[0046] Assuming that a valve control signal value of "0" indicates that the valve is closed, and a valve control signal value of "1" indicates that the valve is open, the host computer can change the value of the valve control signal from "0" to "1" to change the value of the valve control signal from closed to open.

[0047] Understandably, if the lower-level machine cannot distinguish between valve malfunction and valve control signal malfunction, it can handle valve malfunction and valve control signal malfunction sequentially, which will not be elaborated here.

[0048] In some embodiments of the present invention, after acquiring a control signal, the host computer compares the current value of the control signal with a historical value, where the historical value is the value of the control signal last acquired by the host computer. If the current value of the control signal is different from the historical value, the host computer determines whether the control signal is an exception trigger signal corresponding to any preset exception based on a pre-stored correspondence between exception trigger signals and preset exceptions. If the current value of the control signal is the same as the historical value, the host computer does not perform the operation of determining whether the control signal is an exception trigger signal corresponding to any preset exception. The host computer can acquire the control signal according to a preset frequency or a preset time interval.

[0049] Of course, the present invention is not limited to this. In other embodiments, after the host computer obtains the control signal, it can directly perform the operation of determining whether the control signal is an abnormal trigger signal corresponding to any preset abnormality. This will not be elaborated here.

[0050] In some embodiments of the present invention, if the current value of the control signal is the same as the preset signal value of the abnormal trigger signal corresponding to any preset abnormality in the pre-stored correspondence between abnormal trigger signals and preset abnormalities, and the signal identifier of the control signal is the same as the signal identifier of the abnormal trigger signal, then the control signal is determined to be the abnormal trigger signal corresponding to the preset abnormality.

[0051] If the signal identifier and current value of the control signal are different from the signal identifier and preset signal value of the abnormal trigger signal corresponding to any preset abnormality, then the control signal is not the abnormal trigger signal corresponding to any preset abnormality.

[0052] Understandably, each preset anomaly corresponds to an anomaly trigger signal, and each anomaly trigger signal corresponds to a signal identifier and a preset signal value. The signal identifier of the anomaly trigger signal can be its signal name, and the preset signal value can be the expected signal value for that preset anomaly. Therefore, after acquiring a control signal, the host computer can compare the signal identifier of the control signal with the signal identifier of the anomaly trigger signal, and compare the current value of the control signal with the preset signal value of the anomaly trigger signal to determine whether the control signal is the anomaly trigger signal for any preset anomaly.

[0053] Taking the valve control signal sent by the lower-level machine to the semiconductor process equipment to close the valve as an example, let's assume that the value of the valve control signal is "0" to indicate that the valve is closed, and the value of the valve control signal is "1" to indicate that the valve is opened. The preset valve abnormality corresponding to the abnormality trigger signal is the valve control signal with a value of "0". When the value of the valve control signal is "1", the upper-level machine will not be triggered to perform the simulated preset valve abnormality abnormality trigger operation. When the value of the valve control signal is "0", the upper-level machine will be triggered to perform the simulated preset valve abnormality abnormality trigger operation.

[0054] In some embodiments of the present invention, the lower-level computer and the semiconductor process equipment have multiple I / O (Input / Output) channels. These I / O channels are used to realize information interaction between the lower-level computer and the semiconductor process equipment. Specifically, control signals sent by the lower-level computer to the semiconductor process equipment can be obtained by acquiring the signals of the I / O channels between the lower-level computer and the semiconductor process equipment. An abnormal scenario of the semiconductor process equipment can be simulated by modifying the value of the I / O channel signal fed back to the lower-level computer in response to the control signal to a preset second abnormal value. Of course, in other embodiments, the lower-level computer can also interact with the semiconductor process equipment through other types of channels, which will not be elaborated here.

[0055] In some embodiments of the present invention, after performing the exception triggering operation corresponding to the preset exception, the method further includes: obtaining the processing result of the lower-level machine for any exception scenario corresponding to the preset exception.

[0056] In some embodiments, after the host computer executes an exception triggering operation corresponding to any preset exception, it determines whether the slave computer is in an exception scenario corresponding to the preset exception. If it is not in an exception scenario corresponding to the preset exception, it indicates that the exception triggering operation has failed and the process continues. If it is in an exception scenario corresponding to the preset exception, it obtains the processing result of the slave computer for the exception scenario corresponding to the preset exception and determines whether the slave computer can handle the exception based on the processing result. If it can handle the exception, the process continues after the slave computer handles the exception. If it cannot handle the exception, it outputs the result of the process exception.

[0057] Based on this, the host computer can determine the lower-level machine's exception handling capabilities by analyzing the lower-level machine's handling results for all preset exception scenarios. Based on these capabilities, the host computer can then determine whether to improve the lower-level machine's software to enhance software quality and reduce the impact of exceptions on semiconductor process equipment. Furthermore, the host computer can display the lower-level machine's exception handling results to software developers, enabling them to assess the lower-level machine's exception handling capabilities and determine whether software improvements are necessary.

[0058] As another optional implementation of the disclosed content of this invention, this embodiment also discloses an exception handling method applied to a lower-level machine of semiconductor process equipment. This lower-level machine is used to control the process flow of the semiconductor process equipment, etc. Figure 2 As shown, Figure 2 This is a flowchart of an exception handling method disclosed in an embodiment of the present invention. The method includes:

[0059] S201: Send the control signal sent to the semiconductor process equipment to the host computer of the semiconductor process equipment, so that the host computer can determine whether the control signal is an abnormal trigger signal corresponding to any preset abnormality based on the correspondence between the pre-stored abnormal trigger signal and the preset abnormality.

[0060] During the testing of the lower-level machine, it can send control signals intended for the semiconductor process equipment to the upper-level machine. The upper-level machine then determines whether the control signal corresponds to any preset exception based on a pre-stored mapping between exception trigger signals and preset exceptions. These control signals are used to control the semiconductor process equipment to perform corresponding operations, such as controlling a robotic arm to transfer wafers or controlling the gas flow or temperature within the process chamber.

[0061] S202: If the control signal is an exception trigger signal corresponding to any preset exception, respond to the exception trigger operation corresponding to the preset exception executed by the host computer, be in the exception scenario corresponding to the preset exception, and process the exception scenario.

[0062] If the control signal is an exception trigger signal corresponding to any preset exception, the host computer executes the exception trigger operation corresponding to the preset exception, that is, the host computer performs an operation simulating the preset exception. The slave computer responds to the exception trigger operation executed by the host computer, enters the exception scenario corresponding to the preset exception, and processes the exception scenario. Based on this, the exception handling capability of the slave computer can be tested. If the slave computer can handle the exception scenario, the process continues; if the slave computer cannot handle the exception scenario, the host computer outputs the result of the process exception.

[0063] Since the determination of whether the control signal is an exception trigger signal corresponding to any preset exception and the execution of the exception trigger operation corresponding to the preset exception are both performed by the host computer, that is, the determination of whether it is the right time to simulate any preset exception and the operation of simulating the preset exception are both performed by the host computer, it is faster and more accurate than manually determining the timing and executing the operation of simulating the exception. Therefore, it can realize the automatic testing of the exception handling capability of the lower computer, thereby improving the software development efficiency of the lower computer.

[0064] In some embodiments of the present invention, in response to an exception triggering operation performed by the host computer corresponding to a preset exception, being in an exception scenario corresponding to the preset exception includes: in response to an operation performed by the host computer to modify the value of the control signal sent by the lower-level machine to the semiconductor process equipment to a first exception value corresponding to the preset exception, being in a lower-level machine exception scenario corresponding to the first exception value.

[0065] Taking the example of a valve control signal sent by the lower-level machine to the semiconductor process equipment to close the valve, after the upper-level machine performs the operation of modifying the value of the valve control signal to open the valve, the lower-level machine obtains the signal fed back by the semiconductor process equipment in response to the valve control signal to close the valve, which is a valve opening signal. In this case, the lower-level machine is in a lower-level machine abnormal scenario where the valve control signal is abnormal, and the lower-level machine will handle the abnormal scenario of the valve control signal abnormality.

[0066] Of course, the present invention is not limited to this. In other embodiments, in response to the exception triggering operation corresponding to the preset exception executed by the host computer, being in the abnormal scenario corresponding to the preset exception includes: in response to the operation executed by the host computer to modify the value of the signal fed back to the lower computer by the semiconductor process equipment in response to the control signal to the lower computer to a second abnormal value corresponding to the preset exception, being in the abnormal scenario of the semiconductor process equipment corresponding to the second abnormal value.

[0067] Taking the valve control signal sent by the lower-level machine to the semiconductor process equipment to close the valve as an example, after the upper-level machine performs the operation of changing the value of the signal indicating that the valve closed successfully to the value indicating that the valve closed failed, the lower-level machine obtains the signal fed back by the semiconductor process equipment in response to the valve control signal to close the valve, which is a signal indicating that the valve closed failed. In this case, the lower-level machine is in a semiconductor process equipment abnormality scenario where the valve is abnormal, and the lower-level machine will handle the abnormal scenario of the valve abnormality.

[0068] In some embodiments of the present invention, the lower-level machine will send the processing result of the abnormal scenario corresponding to any preset abnormality to the upper-level machine, so that the upper-level machine can determine the abnormality processing capability of the lower-level machine based on the processing result of the lower-level machine on the abnormal scenarios corresponding to all preset abnormalities.

[0069] As another optional implementation of the disclosure of this invention, embodiments of this invention also disclose a host computer for semiconductor process equipment, such as... Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a host computer for a semiconductor process equipment disclosed in an embodiment of the present invention. The host computer includes a memory and a processor. The memory is used to store computer programs. The processor is used to execute the exception handling method disclosed in any of the above embodiments according to the computer programs stored in the memory.

[0070] As another optional implementation of the disclosure of this invention, this embodiment also discloses a lower-level machine for semiconductor process equipment. The lower-level machine includes a memory and a processor; the memory stores a computer program; the processor executes the exception handling method disclosed in any of the above embodiments according to the computer program stored in the memory. The structure of this lower-level machine can be referred to... Figure 3 This will not be elaborated upon here.

[0071] As another optional implementation of the disclosure of this invention, embodiments of this invention also disclose a computer-readable storage medium storing a computer program. When the computer program is run by a processor, it executes the exception handling method disclosed in any of the above embodiments. The computer-readable storage medium can be the memory of a host computer of a semiconductor process device or the memory of a slave computer of the semiconductor process device. Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0072] As another optional implementation of the disclosure in this application, embodiments of this application also disclose a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor causes the processor to execute the exception handling method for semiconductor process equipment as disclosed in any of the above embodiments.

[0073] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Python and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. An exception handling method, characterized in that, The exception handling method is applied to the host computer of semiconductor process equipment, and the exception handling method includes: The system acquires control signals sent from the lower-level machine of the semiconductor process equipment to the semiconductor process equipment; these control signals are used to control the semiconductor process equipment to perform corresponding operations. Based on the pre-stored correspondence between multiple abnormal trigger signals and multiple preset abnormalities, it is determined whether the control signal is an abnormal trigger signal corresponding to any preset abnormality, so as to determine whether it is the right time to simulate any preset abnormality. If the control signal is an exception trigger signal corresponding to any preset exception, then the exception trigger operation corresponding to the preset exception is executed, so that the lower-level machine is in the exception scenario corresponding to the preset exception, and the exception scenario is processed.

2. The anomaly handling method according to claim 1, characterized in that, The execution of the exception triggering operation corresponding to the preset exception includes: The operation of modifying the value of the control signal sent by the lower-level machine to the semiconductor process equipment to a first abnormal value corresponding to the preset abnormality is performed, so that the lower-level machine is in a lower-level machine abnormal scenario corresponding to the first abnormal value.

3. The anomaly handling method according to claim 1, characterized in that, The execution of the exception triggering operation corresponding to the preset exception includes: The operation of modifying the value of the signal fed back to the lower-level machine by the semiconductor process equipment in response to the control signal to the lower-level machine is performed, so that the lower-level machine is in the semiconductor process equipment abnormal scenario corresponding to the second abnormal value.

4. The anomaly handling method according to claim 1, characterized in that, After obtaining the control signal sent by the lower-level machine of the semiconductor process equipment to the semiconductor process equipment, the method further includes: Determine whether the current value of the control signal is the same as its historical value; If they are different, then based on the pre-stored correspondence between the abnormal trigger signal and the preset abnormality, it is determined whether the control signal is an abnormal trigger signal corresponding to any preset abnormality.

5. The anomaly handling method according to claim 1 or 4, characterized in that, The step of determining whether the control signal is an exception trigger signal corresponding to any preset exception based on the pre-stored correspondence between exception trigger signals and preset exceptions includes: If the current value of the control signal is the same as the preset signal value of the abnormal trigger signal corresponding to any preset abnormality in the pre-stored correspondence between abnormal trigger signals and preset abnormalities, and the signal identifier of the control signal is the same as the signal identifier of the abnormal trigger signal, then the control signal is determined to be the abnormal trigger signal corresponding to the preset abnormality.

6. The anomaly handling method according to claim 1, characterized in that, Also includes: Obtain the processing result of the lower-level machine for any of the preset abnormal scenarios.

7. An exception handling method, characterized in that, The exception handling method is applied to the lower-level machine of semiconductor process equipment, and the exception handling method includes: The control signal sent to the semiconductor process equipment is sent to the host computer of the semiconductor process equipment, so that the host computer determines whether the control signal is an abnormal trigger signal corresponding to any preset abnormality based on the correspondence between multiple pre-stored abnormal trigger signals and multiple preset abnormalities, and determines whether it is the time to simulate any preset abnormality; the control signal is used to control the semiconductor process equipment to perform corresponding operations; If the control signal is an exception trigger signal corresponding to any preset exception, it responds to the exception trigger operation corresponding to the preset exception executed by the host computer, is in an exception scenario corresponding to the preset exception, and processes the exception scenario.

8. The anomaly handling method according to claim 7, characterized in that, The exception triggering operation corresponding to the preset exception executed by the host computer, and the exception scenarios corresponding to the preset exception, include: In response to the operation performed by the host computer to modify the value of the control signal sent by the slave computer to the semiconductor process equipment to a first abnormal value corresponding to the preset abnormality, the slave computer is in an abnormal scenario corresponding to the first abnormal value.

9. The anomaly handling method according to claim 7, characterized in that, The exception triggering operation corresponding to the preset exception executed by the host computer, and the exception scenarios corresponding to the preset exception, include: In response to the operation performed by the host computer to modify the value of the signal fed back to the slave computer by the semiconductor process equipment in response to the control signal to the slave computer to a second abnormal value corresponding to the preset abnormality, the semiconductor process equipment is in an abnormal scenario corresponding to the second abnormal value.

10. The anomaly handling method according to claim 7, characterized in that, Also includes: The processing result of any of the preset abnormal scenarios will be sent to the host computer.

11. A host computer for semiconductor process equipment, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to execute the exception handling method according to any one of claims 1-6, based on the computer program stored in the memory.

12. A lower-level machine for semiconductor process equipment, characterized in that, Including memory and processor; The memory is used to store computer programs; The processor is configured to execute the exception handling method according to any one of claims 7-10, based on the computer program stored in the memory.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the exception handling method as described in any one of claims 1-6 or as described in any one of claims 7-10.

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