Test method of new energy station controller, electronic device and readable storage medium

Abstract

The embodiment of the present application relates to the technical field of power system simulation, and discloses a kind of test method, electronic equipment and readable storage medium of new energy station controller.The present application includes: establishing software test model, for the in-loop test of the software function of controller;Establish hardware test model, for the in-loop test of the hardware function of controller;Hardware test model runs in N simulation circuit;Wherein, N is greater than or equal to 1 integer;Compare the test results of software test model and the waveform of hardware test model;If the comparison result is not in the preset error range, adjust the software test model, until the comparison result is in the preset error range;Synchronize software test model and hardware test model based on the first buffer circuit model.The two running carriers and the model with different simulation step lengths are coupled, so that they can run as a unified, dynamic interactive and stable simulation system.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power system simulation technology, and in particular to testing methods, electronic devices and readable storage media for new energy power station controllers. Background Technology

[0002] The large-scale grid connection of renewable energy power plants places stringent requirements on the high reliability and low latency of controllers. In existing technologies, controller testing primarily relies on two methods: Control Software-in-the-Loop (C-SIL) and Control Hardware-in-the-Loop (C-HIL). C-SIL compiles the controller algorithm code into a virtual controller, which runs directly in the simulation environment for interactive simulation. While C-SIL can quickly verify upper-level control algorithms, it cannot reproduce physical layer issues such as communication packet loss and timing deviations because it does not involve real hardware. C-HIL, on the other hand, connects the real controller hardware to the simulation platform. Although it can accurately test the hardware interfaces and logic of the physical controller, it is limited by the computing power of the simulator and the number of hardware interfaces, making it difficult to scale to large-scale power plant-level collaborative testing involving dozens or even more renewable energy units.

[0003] However, related technologies typically construct test architectures for C-SIL and C-HIL separately. Furthermore, since C-SIL and C-HIL usually run on different chips, there is a time delay during communication between them, making it impossible to effectively combine the field-level control algorithm simulation of the controller with the hardware-level response verification of the controller. Summary of the Invention

[0004] The purpose of this invention is to provide a testing method, electronic device, and readable storage medium for a new energy power station controller, enabling the combination of C-SIL and C-HIL to solve the communication delay problem between the two, thereby effectively combining the simulation of the controller's power station-level control algorithm with the verification of the controller's hardware-level response.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a testing method for a new energy power station controller, comprising: establishing a software test model for performing in-loop testing of the controller's software functions; establishing a hardware test model for performing in-loop testing of the controller's hardware functions; the hardware test model running on N simulation circuits; wherein N is an integer greater than or equal to 1; comparing the test results of the software test model with the waveforms of the hardware test model; if the comparison result is not within a preset error range, adjusting the software test model until the comparison result is within the preset error range; and synchronizing the software test model and the hardware test model based on a first buffer circuit model.

[0006] Embodiments of the present invention also provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the test method for a new energy power station controller as described above.

[0007] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the test method for the new energy power station controller as described above.

[0008] In this embodiment of the invention, firstly, independent software and hardware test models are established, constructing test environments for the controller software algorithm and hardware function, respectively. Then, by comparing the test results of the two models and iteratively adjusting the software model, it is ensured that the software test model can accurately reproduce the behavior of the hardware test model, providing a foundation of effectiveness and consistency for the subsequent combination of the two models. Finally, by utilizing a first buffer circuit model to synchronize the aforementioned software and hardware test models that have been ensured to be consistent, that is, by adjusting the interference and divergence problems caused by the time delay in the decoupling of the software and hardware test models, the two models with different running carriers and simulation step sizes are coupled, enabling them to run as a unified, dynamically interactive, and stable simulation system. This achieves the goal of deep coupling and collaborative operation of the software-in-the-loop test model and the hardware-in-the-loop test model. Furthermore, since the hardware test model is deployed on N simulation circuits, the number of simulation circuits deployed can be selected according to the actual number of hardware controllers, effectively expanding the parallel testing capability of the hardware test model.

[0009] Furthermore, the synchronization of the software test model and the hardware test model based on the first buffer circuit model includes: obtaining the first signal interaction delay between the software test model and the hardware test model; the first signal interaction delay is the duration of one signal interaction between the hardware test model and the software test model; adjusting the first buffer circuit model so that the first signal interaction delay meets a first preset duration, thereby synchronizing the software test model and the hardware test model. In this way, the delay existing in the decoupling of the software and hardware test models can be adjusted through the first buffer circuit model, thereby coupling two operating platforms and models with different simulation step sizes. This achieves dynamic coupling between the millisecond-level simulation step size of the software test model and the microsecond-level simulation step size of the hardware test model, effectively ensuring the high precision and high reliability of the new energy power station controller test.

[0010] Furthermore, N is an integer greater than or equal to 2; after establishing the hardware test model, the process includes: obtaining the second signal interaction delay between every two simulation circuits; adjusting the second buffer circuit model on the simulation circuit so that the second signal interaction delay meets a second preset duration, thereby synchronizing every two simulation circuits. In this way, the second buffer circuit model can be used to adjust the delays existing in the decoupling of the hardware test model on different simulation circuits, thereby coupling the hardware test models of N operating carriers, achieving precise synchronization within the hardware test model, and effectively ensuring high precision and high reliability in the testing of new energy power station controllers.

[0011] Furthermore, the N simulation circuits include one main simulation circuit and N-1 extended simulation circuits, where N is an integer greater than or equal to 2. The establishment of the hardware test model includes: establishing a power grid model and a first NPC model connected to the power grid model on the main simulation circuit, and constructing a second NPC model on each of the extended simulation circuits; incorporating the second NPC models into the power grid model to establish the hardware test model; wherein, the first NPC model is used to receive hardware instructions from the controller through the interface of the main simulation circuit and provide simulated electrical parameters to the controller; the second NPC model is used to receive hardware instructions from the controller through the interface of the extended simulation circuit and provide simulated electrical parameters to the controller. In this way, dividing the N simulation circuits into one main simulation circuit (carrying the power grid model and the first NPC model) and N-1 extended simulation circuits (each carrying a second NPC model) allows for flexible addition or removal of hardware test nodes based on the number of controllers, overcoming the bottlenecks of traditional C-HIL in terms of computing power and the number of interfaces. Furthermore, by incorporating the second NPC model in each extended simulation circuit into the main grid model of the main simulation circuit, a holistic hardware-in-the-loop model can be formed, realizing dynamic coupling testing across circuits and chips, thereby meeting the collaborative testing requirements of new energy power station controllers for controller software and hardware.

[0012] Furthermore, the method also includes: if the waveforms in the test results of the synchronized software test model and the hardware test model are unstable, adjusting the first buffer circuit model until the waveforms stabilize. Due to the synchronization of the software test model and the hardware test model, i.e., the adjustment of the delay between them, the waveforms of electrical quantities in the simulation results may exhibit numerical instability, such as numerical divergence, oscillation, or interference. To address this issue, this application uses a first buffer circuit model to compensate for the system, preventing interference and divergence problems caused by decoupling delays, with the ultimate goal of stabilizing the modeled system. Attached Figure Description

[0013] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0014] Figure 1 This is a flowchart of a test method for a new energy power station controller according to an embodiment of the present invention; Figure 2 This is a flowchart of a test method for a new energy power station controller provided according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a simulation model in a test method for a new energy power station controller provided according to an embodiment of the present invention; Figure 4 This refers to the response time from voltage output to current received by the optical port of the communication interface in the FPGA when the FPGA simulation step size is 210ns, according to a test method for a new energy power station controller provided by an embodiment of the present invention. Figure 5 This refers to the response time from voltage output to current received by the optical port of the communication interface in the FPGA when the FPGA simulation step size is 500ns, according to a test method for a new energy power station controller provided in an embodiment of the present invention. Figure 6 This refers to the response time from voltage output to current received by the optical port of the communication interface in the FPGA when the FPGA simulation step size is 1000ns, according to a test method for a new energy power station controller provided by an embodiment of the present invention. Figure 7 This refers to the response time from voltage output to current received by the optical port of the communication interface in the FPGA when the FPGA simulation step size is 2000ns, according to a test method for a new energy power station controller provided in an embodiment of the present invention. Figure 8 This refers to the response time from voltage output to current received by the optical port of the communication interface in the FPGA when the FPGA simulation step size is 2500ns, according to a test method for a new energy power station controller provided by an embodiment of the present invention. Figure 9 This is a schematic diagram of the test model construction in a test method for a new energy power station controller provided according to an embodiment of the present invention; Figure 10 This is a structural diagram of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0015] With the continuous increase in the grid-connected capacity of numerous new energy units such as wind power, photovoltaics, and energy storage, new energy power plants have evolved from small-scale systems with single units and partial parallel connections to large-scale power clusters of tens or even hundreds of megawatts. Against this backdrop of high penetration and large capacity, power plant controllers must not only cope with rapid fluctuations and power pulsations in new energy output, but also respond to grid frequency disturbances in milliseconds and execute power allocation commands in seconds. Simultaneously, the information exchange, topology reconfiguration, and fault isolation among massive amounts of equipment place higher demands on the bandwidth, latency, and reliability of communication networks and control architectures. Any timing drift, communication jitter, or algorithm decision delay can trigger power imbalances, voltage flicker, or even mass grid disconnection incidents, seriously threatening grid security and stability and the economic benefits of new energy power plants.

[0016] In existing technologies, controller testing primarily relies on two methods: Control Software-in-the-Loop (C-SIL) and Control Hardware-in-the-Loop (C-HIL). The aforementioned large-scale field station-level grid connection requires precise synchronization between the field station-level control algorithm (milliseconds or even seconds) and the hardware response (nanoseconds to microseconds). However, existing C-SIL and C-HIL methods are typically implemented independently and verified separately, lacking cross-level dynamic coupling. This results in the inability to verify the timing matching of controller frequency modulation commands and inverter switching actions in the same test environment, and also makes it impossible to accurately reproduce physical layer timing deviations and fault linkage phenomena caused by communication packet loss, ADC sampling jitter, or PWM dead-time effects.

[0017] Secondly, while pure C-SIL testing can rapidly iterate control algorithms, it does not involve any actual hardware components and therefore cannot simulate cross-level fault propagation scenarios that may occur after field deployment, such as communication interruptions, protection malfunctions, or fault propagation. On the other hand, while pure C-HIL testing can verify the hardware interface and logic of a single controller, it is limited by the computing power of the simulator, FPGA / CPU resources, and the number of interfaces, making it difficult to support parallel and coordinated testing of dozens or even hundreds of new energy units (wind turbines, photovoltaic inverters, energy storage systems, etc.), resulting in high testing costs and limited scalability.

[0018] Furthermore, since C-SIL and C-HIL are usually deployed on different chips (CPU and FPGA), data exchange between them must pass through physical buses such as PCIe or fiber optics. Communication delay is unavoidable and fluctuates significantly, which means that the software model and the hardware model cannot process information at the same moment "simultaneously" within the same simulation step or the same signal cycle. This makes it impossible for the in-loop test system to form real-time and stable closed-loop feedback, and loses the ability to verify multi-time-domain collaborative control strategies (such as black start and frequency / voltage support).

[0019] Finally, from an economic and efficiency perspective, pure C-HIL testing requires each new energy unit to be equipped with an independent hardware controller, which not only results in high hardware resource occupancy and soaring costs and maintenance costs, but also long testing cycles and low iteration efficiency, which seriously restricts the promotion and application of large-scale site-level full life cycle testing.

[0020] Therefore, this invention urgently needs a hybrid real-time simulation architecture that achieves deep coupling on a heterogeneous platform of CPU and FPGA, which can reproduce the timing characteristics and fault propagation of real hardware, and make full use of the high efficiency and scalability of digital models, so as to conduct comprehensive dynamic closed-loop testing of the controller of new energy power plants of GW scale and above while ensuring high reliability and low latency.

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of the present invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0022] One embodiment of the present invention relates to a testing method for a new energy power station controller, which can be applied to terminal equipment such as a host computer. The method includes: establishing a software test model for in-loop testing of the controller's software functions; establishing a hardware test model for in-loop testing of the controller's hardware functions; the hardware test model running on N simulation circuits; where N is an integer greater than or equal to 1; comparing the test results of the software test model with the waveforms of the hardware test model; if the comparison result is not within a preset error range, adjusting the software test model until the comparison result is within the preset error range; and synchronizing the software test model and the hardware test model based on a first buffer circuit model. In this embodiment of the invention, firstly, independent software and hardware test models are established, constructing test environments for the controller software algorithm and hardware function, respectively. Then, by comparing the test results of the two models and iteratively adjusting the software model, it is ensured that the software test model can accurately reproduce the behavior of the hardware test model, providing a foundation of effectiveness and consistency for the subsequent combination of the two models. Finally, by utilizing a first buffer circuit model to synchronize the aforementioned software and hardware test models that have been ensured to be consistent, that is, by adjusting the time delay existing in the decoupling of the software and hardware test models through the first buffer circuit model, the two running carriers and models with different simulation step sizes are coupled, enabling them to run as a unified, dynamically interactive simulation system. This achieves the goal of deep coupling and collaborative operation of the software-in-the-loop test model and the hardware-in-the-loop test model. Furthermore, since the hardware test model is deployed on N simulation circuits, the number of simulation circuits deployed can be selected according to the actual number of hardware controllers, effectively expanding the parallel testing capability of the hardware test model.

[0023] The following is a detailed description of the implementation details of the testing method for the new energy power station controller according to an embodiment of the present invention. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0024] like Figure 1 As shown, the embodiments of the present invention include steps 110 to 150, as detailed below.

[0025] In step 110, a software test model is established to perform in-loop testing on the software functions of the controller.

[0026] Furthermore, the controller under test described in this application is not limited to a single type, but can cover a variety of new energy power station control equipment, including but not limited to wind power generation controllers (for wind turbine power tracking and pitch control), photovoltaic power generation controllers (for maximum power point tracking and inverter control), energy storage controllers (for battery pack charging and discharging management and energy optimization), static var generators (for reactive power compensation and grid voltage stabilization), and even microgrid energy management controllers, vehicle charging pile controllers, and hydropower regulation controllers.

[0027] In this embodiment of the invention, the software test model constructed by the host computer mainly runs on the CPU part of the simulator.

[0028] In this embodiment of the invention, the host computer mainly builds a software test model on the simulator CPU through the Matlab / Simulink platform: control algorithm modules such as wind power pitch and power tracking, photovoltaic maximum power point tracking and inversion, energy storage charging and discharging management, and reactive power compensation are added in the Simulink environment, and electrical topologies such as circuits are established. The controller source code is compiled and embedded into the algorithm module to form a digital-in-the-loop real-time simulation model.

[0029] In this embodiment of the invention, the simulation step size of the software simulation model is set in the range of 20-100 microseconds. The specific value can be dynamically allocated based on the size of the single unit in the digital-in-the-loop system of the station. That is, the simulation step size can be adjusted by parameters such as the complexity of the single unit control loop during model initialization, the real-time computing load, the computing time of each simulation unit during runtime, and waveform comparison.

[0030] In step 120, a hardware test model is established to perform in-loop testing on the hardware functions of the controller; the hardware test model runs on N simulation circuits; where N is an integer greater than or equal to 1.

[0031] Specifically, the aforementioned N simulation circuits include one main simulation circuit and N-1 extended simulation circuits, where N is an integer greater than or equal to 2. The establishment of the hardware test model includes: establishing a power grid model and a first NPC model connected to the power grid model on the main simulation circuit, and constructing a second NPC model on each of the extended simulation circuits; incorporating the second NPC model into the power grid model to establish the hardware test model; wherein, the first NPC model is used to receive hardware instructions from the controller through the interface of the main simulation circuit and provide simulated electrical parameters to the controller; the second NPC model is used to receive hardware instructions from the controller through the interface of the extended simulation circuit and provide simulated electrical parameters to the controller.

[0032] In this way, the N simulation circuits are divided into one main simulation circuit (carrying the power grid model and the first NPC model) and N-1 extended simulation circuits (each carrying a second NPC model). This allows for flexible addition or removal of hardware test nodes based on the number of controllers, overcoming the bottlenecks of traditional C-HIL in terms of computing power and interface quantity. Furthermore, by incorporating the second NPC models from each extended simulation circuit into the main power grid model of the main simulation circuit, a unified hardware-in-the-loop model can be formed, enabling dynamic coupling testing across circuits and chips. This meets the collaborative testing requirements of new energy power plant controllers for both controller software and hardware.

[0033] In this embodiment of the invention, each of the simulation circuits is connected to up to five of the controllers.

[0034] Those skilled in the art will recognize that there is a physical limit to the number of hardware interfaces on each FPGA simulation circuit: each simulation circuit can provide a maximum of five high-speed differential I / O interfaces for connecting to external controllers, used for functions such as voltage / current acquisition, PWM waveform generation, and status feedback. Therefore, in order to meet the testing needs of more controllers without exceeding this hardware limit, this embodiment of the invention uses a logic method of multiple FPGAs connected in parallel. While strictly adhering to the hardware limit of five interfaces per circuit, it achieves efficient and reliable testing of multiple types and quantities of new energy controllers.

[0035] In an optional embodiment, N is an integer greater than or equal to 2. Following step 120 above, i.e., after establishing the hardware test model, the process includes: obtaining the second signal interaction delay between every two simulation circuits; adjusting the second buffer circuit model on the simulation circuit so that the second signal interaction delay meets a second preset duration, and synchronizing every two simulation circuits.

[0036] Specifically, during the synchronization process of every two simulation circuits, the host computer uses Vivado's integrated logic analysis module to capture packets from the FPGA optical port interface and measure the time delay (i.e., simulation step size) between the "optical port output voltage" and the "received current response" in real time. By comparing the time delay differences of each path, the decoupling delay between different FPGA nodes can be determined. Based on the measured time delay, the host computer adjusts the coupling parameters inside the FPGA, including the encoding / decoding delay of the Aurora communication link, the relay buffer depth, and the transaction priority, and sends the corresponding correction values ​​to the "second buffer circuit model"—a programmable RC delay module built into the decoupling point between the main simulation circuit and each extended simulation circuit. By changing the time constant τ of the resistor R or capacitor C, the signal transmission delay is finely adjusted, so that the arrival time of the two signals matches the preset second synchronization duration.

[0037] In this way, the delays that exist in the decoupling of the hardware test model on different simulation circuits can be adjusted by the second buffer circuit model, thereby coupling the hardware test models of N operating carriers and achieving precise synchronization within the hardware test model, effectively ensuring the high precision and high reliability of the new energy power station controller test.

[0038] In this embodiment of the invention, N is an integer greater than or equal to 2, and every two simulation circuits communicate via an optical fiber interface. Besides the optical fiber solution, this embodiment also supports alternative communication protocols based on Serial RapidIO, Ethernet TSN, or PCIe Gen 4 / 5 optical fiber physical layers to meet different bandwidth, distance, and architecture requirements.

[0039] In this embodiment of the invention, the hardware test model constructed by the host computer mainly runs on the simulation circuit in the simulator, i.e., on the FPGA. The FPGA includes I / O interface modules such as voltage / current acquisition, PWM wave generation, and status feedback.

[0040] In step 130, the test results of the software test model are compared with the waveforms of the hardware test model; In step 140, if the comparison result is not within the preset error range, the software test model is adjusted until the comparison result is within the preset error range.

[0041] It should be noted that steps 130 and 140 above are mainly for constructing a software model that is consistent with the waveform of the hardware test model. For specific instructions, please refer to [link / reference needed]. Figure 2 Specifically, the host computer, based on the RT-LAB real-time simulator, constructed a process for embedding new energy control code into the simulator: First, the host computer modifies the new energy control source code to conform to compilation specifications. Then, in the RT-LAB real-time simulator, it sequentially executes the compilation and packaging operations of "source code → .o object file → .a library file." During the "source code → .o object file" process, if compilation fails, the source code is modified again until compilation succeeds. Subsequently, the .a library is deployed to the target machine and the output of the software-in-the-loop test is obtained. The waveforms of this software-in-the-loop test are compared for consistency. If they do not match, the process loops back to the source code modification stage. If they match, the verified .a library is encrypted and saved, laying the foundation for subsequent CSIL verification.

[0042] In addition, to further automate and improve the reliability of the above algorithm compilation process, the host computer also integrates a waveform diagnostic submodule, which synchronously compares amplitude deviation, phase difference, and harmonic content through least squares method and frequency domain analysis, and subdivides the preset error threshold into multiple levels to adapt to the performance characteristics of different controllers such as wind power, photovoltaic, energy storage, and SVG; finally, the verified .a library file is signed by a hardware encryption engine and stored in a protected version management system to ensure the consistency and IP security of subsequent CSIL deployment.

[0043] In step 150, the software test model and the hardware test model are synchronized based on the first buffer circuit model.

[0044] Specifically, the step of synchronizing the software test model and the hardware test model based on the first buffer circuit model includes: obtaining a first signal interaction delay between the software test model and the hardware test model; the first signal interaction delay is the duration of one signal interaction between the hardware test model and the software test model; adjusting the first buffer circuit model so that the first signal interaction delay meets a first preset duration, thereby synchronizing the software test model and the hardware test model.

[0045] Specifically, during the synchronization process of the aforementioned software test model and hardware test model, the host computer uses Vivado's integrated logic analysis module to capture packets at the optical interface between the CPU and FPGA, and measures the time delay (i.e., simulation step size) between the "optical port output voltage" and the "received current response" in real time. By collecting the time delay, the decoupling delay between the CPU and FPGA nodes can be determined. Based on the measured time delay, the host computer adjusts the coupling parameters between the CPU and FPGA, including the encoding / decoding delay of the Aurora communication link, the relay buffer depth, and the transaction priority, and sends the corresponding correction values ​​to the "first buffer circuit model"—a programmable RC delay module built into the decoupling point between the main simulation circuit and the CPU. By changing the time constant τ of the resistor R or capacitor C, the signal transmission delay is finely adjusted, so that the arrival time of the two signals matches the preset first synchronization duration. In this way, the delay caused by the decoupling of the software and hardware test models can be adjusted through the first buffer circuit model, thereby coupling the two operating carriers and models with different simulation step sizes. This achieves dynamic coupling between the millisecond-level simulation step size of the software test model and the microsecond-level simulation step size of the hardware test model, effectively ensuring the high precision and high reliability of the new energy power station controller test.

[0046] It should be noted that if the waveforms in the test results of the synchronized software test model and the hardware test model are unstable, the first buffer circuit model should be adjusted until the waveforms stabilize.

[0047] Specifically, after the software test model and the hardware test model have completed initial synchronization, if unstable phenomena (such as numerical divergence, oscillation, or interference) are still found in the electrical waveforms output by both, the system will repeatedly adjust the first buffer circuit model until the waveform stabilizes. Due to the synchronization of the software test model and the hardware test model, i.e., the adjustment of the delay between them, the waveforms of electrical quantities in the simulation results may exhibit numerical instability, such as numerical divergence, oscillation, or interference. To solve this problem, this application compensates for the system using the first buffer circuit model to prevent interference and divergence problems caused by decoupling delay, with the ultimate goal of stabilizing the modeled system.

[0048] It should be noted that the aforementioned software testing model is used to simulate the electrical behavior of the new energy unit array; before synchronizing the software testing model and the hardware testing model based on the first buffer circuit model, the process includes: integrating the software testing model into the power grid model. To accurately simulate the electrical behavior of the new energy unit array, the host computer first integrates the software testing model into the power grid model before synchronizing the software testing model and the hardware testing model based on the first buffer circuit model, thereby achieving seamless integration of the digital array and the power grid model and a unified simulation environment.

[0049] In this embodiment of the invention, the software test model and the hardware test model communicate via a PCIe interface. Besides fiber optic solutions, this embodiment also supports alternative communication protocols based on the PCIe physical layer, such as Serial RapidIO, Ethernet TSN, or fiber optics, to meet different bandwidth, distance, and architectural requirements.

[0050] In the above embodiments of the present invention, by deeply integrating the software simulation model on the CPU side with the hardware test model on the FPGA side, reasonable simulation accuracy can be maintained at the microsecond or even sub-nanosecond level. Specifically, during simulation initialization, the embodiments of the present invention allocate different control algorithms and power grid models to the CPU or FPGA according to the priority of computing power requirements: high-frequency, low-latency critical loops (such as power grid models with fast fault switching, real-time voltage and current closed loops, and three-phase NPC models) are preferentially deployed on the FPGA, while the CPU is responsible for complex strategy decisions and network model simulation (such as digital matrix models). In this way, different models can run on suitable computing platforms, thereby improving simulation accuracy.

[0051] In this embodiment of the invention, after the host computer constructs the coupled software test model and hardware test model, the software test model and hardware model are downloaded to the CPU part and simulation circuit part of the simulator, respectively, and a series of closed-loop tests are performed to comprehensively evaluate the performance and reliability of the system.

[0052] In this embodiment of the invention, the above method can be used to construct a hybrid test model that couples a software test model and a hardware test model. The structure of this simulation model is as follows: Figure 3 As shown.

[0053] like Figure 3 The CPU portion, including the software test model established in this embodiment, is responsible for running large-scale, system-level digital models. This model first uses a "digital matrix" or average value model to perform overall equivalent simulation of the voltage, current, and power dynamic characteristics of hundreds or thousands of photovoltaic, energy storage units, and battery systems. The resulting electrical quantities are used as grid connection point inputs and fed back to the grid model on the FPGA side via controlled voltage / current source signals. This achieves coupling and information interaction between the virtual digital matrix and the grid, comprehensively testing the controller's algorithm correctness and response performance, with a focus on system-level scale and grid connection range.

[0054] It is important to note that the aforementioned software testing model consists of a "digital matrix" and pre-compiled controller code (i.e., the controller algorithm). While constructing the "digital matrix" or average value model to simulate the electrical behavior of hundreds or thousands of photovoltaic, energy storage units, and battery systems, the system dynamically loads the control algorithm, compiled and packaged into a .a library file using RT-LAB (or other real-time simulation platforms), into the simulation environment. In this way, the voltage, current, and other state variables output by the digital simulation model are transmitted in real-time as input to the control algorithm library. The code in the library calculates control commands such as PWM drive and reactive power compensation, which are then fed back to the grid model on the FPGA side via controlled voltage / current sources. This achieves deep coupling between the algorithm and the system-level simulation, ensuring consistency between the control logic and the actual controller behavior while also accommodating the simulation scale and speed of large-scale arrays.

[0055] like Figure 3 The FPGA portion includes the hardware simulation model established in this embodiment of the invention, which is responsible for running the high-precision, high-real-time model. For example, the main simulation circuit (i.e. Figure 3 The FPGA-02 integrates a power grid model and a three-level NPC model. Each three-phase NPC model is directly connected to an external hardware controller through the I / O interface of the simulation circuit itself, so as to realize accurate testing of the controller hardware interface and logic, and ensure sub-microsecond response delay and numerical accuracy.

[0056] It is important to note that, to address the issue of directly modeling electrical connections on different chips, this embodiment of the invention uses semaphore interactions to replace the physical electrical connections in the CPU and FPGA sections. Specifically, the coupling between the power grid and the electrical side is achieved by using paired "controlled voltage sources" and "controlled current sources" at the connection point between the CPU and FPGA sections: First, the power grid model on the FPGA side measures the voltage at its ports, and the voltage value is sent to the CPU as a signal via a communication interface (such as PCIe). The digital array on the CPU side (representing a large number of new energy units) receives this voltage signal and uses it as the power source for its grid connection point. After calculation, a corresponding current value is obtained. This current value is then sent back to the FPGA side as a signal, thereby affecting the power grid model.

[0057] In this embodiment, the C-SIL model (digital matrix) running on the CPU platform uses a simulation step size in the microsecond range, while the C-HIL model on the FPGA uses a simulation step size in the nanosecond range. This difference in step size granularity will produce different response delays in the signal interaction between the two models. For example, Figure 4 – Figure 8 This demonstrates the response time of the communication interface in an FPGA from transmitting voltage to receiving current as the step size varies from 210 ns to 2500 ns; the smaller the step size, the faster the response. However, reducing the simulation step size may cause instability in the electrical quantity waveforms, such as numerical divergence, oscillation, or interference. To address this issue, this invention adds a buffer circuit (i.e., ...) next to the controlled source. Figure 3 The RC circuit in the modeling system compensates for system delays to prevent interference and divergence caused by decoupling delays, thereby stabilizing the operation of the entire modeling system.

[0058] In this embodiment of the invention, the buffer circuit adopts a simple first-order RC circuit, whose time constant τ = R·C determines the circuit's response characteristics to the signal (such as filtering bandwidth and phase shift). To ensure that the buffer circuit precisely offsets the negative impact of synchronization delay caused by different simulation step sizes and model complexity on the waveform, the R and C parameters need to be precisely optimized according to the following process: 1. First, the host computer uses a packet capture tool to measure the voltage-current response delay of the CPU-FPGA signal interaction and evaluates the stability indicators of the output waveform (such as total harmonic distortion (THD) and phase margin). 2. Based on the measured response delay, select the corresponding RC value combination: when the response delay is large, τ can be increased to enhance filtering suppression; when the response delay is small, τ can be decreased to reduce excessive delay.

[0059] 3. Secondly, to cope with extreme oscillations or numerical divergence, the following can be done in the RC network: increase damping by appropriately increasing R or connecting a small capacitor in parallel to enhance energy dissipation during signal transition; extend to multiple orders of RLC by connecting inductors in parallel or series on the RC basis to construct a second-order or higher-order RLC damping network to obtain a narrower band vibration suppression effect; and implement active compensation by introducing operational amplifiers / programmable gain amplifiers to form an active filter with adjustable Q value to achieve dynamic band-stop or band-pass compensation.

[0060] In this embodiment, the host computer can flexibly set the simulation step size (20–100 μs or even finer microsecond granularity) and the values ​​of resistor R and capacitor C in the first buffer circuit through the parameter panel or script interface during the model building stage. The actual voltage-current response time and waveform stability are determined by the host computer using packet capture tools such as Vivado ILA to collect the "voltage emitted by the optical port" to "current received" signals at the communication interface between the CPU and FPGA (such as optical port or PCIe). The host computer then performs stability index analysis such as THD and phase margin on the captured test results waveform to calibrate the RC parameters in real time and verify the simulation accuracy and robustness.

[0061] In an optional embodiment, such as Figure 3 As shown, the FPGA section not only includes the main simulation circuit but can also be expanded into several extended simulation circuits (such as FPGA-01 and FPGA-03) to meet the needs of larger-scale or multi-controller parallel testing. Each simulation circuit deploys a three-level NPC model and connects to an external hardware controller one-to-one via its own high-speed I / O ports, enabling real-time hardware-in-the-loop testing of each controller. The extended simulation circuits are interconnected through the same physical communication interface as the main simulation circuit.

[0062] In one optional embodiment, the main simulation circuit and the extended simulation circuit are distributed on different chips, making it impossible to directly connect the electrical model with physical wires. To address this issue, this invention employs paired "controlled voltage sources" and "controlled current sources" at the interface between the two, using digital signals to replace physical wires and achieve logical coupling between the power grid side and the electrical side; and adds a programmable buffer circuit (such as...) next to the controlled source. Figure 3 The RC circuit, by precisely setting the time constant τ of resistor R and capacitor C, performs time-domain compensation for decoupling delay, suppresses high-frequency interference and numerical divergence caused by sudden delay changes, and ensures waveform stability and numerical convergence of the multi-node simulation system.

[0063] In an optional embodiment, such as Figure 3As shown, in addition to the digital matrix model, the CPU section also specifically constructs a battery equivalent model to simulate the dynamic characteristics of the energy storage module. This battery model is connected one-to-one with the FPGA simulation circuit where each three-level NPC is located (such as the controlled voltage and current source at the PCIe channel): after receiving the PWM drive or reactive power compensation command from the external hardware controller, the FPGA-side three-level NPC outputs a control signal, which is transmitted to the CPU via the optical port or differential level converter; the CPU-side battery model takes this control signal as input, calculates the corresponding charging and discharging current or voltage according to the battery SOC, internal impedance, and temperature characteristics, and feeds it back to the corresponding FPGA three-level NPC through the same communication channel.

[0064] The FPGA NPC then maps this feedback electrical quantity to external hardware through its I / O interface to achieve closed-loop energy storage module testing. In this embodiment of the invention, as... Figure 9 As shown, the test model construction for the new energy controller consists of two parts: first, compiling and encapsulating the actual control code of the controller into a static or dynamic library; second, connecting the actual hardware device to the constructed FPGA hardware-in-the-loop simulation model. Subsequently, on the same simulation platform, the compiled library file is first loaded into the software test model on the CPU side to obtain the CSIL output waveform; simultaneously, in the hardware test model on the FPGA side, the actual hardware controller is run, and the voltage, current, or impedance characteristics of the software simulation and hardware response are compared through HLVRT (Hardware Delay Real-Time Test) or impedance Bode plot analysis; if the waveform or frequency response is not within the preset error range, the source code is adjusted and recompiled; when the two are consistent, the verified library file is deeply integrated with the hardware-in-the-loop model to generate the final hybrid simulation model for real-time closed-loop testing and performance verification.

[0065] In this embodiment of the invention, firstly, independent software and hardware test models are established, constructing test environments for the controller software algorithm and hardware function, respectively. Subsequently, by comparing the test results of the two models and iteratively adjusting the software model, it is ensured that the software test model can accurately reproduce the behavior of the hardware test model, providing a foundation of effectiveness and consistency for the subsequent combination of the two models. Finally, by utilizing a first buffer circuit model to synchronize the aforementioned software and hardware test models that have been ensured to be consistent, that is, by adjusting the interference and divergence problems caused by the time delay in the decoupling of the software and hardware test models, the two models with different running carriers and simulation step sizes are coupled, enabling them to run as a unified, dynamically interactive, and stable simulation system. This achieves the goal of deep coupling and collaborative operation of the software-in-the-loop test model and the hardware-in-the-loop test model. Furthermore, since the hardware test model is deployed on N simulation circuits, the number of simulation circuits deployed can be selected according to the actual number of hardware controllers, effectively expanding the parallel testing capability of the hardware test model.

[0066] The steps described above are for clarity only. In practice, they can be combined into one step or some steps can be broken down into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0067] Furthermore, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The terms "embodiment" or "example" appearing in various locations in the specification do not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0068] Another embodiment of the present invention relates to an electronic device, such as Figure 10 As shown, it includes at least one processor 201; and a memory 202 communicatively connected to at least one processor 201; wherein the memory 202 stores instructions that can be executed by at least one processor 201, and the instructions are executed by at least one processor 201 to enable at least one processor 201 to execute a test method for a new energy power station controller as described above.

[0069] The memory 202 and processor 201 are connected via a bus, which may include any number of interconnecting buses and bridges, connecting various circuits of one or more processors 201 and memory 202 together. The bus may also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by processor 201 is transmitted over a wireless medium via an antenna, which further receives data and transmits it to processor 201.

[0070] Processor 201 is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory 202 can be used to store data used by processor 201 during operation.

[0071] Another embodiment of the present invention relates to a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the method embodiments described above.

[0072] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0073] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A test method for a new energy power station controller, characterized in that, include: A software testing model is established to perform in-loop testing on the software functions of the controller; A hardware test model is established to perform in-loop testing on the hardware functions of the controller; the hardware test model runs on N simulation circuits; where N is an integer greater than or equal to 1. Compare the test results of the software test model with the waveforms of the hardware test model; If the comparison result is not within the preset error range, adjust the software test model until the comparison result is within the preset error range; The software test model and the hardware test model are synchronized based on the first buffer circuit model; The step of synchronizing the software test model and the hardware test model based on the first buffer circuit model includes: obtaining a first signal interaction delay between the software test model and the hardware test model; the first signal interaction delay being the duration of one signal interaction between the hardware test model and the software test model; adjusting the first buffer circuit model so that the first signal interaction delay meets a first preset duration, thereby synchronizing the software test model and the hardware test model.

2. The test method for the new energy power station controller according to claim 1, characterized in that, N is an integer greater than or equal to 2; After establishing the hardware test model, the following is included: Obtain the second signal interaction delay between every two simulation circuits; Adjust the second buffer circuit model on the simulation circuit so that the second signal interaction delay meets the second preset duration, and synchronize every two simulation circuits.

3. The test method for the new energy power station controller according to claim 1, characterized in that, The N simulation circuits include one main simulation circuit and N-1 extended simulation circuits, where N is an integer greater than or equal to 2; The establishment of the hardware test model includes: A power grid model and a first NPC model connected to the power grid model are established on the main simulation circuit, and a second NPC model is constructed on each of the extended simulation circuits; The second NPC model is incorporated into the power grid model to establish the hardware test model; The first NPC model is used to receive hardware instructions from the controller through the interface of the main simulation circuit and to provide simulated electrical parameters to the controller; the second NPC model is used to receive hardware instructions from the controller through the interface of the extended simulation circuit and to provide simulated electrical parameters to the controller.

4. The test method for the new energy power station controller according to claim 3, characterized in that, The software testing model is used to simulate the electrical behavior of the new energy unit array; Before synchronizing the software test model and the hardware test model based on the first buffer circuit model, the following steps are included: The software testing model is incorporated into the power grid model.

5. The test method for the new energy power station controller according to claim 1, characterized in that, The method further includes: If the waveforms in the test results of the synchronized software test model and the hardware test model are unstable, the first buffer circuit model is adjusted until the waveforms stabilize.

6. The test method for the new energy power station controller according to claim 1, characterized in that, Each of the simulation circuits is connected to up to five of the controllers.

7. The test method for the new energy power station controller according to claim 1, characterized in that, N is an integer greater than or equal to 2, and every two simulation circuits communicate with each other via an optical fiber interface.

8. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the test method for the new energy power station controller as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the test method for the new energy power station controller as described in any one of claims 1 to 7.

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