Data communication method for hybrid deployment operating system and industrial control device

Abstract

The application relates to the technical field of industrial control, and discloses a data communication method of a hybrid deployment operating system and an industrial control device. The method is applied to the industrial control device, and the method comprises the following steps: determining inter-process shared memory of a non-real-time operating system and target shared memory corresponding to a target real-time operating system; the inter-process shared memory is used for storing a lock signal; the lock signal is used for indicating an accessible state of the target shared memory; the target shared memory is shared memory of a first processor core and a second processor core; the first processor core is used for running the non-real-time operating system; the second processor core is used for running the target real-time operating system; data and the length of the data are written into the target shared memory based on the lock signal and the memory address of the target shared memory; a first interrupt signal is sent to the second processor; the first interrupt signal is used for instructing the real-time operating system to read the data from the target shared memory based on the length of the data. The application can improve the efficiency of inter-core communication while avoiding data conflicts.

Description

Technical Field

[0001] This application relates to the field of industrial control technology, and in particular to a data communication method and industrial control equipment with a hybrid operating system. Background Technology

[0002] With the rapid development of information technology, multi-core processor systems have become a core component of computing architecture, widely used in fields with high real-time requirements such as industrial control, autonomous driving, and edge computing. In multi-core processor systems, efficient collaboration between different processor cores (or processor kernels) is crucial for ensuring overall system performance. Inter-core communication mechanisms are typically used to achieve data communication between multiple processor cores; existing inter-core communication mechanisms include message passing, shared memory, and remote procedure calls.

[0003] However, as application scenarios become more complex, the amount of data that needs to be transferred between processor cores is also increasing. Therefore, when conducting data communication based on existing inter-core communication mechanisms, multiple data copies and frequent interrupt notifications are usually required, resulting in low data communication efficiency. Summary of the Invention

[0004] This application provides a data communication method and industrial control equipment for hybrid operating system deployment, which can improve the efficiency of inter-core communication.

[0005] In a first aspect, embodiments of this application provide a data communication method for a hybrid deployed operating system, applied to industrial control equipment. The method includes: determining inter-process shared memory shared by processes of a non-real-time operating system and a target shared memory corresponding to a target real-time operating system; wherein the inter-process shared memory is used to store a lock signal; the lock signal is used to indicate the accessibility status of the target shared memory; the target shared memory is memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; based on the lock signal and the memory address of the target shared memory, data and the length of the data are written into the target shared memory; a first interrupt signal is sent to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0006] Based on this implementation, a one-time transfer of data to be processed from a non-real-time system to a real-time system can be achieved using inter-core shared memory and inter-process shared memory. This reduces communication latency and read / write resource overhead, and improves communication efficiency between the non-real-time and real-time systems. Furthermore, during data communication between the user process and the target real-time system, setting a lock signal for the target real-time system can prevent data write conflicts caused by multiple user processes simultaneously attempting to communicate with the same target real-time system, thus ensuring data write consistency.

[0007] In one possible implementation, before writing the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory, the method further includes: obtaining the address of the inter-process shared memory; obtaining the lock signal from the inter-process shared memory based on the address of the inter-process shared memory; and determining whether the target shared memory is in an accessible state based on the lock signal.

[0008] Based on this implementation, by setting a lock signal for the inter-process shared memory corresponding to the target real-time system, the synchronization and security of the inter-core communication process can be ensured based on the lock signal, data conflicts can be avoided, and the reliability of communication can be improved.

[0009] In another possible implementation, writing data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory includes: when the target shared memory is in an accessible state, writing data and the length of the data into the target shared memory based on the address of the target shared memory.

[0010] Based on this implementation, by accessing the target shared memory only after determining that it is in an accessible state based on the lock signal, it is possible to avoid access conflicts to the target shared memory caused by multiple user processes simultaneously attempting to communicate with the same target real-time system, thus ensuring the consistency of data writing.

[0011] In another possible implementation, determining whether the target shared memory is in an accessible state based on the lock signal includes: determining whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in an accessible state; and determining that the target shared memory is in an accessible state when the lock signal is the first signal.

[0012] Based on this implementation, by determining the value of the lock signal, data can be written to the target shared memory when the lock signal is available, avoiding long-term blocking of the write task; and when the lock signal is unavailable, it enters a waiting state until the lock signal is released, so as to ensure the fairness and stability of the inter-core communication process.

[0013] In another implementation, the method further includes: updating the lock signal to a second signal using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

[0014] Based on this implementation, when multiple user processes access the same target real-time system at the same time, atomic operations are used to respond to the call of one of the user processes and change the signal value of the lock signal corresponding to the target real-time system, thereby avoiding data conflicts.

[0015] In another possible implementation, the target shared memory includes a first target shared memory and a second target shared memory; the process of writing data and the length of the data into the target shared memory based on its address when the target shared memory is accessible includes: writing the data into the first target shared memory based on its address when the target shared memory is accessible; and writing the length information of the data into the second target shared memory based on its address.

[0016] Based on this implementation, by dividing the target shared memory into a first target shared memory and a second target shared memory, it is possible to achieve regional storage of data and data length, so as to facilitate reading and writing of data and data length separately.

[0017] In another possible implementation, the method further includes: in response to a second interrupt signal sent by the second processor core, obtaining the length of a return message from the target shared memory based on the lock signal and the memory address of the target shared memory; wherein the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message is related to or unrelated to the data; and the return message is read from the target shared memory by the non-real-time operating system based on the memory address of the target shared memory and the length of the return message.

[0018] Based on this implementation, data to be processed can be transferred from a real-time system to a non-real-time system in a single transaction using inter-core shared memory and inter-process shared memory. This avoids multiple data read / write operations and multiple interrupt signal transmissions, significantly reducing communication latency and read / write resource overhead, thus enabling efficient communication between the non-real-time and real-time systems. Furthermore, during data communication between the user process and the target real-time system, setting a lock signal for the target real-time system can prevent data write conflicts caused by multiple user processes simultaneously attempting to communicate with the same target real-time system, ensuring the atomicity and consistency of data writes.

[0019] In another possible implementation, the target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the third target shared memory; the process of obtaining the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory in response to the second interrupt signal sent by the second processor core includes: obtaining the length of the return message from the third target shared memory based on the lock signal and the memory address of the third target shared memory in response to the second interrupt signal sent by the second processor core; the process of reading the return message from the target shared memory through the non-real-time operating system based on the memory address of the target shared memory and the length of the return message includes: reading the return message from the fourth target shared memory through the non-real-time operating system based on the memory address of the fourth target shared memory and the length of the return message.

[0020] Based on this implementation, by dividing the target shared memory into a third target shared memory and a fourth target shared memory, it is possible to achieve regional storage of the returned message and the length of the returned message, so as to facilitate reading and writing of the returned message and the length of the returned message respectively.

[0021] In another possible implementation, determining the target shared memory corresponding to the target real-time operating system includes: obtaining the identifier of the target real-time operating system; determining the target shared memory based on the identifier of the target real-time operating system and a preset mapping relationship; wherein the preset mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

[0022] Based on this implementation, when there are multiple real-time systems deployed, independent target shared memory can be allocated to each real-time system and a mapping relationship can be established, thereby enabling resource isolation when user processes access different real-time systems and when multiple real-time systems perform data write operations.

[0023] Secondly, embodiments of this application also provide a data communication device for a hybrid operating system, configured in industrial control equipment. The device includes: a first determining module configured to determine inter-process shared memory shared by processes of a non-real-time operating system and a target shared memory corresponding to a target real-time operating system; wherein the inter-process shared memory is used to store a lock signal; the lock signal is used to indicate the accessibility status of the target shared memory; the target shared memory is memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; a writing module configured to write data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory; and a sending module configured to send a first interrupt signal to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system to read the data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0024] In one possible implementation, the device further includes: a first acquisition module, a second acquisition module, and a second determination module; the first acquisition module is configured to: acquire the address of the inter-process shared memory; the second acquisition module is configured to: acquire the lock signal from the inter-process shared memory based on the address of the inter-process shared memory; and the second determination module is configured to: determine whether the target shared memory is in an accessible state based on the lock signal.

[0025] In another possible implementation, the write module is specifically configured to write data and the length of the data into the target shared memory based on the address of the target shared memory, provided that the target shared memory is accessible.

[0026] In another possible implementation, the second determining module is specifically configured to: determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in an accessible state; and if the lock signal is the first signal, determine that the target shared memory is in an accessible state.

[0027] In another possible implementation, the device further includes a resource update module; the resource update module is configured to update the lock signal to a second signal using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

[0028] In another possible implementation, the target shared memory includes a first target shared memory and a second target shared memory; the write module is specifically configured to: when the target shared memory is in an accessible state, write the data to the first target shared memory based on the address of the first target shared memory; and write the length information of the data to the second target shared memory based on the address of the second target shared memory.

[0029] In another possible implementation, the device further includes a third acquisition module and a reading module; the third acquisition module is configured to: in response to a second interrupt signal sent by the second processor core, acquire the length of a return message from the target shared memory based on the lock signal and the memory address of the target shared memory; wherein the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message may or may not be related to the data; the reading module is configured to: read the return message from the target shared memory through the non-real-time operating system based on the memory address of the target shared memory and the length of the return message.

[0030] In another possible implementation, the target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the third target shared memory; the third acquisition module is configured to: in response to the second interrupt signal sent by the second processor core, acquire the length of the return message from the third target shared memory based on the lock signal and the memory address of the third target shared memory; the reading module is configured to: read the return message from the fourth target shared memory through the non-real-time operating system based on the memory address of the fourth target shared memory and the length of the return message.

[0031] In another possible implementation, the first determining module is specifically configured to: obtain the identifier of the target real-time operating system; determine the target shared memory based on the identifier of the target real-time operating system and the target mapping relationship; wherein the target mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

[0032] Thirdly, embodiments of this application also provide an industrial control device, including: a processor and a memory; the processor and the memory are coupled; the memory is used to store program instructions; the processor is used to execute the program instructions to perform the method as described in any of the first aspects above.

[0033] Fourthly, embodiments of this application provide a chip for performing the methods described in any of the first aspects above.

[0034] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the method as described in any of the first aspects.

[0035] In a sixth aspect, embodiments of this application provide a program product including a computer program that, when executed by a processor, implements the method as described in any of the first aspects. Attached Figure Description

[0036] Figure 1 A scenario diagram illustrating a data communication method for a hybrid operating system provided in this application embodiment;

[0037] Figure 2 A flowchart illustrating a data communication method for a hybrid deployment operating system provided in this application embodiment;

[0038] Figure 3 A schematic diagram of an inter-core shared memory provided in an embodiment of this application;

[0039] Figure 4 This application provides a schematic diagram illustrating the relationship between a real-time system and inter-process shared memory.

[0040] Figure 5 A schematic diagram of inter-core communication provided in an embodiment of this application;

[0041] Figure 6 A flowchart illustrating another data communication method for hybrid operating system deployment provided in this application embodiment;

[0042] Figure 7 A schematic diagram illustrating another type of inter-core communication provided in an embodiment of this application;

[0043] Figure 8 A flowchart illustrating another data communication method for hybrid operating system deployment provided in this application embodiment;

[0044] Figure 9 A schematic diagram of a data communication device for a hybrid operating system provided in an embodiment of this application;

[0045] Figure 10 This is a schematic diagram of an industrial control device provided in an embodiment of this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0047] The data communication method for hybrid operating system deployment provided in this application can be applied to computing devices, such as industrial control equipment. The industrial control equipment deploys both a real-time operating system (hereinafter referred to as a real-time system) and a non-real-time operating system (hereinafter referred to as a non-real-time system). When implementing data communication between the real-time system and the non-real-time system based on the data communication method for hybrid operating system deployment provided in this application, efficient data communication can be achieved based on inter-core shared memory and inter-process shared memory.

[0048] Figure 1 A scenario diagram illustrating a data communication method for a hybrid operating system provided in this application embodiment, such as... Figure 1 As shown, the industrial control equipment 100 is equipped with one or more multi-core processors 10, each including multiple processor cores. These processor cores can be ARM or x86 architecture central processing unit (CPU) cores.

[0049] In some embodiments, a non-real-time system 11 and a real-time operating system (RTOS) 12 can be deployed on different processor cores in a multi-core processor 10, or they can be deployed on different processor cores in different multi-core processors 10. For example, a non-real-time system 11 can be deployed on a first processor core, and a real-time system can be deployed on a second processor core; furthermore, one or more real-time systems can be deployed on the second processor core. The non-real-time system 11 (such as Windows or Linux) typically employs a time-sharing scheduling algorithm, where all tasks have the same priority. Therefore, the non-real-time system 11 is suitable for running ordinary applications but cannot guarantee high real-time performance of task execution.

[0050] Real-time system 12 is an operating system capable of responding to external events or data within a specified time and scheduling resources to complete real-time tasks. The core function of real-time system 12 is to schedule and manage real-time tasks, ensuring that all tasks run in a coordinated manner. Real-time system 12 employs a multi-tasking mechanism; its kernel schedules multiple external event threads to run concurrently, enabling concurrent task execution. Furthermore, real-time system 12 uses a preemptive task scheduling mechanism. When a higher-priority task becomes executable while a task is being executed, the preemptive task immediately seizes the current processor resources and exits, allowing the higher-priority task to run first. This preemptive task scheduling mechanism ensures that high-priority tasks are processed promptly, meeting real-time requirements.

[0051] The non-real-time system 11 is used to display the user's graphical interface and perform tasks with low real-time requirements, such as image rendering, file downloading, database querying, and log recording. The real-time system 12 is used to perform highly real-time tasks, such as motion control of industrial equipment, emergency stop triggering of industrial equipment, and overload protection of power systems—tasks that require strict control over execution duration and sequence. Compared to the real-time system 12, the non-real-time system 11 supports a richer software and hardware ecosystem and can achieve more diverse functions. Users can integrate more third-party software and hardware into the non-real-time system 11.

[0052] The controlled device 110 may include industrial equipment (such as CNC machine tools, robots, industrial cameras), medical equipment, lidar and braking devices in autonomous driving systems, aircraft, and other devices with high real-time requirements for data transmission. The real-time system 12 and the controlled device 110 can communicate via real-time Ethernet communication protocols, such as EtherCAT (Ethernet for Control Automation Technology), Time-Sensitive Networking (TSN), and process field network protocols.

[0053] In some embodiments, the industrial control device 100 may include one or more memory modules, which may be dynamic random-access memory (DRAM), static random-access memory (SRAM), synchronous dynamic random-access memory (SDRAM), etc., and this embodiment does not limit the specific memory used. The non-real-time system 11 can divide the total memory area corresponding to one or more memory modules into inter-core shared memory and inter-process shared memory. Inter-core shared memory and inter-process shared memory are independent memory areas, which may reside on the same memory or on different memory areas. The number of inter-core shared memory modules can be one; the number of inter-process shared memory modules is equal to the number of real-time systems deployed, and there is a one-to-one correspondence between inter-process shared memory and real-time systems. Furthermore, based on the number of real-time systems, the inter-core shared memory can be divided into one or more sub-inter-core shared memory modules, the number of which is equal to the number of real-time systems deployed, and there is a one-to-one correspondence between sub-inter-core shared memory and real-time systems.

[0054] In some embodiments, the non-real-time system 11 and the real-time system 12 can communicate and transmit data based on inter-core shared memory and inter-process shared memory. For example, a user process runs in the non-real-time system 11; the user process is the process used by the application running on the non-real-time system 11. The user process in the non-real-time system 11 and the real-time system 12 can transmit data through inter-core communication, allowing the user process to transmit data (hereinafter referred to as pending data) required by the application in the non-real-time system 11 to the real-time system 12. The pending data may include control instructions for the controlled device 110, operating status information of the controlled device 110, and other data. A resource management process also runs in the non-real-time system 11. This resource management process assists in communication between the user process and the real-time system, and manages the lock signals and status signals corresponding to the inter-process shared memory, thereby enabling data transmission between the user process in the non-real-time system 11 and the real-time system 12 and avoiding resource conflicts when multiple user processes access the same process shared memory.

[0055] In some embodiments, when the data to be processed received by the real-time system 12 is the working status information of the controlled device 110, the real-time system 12 can store this data in a memory buffer used solely by the real-time system 12. When the data to be processed received by the real-time system is a control command, the real-time system 12 can send the control command to the controlled device 110 to control the controlled device 110; furthermore, the real-time system 12 can collect the execution result of the controlled device 110 on the control command and transmit the execution result to the non-real-time system 11. Further, the resource management process in the non-real-time system 11 can assist the user process in obtaining the execution result based on inter-process shared memory and inter-core shared memory.

[0056] It should be noted that the multi-core processor 10 can be a multi-core system-on-a-chip (SoC), which includes multiple processor cores and memory. For example, Figure 1 The first processor core, the second processor, and the inter-process shared memory and inter-core shared memory shown are integrated into the same multi-core system-on-a-chip.

[0057] Figure 2 This is a flowchart illustrating a data communication method for a hybrid operating system provided in this embodiment. It should be noted that this data communication method is executed by an industrial control device, specifically a processor or processor core within that device. The method steps executed by the process or software described in this embodiment are actually called by the processor or processor core, meaning the actual execution entity is the processor or processor core.

[0058] like Figure 2 As shown, the method includes steps 210 to 230.

[0059] Step 210: Determine the inter-process shared memory shared by processes of the non-real-time operating system and the target shared memory corresponding to the target real-time operating system.

[0060] In some embodiments, deployment personnel can pre-define the size and physical address (the physical address being the starting address of the inter-core shared memory) in a configuration file via kernel boot parameters (such as the cmdline parameter in the Linux operating system). For example, the size of the inter-core shared memory can be defined as 8GB, and the physical address as 0x1800000. The size of the inter-core shared memory can be determined based on the maximum data transfer volume in the actual usage scenario to reserve sufficient memory space for data transfer during inter-core communication, thereby reducing the number of data copies and interrupt signal transmissions during inter-core communication.

[0061] During the deployment of both non-real-time (NRT) and real-time (RT) systems, the NRT system kernel loads kernel startup parameters from the configuration file via the bootloader. Based on the size and physical address of the inter-core shared memory defined in these parameters, it performs a memory map operation, reserving a portion of the total memory area on the multi-core processor as inter-core shared memory. After deployment on the multi-core processor, both the NRT and RRT systems can jointly perform data read and write operations within this inter-core shared memory. Additionally, a portion of the remaining memory in the total memory area can be used separately by the NRT and RRT systems, respectively.

[0062] In non-real-time systems, a resource management process can run, which allocates inter-process shared memory to each real-time system and determines the size and physical address (starting address) of the inter-process shared memory. This inter-process shared memory is a memory region outside the total memory area excluding inter-core shared memory and the separate memory regions used by non-real-time and real-time systems. It is used for data communication between user processes and the resource management process in non-real-time systems.

[0063] In some embodiments, in addition to pre-defining the size and physical address (which is the starting address of the inter-core shared memory) of the inter-core shared memory in the configuration file via kernel boot parameters, the deployer can also define the size and physical address (which is the starting address of the sub-core shared memory) of the sub-core shared memory corresponding to each real-time system in the inter-core shared memory.

[0064] refer to Figure 3 The diagram shown illustrates an inter-core shared memory mechanism. Figure 3 As shown, during the deployment of non-real-time and real-time systems, the kernel of the non-real-time system loads the kernel startup parameters in the configuration file through the bootloader, and performs memory mapping operations based on the size and physical address of the shared memory between each sub-core defined in the kernel startup parameters, thereby dividing the shared memory between each sub-core corresponding to the real-time system in the shared memory between cores.

[0065] In some examples, a pre-defined mapping relationship can be established between the physical addresses of the real-time system and the shared memory between the sub-cores. This could be achieved by establishing a pre-defined mapping relationship between the identifiers of each real-time system and the physical addresses of the shared memory between the sub-cores; where each real-time system's identifier corresponds to a unique physical address of the shared memory between the sub-cores. For example, such as... Figure 3 As shown, inter-core shared memory A corresponds to real-time system A, inter-core shared memory B corresponds to real-time system B, and inter-core shared memory C corresponds to real-time system C.

[0066] In some embodiments, the resource management process can initialize inter-process shared memory in the total memory area. The number of inter-process shared memory units can be one or more; the number of inter-process shared memory units is determined by the number of real-time systems deployed, meaning there is a one-to-one correspondence between real-time systems and inter-process shared memory units.

[0067] In some examples, a pre-defined mapping relationship can be established between real-time systems and inter-process shared memory, such as establishing a pre-defined mapping relationship between the identifier of the real-time system and the identifier of the inter-process shared memory; wherein the identifier of the real-time system corresponds to a unique identifier of the inter-process shared memory. (See reference) Figure 4 The diagram illustrates the relationship between a real-time system and inter-process shared memory. Figure 4 As shown, inter-process shared memory A corresponds to real-time system A, inter-process shared memory B corresponds to real-time system B, and inter-process shared memory C corresponds to real-time system C.

[0068] In some embodiments, after determining the inter-process shared memory corresponding to the real-time system, the resource management process can further initialize the lock signals and status signals corresponding to the real-time system to determine the initial values ​​of the lock signals and status signals, and write the lock signals and status signals into the inter-process shared memory corresponding to the real-time system. The initial values ​​of both the lock signals and status signals are the first signal (e.g., 0). Figure 4 As shown, after initializing the lock signal a and the status signal a corresponding to the real-time system A, the lock signal a and the status signal a can be written into the inter-process shared memory A corresponding to the real-time system A.

[0069] The lock signal is used to indicate whether a user process can currently use the shared memory corresponding to the real-time system for data communication. For example, when the lock signal value is the first signal (e.g., 1), it indicates that the user process can currently use the shared memory corresponding to the real-time system to communicate with the real-time system; and when the lock signal value is the second signal (e.g., 0), it indicates that the user process cannot currently use the shared memory corresponding to the real-time system to communicate with the real-time system and enters a waiting state (or a blocked state) until the lock signal value is the first signal.

[0070] Status signals are semaphore resources used to indicate whether a user process is currently able to communicate with the real-time system. For example, a status signal value of 1 indicates that the user process can communicate with the real-time system; and a status signal value of 0 indicates that the user process enters a waiting state until the status signal value changes back to the first signal, at which point the user process can be woken up from the waiting state by the resource management process.

[0071] In some embodiments, after the non-real-time system has allocated inter-core shared memory and inter-process shared memory, applications running on the non-real-time system can communicate with the real-time system through user processes within the non-real-time system, based on the inter-core shared memory and inter-process shared memory. For example, when multiple real-time systems are deployed, different user processes can communicate with different real-time systems separately, or different user processes can communicate with the same real-time system.

[0072] For example, a user process can first determine the real-time system to be communicated with (hereinafter referred to as the target real-time system) among all real-time systems, determine which real-time system to send the data to, and determine the memory address (such as a virtual address) of the inter-core shared memory (hereinafter referred to as the target shared memory) corresponding to the target real-time system. In some examples, the user process can determine the identifier of the real-time system to be communicated with (the target real-time system), where different real-time systems have unique identifiers. Then, it calls the first interface provided by the non-real-time system (hereinafter referred to as the inter-core communication initialization interface), transmitting the identifier of the target real-time system to the inter-core communication initialization interface. This allows the user process to obtain a pre-defined mapping relationship between the real-time system and inter-process shared memory from the non-real-time system. Based on this pre-defined mapping relationship and the identifier of the target real-time system, the user process determines the physical address of the inter-process shared memory corresponding to the target real-time system and returns it to the user process. Additionally, the user process obtains a pre-defined mapping relationship between the real-time system and sub-core shared memory from the non-real-time system, and based on this pre-defined mapping relationship and the identifier of the target real-time system, determines the physical address of the target shared memory corresponding to the target real-time system and returns it to the user process. The inter-core communication initialization interface is used for data communication between the user process and the non-real-time system.

[0073] For example, such as Figure 3 As shown, if the target real-time system corresponding to the user process is target real-time system A, then the user process can determine that the inter-core shared memory corresponding to target real-time system A is target shared memory A; for example... Figure 4As shown, if the target real-time system corresponding to the user process is target real-time system A, then the user process can determine that the inter-process shared memory corresponding to target real-time system A is inter-process shared memory A.

[0074] In some examples, after obtaining the physical address of the inter-process shared memory, the user process can perform virtual address mapping on the physical address of the inter-process shared memory corresponding to the target real-time system to obtain the virtual address of the inter-process shared memory corresponding to the target real-time system; and, it can perform virtual address mapping on the physical address of the target shared memory to obtain the virtual address of the target shared memory.

[0075] Step 220: Based on the lock signal and the memory address of the target shared memory, write the data and the length of the data into the target shared memory.

[0076] Next, the user process can determine the data to be sent and its length. (See reference) Figure 5 The diagram shown illustrates an inter-core communication method, as follows: Figure 5 As shown, a user process can call the inter-core communication interface to write data and its length into the target shared memory based on the memory address of the target shared memory.

[0077] In some embodiments, after a user process obtains the physical address of the inter-process shared memory corresponding to the target real-time system, it can call the second interface provided by the non-real-time system (hereinafter referred to as the inter-core communication message sending interface) to read the lock signal in the inter-process shared memory corresponding to the target real-time system based on the physical address of the inter-process shared memory corresponding to the target real-time system. The lock signal in the inter-process shared memory corresponding to the target real-time system is used to indicate the accessibility status of the target shared memory corresponding to the target real-time system.

[0078] User processes can use the inter-core communication message sending interface to determine whether the current value of the lock signal for the inter-process shared memory corresponding to the target real-time system is equal to the first signal (e.g., 1), thus determining whether the target shared memory is currently accessible. The first signal indicates that the target shared memory is accessible. For example, the inter-core communication message sending interface can periodically poll the value of the lock signal so that the user process can promptly perform data write operations when the lock signal value changes from the second signal to the first signal. The second signal indicates that the target shared memory is inaccessible.

[0079] In some embodiments, if the current value of the lock signal corresponding to the target shared memory is equal to the first signal (e.g., 1), indicating that the target shared memory is currently accessible, the user process can write data and its length into the target shared memory based on its address. Furthermore, the inter-core communication message sending interface can use an atomic operation to change the value of the lock signal to the second signal (e.g., 0) to indicate that the target shared memory is currently inaccessible. This means that the user process is currently communicating with the target real-time system, preventing other user processes in the non-real-time system from communicating with the target real-time system (e.g., from accessing the inter-process shared memory corresponding to the target real-time system or writing data to it), thus avoiding data conflicts. Here, "atomic operation" means that when multiple user processes access the same target real-time system simultaneously, the inter-core communication message sending interface can only respond to the call of one user process and change the signal value of the lock signal corresponding to the target real-time system.

[0080] For example, if user process A obtains lock signal a in the inter-process shared memory A corresponding to the target real-time system A, and the current value of lock signal a is equal to 1, then the inter-core communication message sending interface will set the value of lock signal a to 0, indicating that user process A is currently accessing the target shared memory A corresponding to the target real-time system A.

[0081] In some embodiments, if the value of the lock signal corresponding to the target real-time system is equal to the second signal (e.g., 0), the user process enters a state of waiting for the lock signal until the value of the lock signal equals the first signal (e.g., 1). Continuing the example above, if user process B needs to access inter-process shared memory A when the value of lock signal a is 0, user process B cannot access inter-process shared memory A because the value of lock signal a in inter-process shared memory A is 0. Therefore, user process B enters a state of waiting for the lock signal until user process A releases lock signal a, making the value of lock signal a equal to 1, at which point user process B can acquire the lock signal and access inter-process shared memory A.

[0082] Step 230: Send a first interrupt signal to the second processor.

[0083] In some embodiments, after performing the above-described write operation, the user process may send a processing request to the resource management process. This processing request instructs the resource management process to read the data length from the target shared memory corresponding to the target real-time system. For example... Figure 5 As shown, the resource management process then responds to the processing request sent by the user process and reads the length of data from the target shared memory based on the memory address (such as the physical address) of the target shared memory corresponding to the target real-time system.

[0084] In some embodiments, the status signals corresponding to the target real-time system may include two associated status signals. One status signal (hereinafter referred to as the first status signal) is the status signal corresponding to when the resource management process receives a processing request sent by the user process, and the other status signal (hereinafter referred to as the second status signal) is the status signal corresponding to when the resource management process sends a processing result to the user process. The initial values ​​of both the first and second status signals can be set to 0.

[0085] After writing the data and data length to the target shared memory corresponding to the target real-time system, the user process can send a processing request to the resource management process for the first status signal in the target shared memory. The user process then performs a V operation (semPost operation) on this first status signal to request data communication with the target real-time system. The status signal includes the first status signal. After sending the processing request to the resource management process, the user process enters a waiting state, i.e., waiting for a response from the resource management process.

[0086] In some embodiments, after receiving a processing request for a first status signal from a user process, if no other user process is currently using the first status signal of the target real-time system, the resource management process can respond to the processing request by allowing the user process to call the semPost interface to increment the value of the first status signal by a preset step. For example, if the preset step is 1, the value of the first status signal is incremented by 1. It is understood that if a user process has already used the status signal corresponding to the target real-time system and has not released it, other user processes cannot obtain the status signal corresponding to the inter-process shared memory, thus avoiding contention for the same status signal among multiple user processes.

[0087] For example, if user process A sends a request to the resource management process to process the first status signal a1, the resource management process can allow the user process to increment the value of the first status signal a1 by 1, and the current value of the first status signal a1 will be 1.

[0088] In some embodiments, after a user process acquires a first status signal, the resource management process can reduce the value of the first status signal according to a preset step. That is, the resource management process can perform a P operation (i.e., a semWait operation) on the first status signal to indicate that a user process is currently using the first status signal of the target real-time system.

[0089] In some embodiments, after the user process obtains the first status signal, the resource management process can determine the memory address of the target shared memory corresponding to the first status signal based on the first status signal, and read the length of data written by the user process from the target shared memory based on the memory address of the target shared memory.

[0090] Subsequently, the resource management process sends the memory address of the target shared memory and the length of the read data to the target real-time system, and sends an interrupt signal (hereinafter referred to as the first interrupt signal) to the target real-time system. For example, the resource management process can send the first interrupt signal, the memory address of the target shared memory, and the data length to the target real-time system through the remote processor messaging (rpmsg) sending interface (rpmsg_send interface); wherein, the first interrupt signal is used to instruct the target real-time operating system to read data from the target shared memory based on the data length and the memory address of the target shared memory.

[0091] The target real-time system can receive and respond to the first interrupt signal via the rpmsg_send interface. Based on the received data length and the memory address of the target shared memory, it reads data from the target shared memory; that is, the target real-time system starts from the memory address of the target shared memory and reads data of the corresponding length according to the data length information. For example, when the target real-time system detects the first interrupt signal, it can call the receive service and read data from the target shared memory through the receive service.

[0092] In some embodiments, the non-real-time system may further divide the target shared memory corresponding to the target real-time system into a first target shared memory and a second target shared memory. The first target shared memory is used to store data, and the second target shared memory is used to store the length of the data. Therefore, when the target shared memory corresponding to the target real-time system is accessible, the user process can write data into the first target shared memory based on its memory address, and write the length information of the data into the second target shared memory based on its address.

[0093] Furthermore, when responding to a processing request sent by a user process, the resource management process can read the length information of the data from the second target shared memory based on the memory address (e.g., physical address) corresponding to the target real-time system. Then, the resource management process can send a first interrupt signal, the memory address of the first target shared memory, and the length of the read data to the target real-time system. This allows the target real-time system to receive and respond to the first interrupt signal, and read data from the first target shared memory based on the received data length and the memory address of the first target shared memory; that is, the target real-time system starts from the memory address of the first target shared memory and reads data of the corresponding length according to the data length information.

[0094] In some embodiments, after acquiring data, if the data is the working status information of the controlled device, the target real-time system can store the data in a memory buffer used solely by the target real-time system; if the data is a control instruction for the controlled device, the target real-time system can send the control instruction to the controlled device to control the controlled device.

[0095] The above scheme enables a one-time transfer of data from a non-real-time system to a real-time system based on inter-core shared memory and inter-process shared memory. This avoids multiple data read / write operations and multiple interrupt signal transmissions, significantly reducing communication latency and read / write resource overhead, thus achieving efficient communication between the non-real-time and real-time systems. Furthermore, user processes can use the inter-core communication initialization interface to determine the addresses of the target shared memory and inter-process shared memory corresponding to the target real-time system based on the target real-time system's identifier, thereby enabling data communication between the user process and the target real-time system.

[0096] Furthermore, during the data communication process between user processes and real-time systems, by setting lock signals for each real-time system, the problem of data write conflicts caused by multiple user processes simultaneously attempting to communicate with the same real-time system can be avoided, ensuring the consistency of data writes.

[0097] Figure 6 A flowchart of another data communication method for a hybrid operating system provided in this application embodiment is shown below. Figure 6 As shown, the above method also includes steps 610 to 620.

[0098] Step 610: In response to the second interrupt signal sent by the second processor core, obtain the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory.

[0099] In some embodiments, the target real-time system may also send data to a non-real-time system (hereinafter referred to as a return message). This return message may be the processing result obtained after processing the data sent by the non-real-time system.

[0100] For example, after receiving and processing data sent by the user process, the target real-time system can obtain the processing result. The target real-time system can call a receiving service and read the data written by the user process based on the address of the first target shared memory. If the data is the working status information of the controlled device, it can be written to a memory buffer used separately by the target real-time system through the receiving service. The application in the target real-time system can then directly read and process the data from this memory buffer. For example, in industrial automation, the application in the target real-time system can filter and perform calculations on the data collected by sensors from the controlled device. If the data is a control command for the controlled device, the target real-time system can send the control command to the controlled device to control it and obtain the execution result (i.e., the processing result) of the control command by the controlled device.

[0101] In some embodiments, the return message sent by the target real-time system to the non-real-time system may also be information unrelated to the data sent by the non-real-time system, such as the working status information of industrial control equipment automatically collected by the target real-time system. That is, the return message may or may not be related to the data sent by the non-real-time system.

[0102] refer to Figure 7 Another schematic diagram of inter-core communication is shown, such as Figure 7 As shown, the target real-time system can call the inter-core communication interface and, based on the memory address of the target shared memory corresponding to the target real-time system, write the return message and its length into the target shared memory through the inter-core communication interface. Furthermore, the target real-time system can send a second interrupt signal to the non-real-time system via the rpmsg_send interface. This second interrupt signal instructs the non-real-time operating system to read the return message from the target shared memory.

[0103] Next, the second processor core can respond to the second interrupt signal by calling the resource management process, so that the resource management process can read the length of the return message from the target shared memory based on the memory address of the target shared memory corresponding to the target real-time system.

[0104] In some embodiments, when configuring the target shared memory corresponding to the target real-time system, the non-real-time system can further divide the target shared memory into a third target shared memory and a fourth target shared memory. The third target shared memory is used to store the length of the returned message, and the fourth target shared memory is used to store the returned message itself. For example, the real-time system can write the length of the returned message to the third target shared memory based on its memory address, and write the returned message to the fourth target shared memory based on its memory address. Thus, the resource management process can read the length of the returned message from the third target shared memory based on its memory address.

[0105] Step 620: Based on the memory address of the target shared memory and the length of the returned message, read the returned message from the target shared memory using a non-real-time operating system.

[0106] In some embodiments, after obtaining the length of the returned message, the resource management process can obtain the second status signal in the inter-process shared memory corresponding to the target real-time system, and increment the value of the second status signal according to a preset step, so as to change the value of the second status signal from the initial first signal to the second signal. For example, if the preset step is 1, the value of the second status signal is incremented by 1.

[0107] like Figure 7 As shown, after the resource management process changes the value of the second status signal from the initial first signal (e.g., 0) to the second signal (e.g., 1), it can wake up the user process so that the user process ends the waiting state and reads the return message from the target shared memory based on the virtual address of the target shared memory corresponding to the second status signal and the length of the return message.

[0108] For example, consider a user process A communicating with a target real-time system A, where the target real-time system A corresponds to inter-process shared memory A and a target shared memory A, and the inter-process shared memory A includes a second status signal a2. Then, after the resource management process reads the length of the returned message from the target shared memory A, it retrieves the second status signal a2 from the inter-process shared memory A and increments the value of the second status signal a2 by 1. The current value of the second status signal a2 changes from its initial value of 0 to 1.

[0109] In some embodiments, after obtaining the processing result, the user process can update the value of the lock signal from the second signal to the first signal to release the lock signal. For example, after receiving the return message sent by the target real-time system and the resource management process, the user process can call the inter-core communication message sending interface to change the value of the lock signal from the second signal (e.g., 0) to the first signal (e.g., 1), thereby releasing the lock signal in the inter-process shared memory of the target real-time system.

[0110] Through the above scheme, while a user process is waiting for return messages from the target real-time system and the resource management process, the resource management process can determine whether to wake up the user process based on the value of the second state signal. Therefore, different user processes will detect different second state signals when waiting for return messages from different real-time systems, thus avoiding data conflicts. Furthermore, after receiving the return message, the user process releases the lock signal in the inter-process shared memory corresponding to the target real-time system, restoring the lock signal to an available state. This allows other user processes to acquire the lock signal in the inter-process shared memory corresponding to the target real-time system and communicate with it.

[0111] In some embodiments, after a user process obtains the processing result and returns it to the application, if the user process's lifecycle ends, the user process can call a third interface provided by the non-real-time system (hereinafter referred to as the inter-core communication deinitialization interface) to remove the mapping relationship between the virtual address and physical address of the inter-process shared memory, as well as the mapping relationship between the virtual address and physical address of the inter-core shared memory; and the user process can close the status signal through the inter-core communication deinitialization interface to remove the association between the status signal and the user process.

[0112] In some embodiments, if it is necessary to destroy a real-time system deployed in a non-real-time system, the resource management process can destroy the resources associated with the real-time system. For example, the resource management process can first determine whether all lock signals and status signals are at their initial values, i.e., whether any user processes are still communicating with the real-time system. If all lock signals and status signals are at their initial values, the resource management process can delete the real-time system, call the destroy interface to destroy the status signals corresponding to the real-time system, and then destroy the inter-process shared memory corresponding to the real-time system. Simultaneously with the destruction of the inter-process shared memory, the lock signals corresponding to the real-time system are also destroyed.

[0113] Figure 8A flowchart illustrating another data communication method for a hybrid operating system provided in this application embodiment is shown below. Figure 8 As shown, the method includes steps 801 to 811.

[0114] Step 801: The first processor core obtains a lock signal from the inter-process shared memory through a user process in the non-real-time system, based on the address of the inter-process shared memory corresponding to the target real-time system.

[0115] Understandably, the implementation of step 801 can be referred to the descriptions of steps 210 and 220, and will not be repeated here.

[0116] Step 802: If the target shared memory corresponding to the target real-time system is determined to be in an accessible state based on the lock signal, the first processor core writes the data and the length of the data into the target shared memory through the user process based on the memory address of the target shared memory.

[0117] Understandably, the implementation of step 802 can be referred to the description of step 220, and will not be repeated here.

[0118] Step 803: The first processor core sends a processing request to the resource management process through the user process.

[0119] Understandably, the implementation of step 803 can be referred to the description of step 230, and will not be repeated here.

[0120] Step 804: The first processor core responds to the processing request through the resource management process and reads the length of data from the target shared memory based on the memory address of the target shared memory.

[0121] Understandably, the implementation of step 804 can be referred to the description of step 230, and will not be repeated here.

[0122] Step 805: The first processor core sends the memory address of the target shared memory, the data length, and the first interrupt signal to the second processor core through the resource management process.

[0123] Understandably, the implementation of step 805 can be referred to the description of step 230, and will not be repeated here.

[0124] Step 806: The second processor core responds to the first interrupt signal through the target real-time system and reads data from the target shared memory based on the data length and the memory address of the target shared memory.

[0125] Understandably, the implementation of step 806 can be referred to the description of step 230, and will not be repeated here.

[0126] Step 807: The second processor core writes the return message and the length of the return message into the target shared memory through the target real-time system, based on the memory address of the target shared memory.

[0127] Understandably, the implementation of step 807 can be referred to the description of step 610, and will not be repeated here.

[0128] Step 808: The second processor core sends a second interrupt signal to the first processor core through the target real-time system.

[0129] Understandably, the implementation of step 808 can be referred to the description of step 610, and will not be repeated here.

[0130] In step 809, the first processor core responds to the second interrupt signal and, through the resource management process, reads the length of the return message from the target shared memory based on the memory address of the target shared memory.

[0131] Understandably, the implementation of step 809 can be referred to the description of step 620, and will not be repeated here.

[0132] Step 810: The first processor core wakes up the user process through the resource management process, and reads the return message from the target shared memory through the user process based on the memory address of the target shared memory and the length of the return message.

[0133] Understandably, the implementation of step 810 can be referred to the description of step 620, and will not be repeated here.

[0134] Step 811: The first processor core releases the lock signal of the inter-process shared memory corresponding to the target real-time system through the user process.

[0135] Understandably, the implementation of step 811 can be referred to the description of step 520, and will not be repeated here.

[0136] By applying the above technical solutions, based on inter-core shared memory and process shared memory, single data read / write operations are performed during data transmission, and only a single inter-core interrupt notification is needed, thereby improving the efficiency of inter-core communication. Furthermore, mutex locks are implemented through atomic operations, and independent inter-core shared memory and status signals are allocated to each real-time system, ensuring resource isolation. Simultaneously, in concurrent scenarios with multiple user processes, data corruption and lock contention issues are avoided, thus improving the stability of inter-core communication. In addition, the resource initialization and release processes are uniformly managed by the resource management process on the non-real-time side, and user processes only need to call standardized interfaces (such as initialization, sending, and de-initialization) to obtain resources and related memory addresses, thus eliminating the need for users to concern themselves with the underlying data interaction process, improving user experience. Moreover, the quantity and size of inter-process shared memory and secondary shared memory can be dynamically adjusted according to the number of real-time systems deployed and business needs, ensuring deployment flexibility.

[0137] Figure 9 This is a schematic diagram of a data communication device for a hybrid operating system provided in an embodiment of this application. Figure 9 As shown, the data communication device 900 with a hybrid operating system can be configured in industrial control equipment; the data communication device 900 with a hybrid operating system includes a first determining module 901, a writing module 902, and a sending module 903.

[0138] The first determining module 901 is configured to determine the inter-process shared memory shared by processes of a non-real-time operating system and the target shared memory corresponding to the target real-time operating system.

[0139] In this system, inter-process shared memory is used to store lock signals; lock signals are used to indicate the accessibility status of the target shared memory; the target shared memory is memory shared by the first processor core and the second processor core; the first processor core is used to run a non-real-time operating system; and the second processor core is used to run the target real-time operating system.

[0140] The write module 902 is configured to write data and the length of the data to the target shared memory based on the lock signal and the memory address of the target shared memory.

[0141] The sending module 903 is configured to send a first interrupt signal to the second processor core.

[0142] The first interrupt signal is used to instruct the target real-time operating system to read data from the target shared memory based on the length of the data and the memory address of the target shared memory.

[0143] like Figure 9As shown, the data communication device 900 with a hybrid operating system further includes: a first acquisition module 904, a second acquisition module 905, and a second determination module 906.

[0144] In some embodiments, the first acquisition module 904 is configured to: acquire the address of inter-process shared memory; the second acquisition module 905 is configured to: acquire a lock signal from the inter-process shared memory based on the address of the inter-process shared memory; and the second determination module 906 is configured to: determine whether the target shared memory is in an accessible state based on the lock signal.

[0145] In some embodiments, the write module 902 is specifically configured to write data and the length of the data into the target shared memory based on the address of the target shared memory when the target shared memory is in an accessible state.

[0146] In some embodiments, the second determining module 906 is specifically configured to: determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in an accessible state; and if the lock signal is the first signal, determine that the target shared memory is in an accessible state.

[0147] like Figure 9 As shown, the data communication device 900 with a hybrid operating system also includes a resource update module 907.

[0148] In some embodiments, the resource update module 907 is configured to update the lock signal to a second signal using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

[0149] In some embodiments, the target shared memory includes a first target shared memory and a second target shared memory; the write module 902 is specifically configured to: when the target shared memory is in an accessible state, write data to the first target shared memory based on the address of the first target shared memory; and write the length information of the data to the second target shared memory based on the address of the second target shared memory.

[0150] like Figure 9 As shown, the data communication device 900 with a hybrid operating system also includes a third acquisition module 908 and a reading module 909.

[0151] In some embodiments, the third acquisition module 908 is configured to: in response to a second interrupt signal sent by the second processor core, acquire the length of the return message from the target shared memory based on a lock signal and the memory address of the target shared memory; wherein the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message may or may not be related to data; the reading module 909 is configured to: read the return message from the target shared memory through the non-real-time operating system based on the memory address of the target shared memory and the length of the return message.

[0152] In some embodiments, the target shared memory includes a third target shared memory and a fourth target shared memory; a second interrupt signal is used to instruct the non-real-time operating system to read a return message from the third target shared memory; a third acquisition module 908 is configured to: in response to a second interrupt signal sent by a second processor core, acquire the length of the return message from the third target shared memory based on a lock signal and the memory address of the third target shared memory; and a reading module 909 is configured to: read the return message from the fourth target shared memory through the non-real-time operating system based on the memory address of the fourth target shared memory and the length of the return message.

[0153] In some embodiments, the first determining module 901 is specifically configured to: obtain the identifier of the target real-time operating system; determine the target shared memory based on the identifier of the target real-time operating system and the target mapping relationship; wherein the target mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

[0154] Figure 10 This is a schematic diagram of an industrial control device provided for some embodiments of this application. The industrial control device includes one or more processors and a memory. The memory is configured to store one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the data communication method of the hybrid operating system described in the above embodiments.

[0155] like Figure 10 As shown, the industrial control device 1000 includes a processor 1001 and a memory 1002. Exemplarily, the industrial control device 1000 may also include a communications interface 1003 and a communications bus 1004.

[0156] The processor 1001, memory 1002, and communication interface 1003 communicate with each other via communication bus 1004. Communication interface 1003 is used to communicate with other network elements such as clients or other servers.

[0157] In some embodiments, the processor 1001 is used to execute program 1005, specifically performing the relevant steps in the above-described embodiments of the data communication method for a hybrid operating system. Specifically, program 1005 may include program code, which includes computer-executable instructions.

[0158] For example, processor 1001 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement some embodiments of this application. Industrial control device 1000 may include one or more processors, which may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs.

[0159] In some embodiments, memory 1002 is used to store program 1005. Memory 1002 may include high-speed RAM memory and may also include non-volatile memory (NVM), such as at least one disk storage.

[0160] Specifically, program 1005 can be called by processor 1001 to enable industrial control equipment 1000 to perform data communication method operations of hybrid deployed operating system.

[0161] Some embodiments of this application provide a computer-readable storage medium storing at least one executable instruction that, when executed on an industrial control device 1000, causes the industrial control device 1000 to perform the data communication method of the hybrid deployment operating system described in the above embodiments.

[0162] Specifically, the executable instructions can be used to enable the industrial control equipment 1000 to perform data communication methods of the hybrid deployed operating system.

[0163] For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device.

[0164] The beneficial effects that the readable storage medium provided in some embodiments of this application can achieve can be referred to the beneficial effects in the corresponding data communication method of the hybrid deployment operating system provided above, and will not be repeated here.

[0165] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0166] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0167] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0168] For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0169] More specific examples (a non-exhaustive list) of computer-readable media include the following: electrical connections having one or more wires (electronic devices), portable computer disks (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM).

[0170] Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory. It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof.

[0171] In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0172] The embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A data communication method for hybrid operating system deployment, applied to industrial control equipment, characterized in that, The method includes: The inter-process shared memory shared by processes of a non-real-time operating system and the target shared memory corresponding to a target real-time operating system are determined. The inter-process shared memory is used to store lock signals; the lock signals are used to indicate the accessibility status of the target shared memory; the target shared memory is memory shared by a first processor core and a second processor core; the first processor core is used to run the non-real-time operating system; the second processor core is used to run the target real-time operating system; and the inter-process shared memory and the target shared memory are independent memory regions. Obtain the lock signal corresponding to the target shared memory located in the inter-process shared memory, so as to determine the accessibility status of the target shared memory based on the lock signal; When the target shared memory is in an accessible state, data and the length of the data are written to the target shared memory based on the memory address of the target shared memory; The resource management process sends a first interrupt signal to the second processor core; wherein the first interrupt signal is used to instruct the target real-time operating system based on the length of the data and the memory address of the target shared memory, and the resource management process is located in the non-real-time operating system; In response to the first interrupt signal, the data is read from the target shared memory based on the data length and the memory address of the target shared memory.

2. The method according to claim 1, characterized in that, Before writing the data and the length of the data into the target shared memory based on the lock signal and the memory address of the target shared memory, the method further includes: Obtain the address of the inter-process shared memory; Based on the address of the inter-process shared memory, obtain the lock signal from the inter-process shared memory; Based on the lock signal, it is determined whether the target shared memory is in an accessible state.

3. The method according to claim 2, characterized in that, Determining whether the target shared memory is in an accessible state based on the lock signal includes: Determine whether the lock signal is a first signal; wherein the first signal is used to indicate that the target shared memory is in an accessible state; When the lock signal is the first signal, it is determined that the target shared memory is in an accessible state.

4. The method according to claim 3, characterized in that, The method further includes: The lock signal is updated to a second signal using an atomic operation; wherein the second signal is used to indicate that the target shared memory is in an inaccessible state.

5. The method according to claim 3 or 4, characterized in that, The target shared memory includes a first target shared memory and a second target shared memory; When the target shared memory is in an accessible state, writing data and the length of the data into the target shared memory based on the address of the target shared memory includes: When the target shared memory is in an accessible state, the data is written to the first target shared memory based on the address of the first target shared memory; Based on the address of the second target shared memory, the length information of the data is written into the second target shared memory.

6. The method according to claim 1, characterized in that, The method further includes: In response to a second interrupt signal sent by the second processor core, the length of the return message is obtained from the target shared memory based on the lock signal and the memory address of the target shared memory; wherein, the second interrupt signal is used to instruct the non-real-time operating system to read the return message from the target shared memory; the return message may or may not be related to the data; Based on the memory address of the target shared memory and the length of the returned message, the returned message is read from the target shared memory through the non-real-time operating system.

7. The method according to claim 6, characterized in that, The target shared memory includes a third target shared memory and a fourth target shared memory; the second interrupt signal is used to instruct the non-real-time operating system to read a return message from the third target shared memory; The step of responding to the second interrupt signal sent by the second processor core, and obtaining the length of the return message from the target shared memory based on the lock signal and the memory address of the target shared memory, includes: In response to the second interrupt signal sent by the second processor core, the length of the return message is obtained from the third target shared memory based on the lock signal and the memory address of the third target shared memory; The step of reading the return message from the target shared memory based on the memory address of the target shared memory and the length of the return message through the non-real-time operating system includes: Based on the memory address of the fourth target shared memory and the length of the returned message, the returned message is read from the fourth target shared memory through the non-real-time operating system.

8. The method according to any one of claims 1-7, characterized in that, Determine the target shared memory corresponding to the target real-time operating system, including: Obtain the identifier of the target real-time operating system; Based on the identifier of the target real-time operating system and the preset mapping relationship, the target shared memory is determined; wherein, the preset mapping relationship is used to indicate the mapping relationship between the real-time operating system and the corresponding inter-core shared memory, the real-time operating system includes the target real-time operating system, and the inter-core shared memory includes the target shared memory.

9. An industrial control device, characterized in that, include: Memory and processor; The memory and processor are coupled; Memory, used to store program instructions; The processor is used to execute the program instructions to cause the industrial control equipment to perform the data communication method of the hybrid deployment operating system as described in any one of claims 1-8.

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