Table lookup method based on RISC-V architecture, electronic device, readable medium and program product

Abstract

The present disclosure provides a table lookup method based on RISC-V architecture, comprising: receiving a virtual address sent by a processor, and searching a level 2 translation lookaside buffer (L2TLB); in a case where a leaf page table corresponding to the virtual address is hit in the L2TLB, returning a target physical address corresponding to the virtual address, access protection information and security information of the target physical address to a level 1 translation lookaside buffer (L1TLB), wherein the access protection information and the security information of the target physical address are stored in the L2TLB. The present disclosure also provides an electronic device, a readable medium and a program product.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a table lookup method, electronic device, readable medium, and program product based on RISC-V architecture. Background Technology

[0002] The security of the fifth-generation Reduced Instruction Set Compute-five (RISC-V) is implemented based on the CoVE framework, which essentially protects security components through isolation. The CoVE architecture supports the Trusted Execution Environment Security Manager (TSM) through Instruction Set Architecture (ISA) and non-ISA extensions, and provides temporal and spatial isolation to security applications, preventing access by the host operating system or hypervisor.

[0003] In the CoVE framework, access protection extensions for the Supervisor Domain are achieved through the Root Domain Security Manager (RDSM) in M ​​mode, which programs access policies for operations within the Supervisor Domain. The Machine-level Memory Protection Tables (SMMPT) module enables RDSM to program permissions for physically addressed memory (or device-mapped regions) for addressable remote sensor high-speed channels (HARTs) or devices operating within the Supervisor Domain. Specifically, RDSM restricts and manages access to the Memory Protection Tables (MPTs). Any access to physically addressable regions occurring within the Supervisor Domain context is subject to access checks. Therefore, in secure mode, RDSM not only translates virtual addresses but also checks the security access permissions for physical addresses. However, the current high number of page table lookups reduces the efficiency of memory management. Summary of the Invention

[0004] This disclosure provides a table lookup method, electronic device, readable medium, and program product based on a RISC-V architecture.

[0005] In a first aspect, embodiments of this disclosure provide a table lookup method based on a RISC-V architecture, comprising:

[0006] Receive the virtual address sent by the processor and look up the L2TLB (Level 2 Translation Bypass Buffer).

[0007] If the leaf page table corresponding to the virtual address is hit in the L2TLB, the target physical address corresponding to the virtual address, the access protection information and security information of the target physical address are returned to the first-level translation bypass buffer L1TLB, and the access protection information and security information of the target physical address are stored in the L2TLB.

[0008] Secondly, embodiments of this disclosure provide an electronic device, which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the table lookup methods based on the RISC-V architecture provided in embodiments of this disclosure.

[0009] Thirdly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the table lookup methods based on the RISC-V architecture provided in embodiments of this disclosure.

[0010] Fourthly, embodiments of this disclosure provide a computer program product, which includes a computer program that, when executed by a processor, implements any of the RISC-V architecture-based lookup methods provided in embodiments of this disclosure.

[0011] The table lookup method based on RISC-V architecture provided in this embodiment receives a virtual address sent by the processor and searches the Level 2 Translation Bypass Buffer (L2TLB). Since the L2TLB stores the target physical address and its access protection and security information, when the leaf page table corresponding to the virtual address is hit in the L2TLB, not only the target physical address but also its access protection and security information can be obtained. This eliminates the need to look up the physical address again to obtain its security and address protection information, thus reducing the number of table lookups and the time required, thereby improving memory management efficiency. Attached Figure Description

[0012] In the accompanying drawings of the embodiments disclosed herein:

[0013] Figure 1 This diagram illustrates a flowchart of address translation performed by a memory management unit in the related art.

[0014] Figure 2 A flowchart of a table lookup method based on a RISC-V architecture is provided for embodiments of this disclosure;

[0015] Figure 3A flowchart of a table lookup process for an MPT module is shown;

[0016] Figure 4 A flowchart illustrating another table lookup method based on the RISC-V architecture provided in this disclosure embodiment is shown.

[0017] Figure 5 This diagram illustrates a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0019] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0020] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0021] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0024] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0025] Figure 1 This diagram illustrates a flowchart of address translation performed by a memory management unit in related technologies. For example... Figure 1 As shown, the steps of the memory management unit in translating between virtual addresses and physical addresses include:

[0026] Step S101: Convert the virtual address to the target physical address.

[0027] In region A, a lookup table is performed based on the Virtual Address (VA), the Physical Page Number (PPN) of the MPT, and the Supervisor Domain Identifier (SDID) to obtain the target physical address. When virtualization is enabled, both first-level and second-level table lookups are performed. When virtualization is disabled, only a first-level table lookup is performed. This disclosure uses an example of enabling virtualization for illustration.

[0028] Step S102: Perform an address protection PMP check on the target physical address to confirm whether the target physical address has corresponding read / write / execute permissions.

[0029] The PMP module's registers store physical addresses and their access permission attributes. When the target physical address is located in the PMP module's registers, its access permission attributes are used to determine if it has the corresponding read / write / execute permissions. If it has read / write / execute permissions, the target physical address passes the protection check; otherwise, access fails, and access to the target physical address is not permitted.

[0030] Step S103: Perform an MPT query on the target physical address to confirm whether the target physical address is secure.

[0031] If the system requires security applications, the MPT module performs a security check on the target physical address. If the target physical address is secure, the security check is passed; if the target physical address is insecure, the access fails and access to the target physical address is not allowed.

[0032] After the above steps S101 to S103, not only is the address translation completed, that is, the destination physical address is obtained, as well as the protection check and security check of the destination physical address.

[0033] It should be noted that even when virtualization is not enabled, security and protection checks can still be performed after a first-level table lookup.

[0034] In the RISC-V architecture Sv48+Sv48×4 mode, during the virtual address to physical address translation process, each page table walk (PTW) requires approximately three memory protection table (MPT) queries. Moreover, after the last PTW query retrieves the main physical address leaf page table, a security access check is also required on the final leaf page table. Therefore, completing a complete physical address lookup requires approximately 99 page table queries, which consumes a significant amount of time.

[0035] In safe mode, the L2TLB (Level 2 Translation Bypass Cache) takes longer to look up the page table. The Page Table Transition (PTW) lookup request is initiated by the bypass cache to query the Page Table Entry (PTE) data in the memory space. This process also requires multiple cycles, increasing the time overhead of the translation between virtual and physical addresses and reducing the efficiency of memory management.

[0036] In a first aspect, embodiments of this disclosure provide a table lookup method based on the RISC-V architecture.

[0037] Figure 2 This document provides a flowchart of a table lookup method based on a RISC-V architecture, as an embodiment of this disclosure. Figure 2 As shown,

[0038] Step S201: Receive the virtual address sent by the processor and locate the Level 2 Translation Bypass Buffer (L2TLB).

[0039] The processor in the system sends a virtual address to the MMU. After receiving the virtual address, the MMU searches for the virtual address in the L2TLB to determine whether the leaf page table can be found.

[0040] In step S202, if the leaf page table corresponding to the virtual address is hit in L2TLB, the target physical address corresponding to the virtual address, the access protection information and security information of the target physical address are returned to the first-level translation bypass buffer L1TLB, and the access protection information and security information of the target physical address are stored in L2TLB.

[0041] In this embodiment, the access protection information and security information of the target physical address are stored in the L2TLB. The access protection information and security information of the target physical address can be obtained by directly hitting the leaf page table in the L2TLB. Since the hit rate of the L2TLB can reach more than 90%, the probability of hitting the access protection information and security information of the target physical address can also be more than 90%, saving the time of querying the MPT_SRAM module and the MPT module, thereby improving the working efficiency of the memory management unit.

[0042] In this embodiment, the MPT module is based on the RISC-V Supervisor Domains Access Protection architecture, version v0.1.2, and supports bare mode and smmpt56 mode. In bare mode, security mode checks are disabled, and the security mode can be switched as needed. In smmpt56 mode, security mode checks are enabled, and read, write, and execute permissions are determined, providing security checks based on these permissions. This embodiment provides a specified lookup table method applicable to all high-performance processors supporting the SMMPT security architecture.

[0043] Figure 3 This illustrates a table lookup flowchart for an MPT module. For example... Figure 3 As shown, if the security table retrieved by MPTL3 is of type table and not the final leaf page table entry, the lookup result of MPTL3 is not within the scope of MPT security permission checks and points to the next level security page table location. The data returned by MPTL2 and MPTL1 may both be leaf entries, and the leaf entry information can be backfilled and stored in L2TLB and MPT_SRAM.

[0044] In this embodiment, the lookup of the security page table and the storage of security information corresponding to the physical address are independent. The final security information is stored not only in MPT_SRAM but also in L2TLB, realizing the relative coupling of MPT and L2TLB. In this way, when the system issues a virtual address to query the L2TLB page table, the security check result can be obtained at the same time as the target physical address is hit, which shortens the table lookup time in security scenarios.

[0045] In some embodiments, the table lookup method provided in this disclosure further includes:

[0046] In the case of a missing leaf page table in L2TLB, the intermediate physical address to be looked up is calculated, and a security check and address protection PMP check are performed on the intermediate physical address. The intermediate physical address is the address of the page table where the target physical address is located.

[0047] In the event that the leaf page table is not hit in the L2TLB, the intermediate physical address that needs to be looked up is calculated. This embodiment does not limit the method for calculating the intermediate physical address. After obtaining the intermediate physical address, a security check and an address protection PMP check are performed on the intermediate physical address to obtain secure access permissions for the intermediate physical address.

[0048] If security checks on the intermediate physical address are not possible, a page table traversal PTW query request for MPT is initiated to the intermediate physical address to obtain the first leaf page table, which includes the security information of the intermediate physical address.

[0049] In some embodiments, after obtaining the first leaf page table, the method further includes: storing security information of the intermediate physical address in the random access memory (SRAM) of the L2TLB and the memory protection page table (MPT).

[0050] If the intermediate physical address has access permissions, a PTW query request for the page table entry PTE is initiated to the intermediate physical address to obtain the second leaf page table, which includes access protection information for the target physical address.

[0051] In some embodiments, after obtaining the second leaf page table, the method further includes: storing access protection information of the target physical address in an L2TLB.

[0052] In some embodiments, address protection PMP checks are performed on intermediate physical addresses, including: querying the access protection information of the intermediate physical address in the registers of the PMP module; and determining whether the intermediate physical address has access permissions based on the access protection information of the intermediate physical address.

[0053] It should be noted that if the PMP check fails, no further security checks will be performed.

[0054] In this embodiment of the disclosure, the access protection information of the intermediate physical address is stored in the register of the PMP module, and it can be determined whether the intermediate physical address has access rights based on the access protection information of the intermediate physical address.

[0055] In some embodiments, performing a security check on the intermediate physical address includes: if security information of the intermediate physical address is found in the random access memory (SRAM) of the memory protected page table (MPT), determining the security of the intermediate physical address based on the security information.

[0056] In some embodiments, if the security information of the target physical address is found in the random access memory (SRAM) of the memory protection page table (MPT), after obtaining the first leaf page table, the security information of the target physical address and the access protection information are stored together in the L2TLB.

[0057] In some embodiments, if the security information of the target physical address is not found in the random access memory (SRAM) of the memory protection page table (MPT), an access protection check is performed on the intermediate physical address, and then a PTW query request for the MPT and a PTW query request for the PTE are initiated.

[0058] To better understand this disclosure, the following is in conjunction with the appendix. Figure 4 The table lookup method is described in detail.

[0059] Figure 4 A flowchart illustrating another table lookup method based on the RISC-V architecture provided in an embodiment of this disclosure is shown. Figure 4 As shown, the table lookup method based on the RISC-V architecture includes:

[0060] Step S401: Receive the missed virtual address (miss VA) sent by the processor and search the L2TLB (Level 2 Translation Bypass Buffer).

[0061] In step S402, if the leaf page table is directly hit, the access protection information and security information of the physical address corresponding to the virtual address are directly returned to the L1TLB.

[0062] In step S403, if the leaf page table is not hit in L2TLB, the virtual address is sent to the Trusted Service Manager (TSM). The TSM calculates the intermediate physical address that needs to be looked up and sends the intermediate physical address to the PMP module and MPT_SRAM.

[0063] In step S404, the PMP module performs a physical address protection check on the intermediate physical address.

[0064] Step S405: Locate the intermediate physical address in SRAM and check whether a security check was performed on the intermediate physical address in a previously processed transaction.

[0065] If the security information for the intermediate physical address can be found in SRAM, then the PMP's PTW query result needs to be waited for. The security information and the PTW query result are then sent together to L2TLB storage.

[0066] In step S406, the MPT module fails to find the intermediate physical address in the SRAM. After the PMP performs a protection check on the intermediate physical address, it initiates a PTW query request for the MPT to obtain the first leaf page table.

[0067] In step S407, after the PMP module passes the protection check of the intermediate physical address, it initiates a PTW query for the PTE to obtain the second leaf page table.

[0068] Step S408: Store the security information and access protection information of the intermediate physical address into the L2TLB, and return the virtual address to physical address conversion and related information to the L1TLB.

[0069] Through steps S401 to S408, the relative coupling between MPT and L2TLB is achieved.

[0070] Table 1 shows different scenarios for table lookup and backfilling after the relative coupling of MPT and L2TLB is implemented.

[0071]

[0072] In Table 1, scenario A is when the L2TLB page table is not hit and the physical address security information is not stored in MPT_SRAM. In this case, PTE_PTW query and MPT_PTW query will be initiated. The returned page table and security table read / write / execution information needs to be stored in L2TLB and MPT_SRAM.

[0073] In scenario B, if the L2TLB page table is not hit, and the MPT_SRAM contains the PPN information of the next-level MPT access table of the physical address, a PTE_PTW query and an MPT PTW query will be initiated. The returned page table and security table read / write / execution information need to be stored in the L2TLB and MPT_SRAM.

[0074] In scenario C, if the L2TLB page table is not hit and the MPT_SRAM contains the security information of the physical address, a PTE_PTW query will be initiated. The returned page table and security table read / write / execution information needs to be stored in the L2TLB.

[0075] In scenario D, if the L2TLB hits a TABLE type page table but the MPT_SRAM does not contain security information for the physical address, a PTE_PTW query and an MPT_PTW query will be initiated. The returned page table and security table read / write / execution information needs to be stored in the L2TLB and MPT_SRAM.

[0076] In scenario E, if the L2TLB hits a TABLE type page table and the MPT_SRAM contains the PPN information of the next-level MPT walk table of the physical address, then a PTE_PTW query and an MPT_PTW query will be initiated. The returned page table and security table read / write / execution information needs to be stored in the L2TLB and MPT_SRAM.

[0077] If scenario F involves an L2TLB hitting a TABLE type page table and the MPT_SRAM contains security information about the physical address, a PTE_PTW query will be initiated. The returned page table and security table read / write / execution information needs to be stored in the L2TLB.

[0078] If scenario G is an L2TLB hit on the leaf page table and the MPT_SRAM does not contain security information for the physical address, then there is no need to initiate PTE_PTW queries and MPT_PTW queries, nor is it necessary to store the returned page table and security table read / write / execution information in L2TLB and MPT_SRAM.

[0079] As shown in Table 1, in scenario G, during address translation, it is no longer necessary to access MPT_SRAM. Security information for the physical address can be directly obtained from the L2TLB, and access permissions can be determined. If the L2TLB and MPT are completely independent lookup and storage systems, and both the L2TLB and MPT have found the final leaf page table, then querying the L2TLB requires 3 clock cycles, and querying the MPT_SRAM also requires 3 clock cycles, for a total of 6 clock cycles. However, the table lookup method provided in this disclosure, because the L2TLB stores security information, only requires 3 clock cycles to complete the L2TLB query, reducing the lookup time by 50%. This reduces the virtual address to physical address lookup time and improves memory management efficiency.

[0080] The table lookup method provided in this disclosure is applicable to Trusted Execution Environments (TEEs) based on the RIC-V architecture, in order to protect data security in different hypervisor domains for system-on-a-chip (SOC) or other security application scenarios based on the RIC-V architecture.

[0081] Secondly, embodiments of this disclosure provide an electronic device.

[0082] Figure 5 This diagram illustrates a block diagram of an electronic device provided in an embodiment of the present disclosure. Figure 5 As shown, an electronic device provided in this embodiment includes a processor 501 and a memory 502; the memory 502 stores a computer program that can be executed by the processor 501, and when the computer program is executed by the processor 501, it implements any of the RISC-V architecture-based lookup methods in this embodiment.

[0083] In some embodiments, the electronic device further includes an I / O interface (read / write interface) 503, which is connected between the processor 501 and the memory 502 and enables information interaction between the memory 502 and the processor 501. The I / O interface 503 includes, but is not limited to, a data bus.

[0084] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, enabling information exchange between the memory and the processor, including but not limited to the data bus (Bus).

[0085] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0086] This disclosure also provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the RISC-V architecture-based lookup methods described in the above embodiments.

[0087] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements any of the RISC-V architecture-based lookup methods described in the above embodiments.

[0088] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0089] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0090] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0091] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0092] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A table lookup method based on RISC-V architecture, characterized in that, include: The processor receives a virtual address sent by the processor and searches for the Level 2 Translation Bypass Buffer (L2TLB); the processor includes a processor with an SMMPT security architecture. If the leaf page table corresponding to the virtual address is hit in the L2TLB, the target physical address corresponding to the virtual address, the access protection information and security information of the target physical address are returned to the first-level translation bypass buffer L1TLB, and the access protection information and security information of the target physical address are stored in the L2TLB.

2. The method according to claim 1, characterized in that, Also includes: If the leaf page table is not hit in the L2TLB, the intermediate physical address that needs to be looked up is calculated, and the intermediate physical address is subjected to security checks and address protection PMP checks. The intermediate physical address is the address of the page table where the target physical address is located. If a security check of the intermediate physical address is not possible, a page table traversal PTW query request for the memory protection page table (MPT) is initiated to the intermediate physical address to obtain a first leaf page table, which includes the security information of the intermediate physical address. If the intermediate physical address has access permissions, a PTW query request for the page table entry PTE is initiated to the intermediate physical address to obtain the second leaf page table, which includes the access protection information of the target physical address.

3. The method according to claim 2, characterized in that, The address protection PMP check performed on the intermediate physical address includes: Query the access protection information of the intermediate physical address in the registers of the PMP module; Whether the intermediate physical address has access permissions is determined based on the access protection information of the intermediate physical address.

4. The method according to claim 2, characterized in that, After obtaining the second leaf page table, the process also includes: The access protection information of the target physical address is stored in the L2TLB.

5. The method according to claim 2, characterized in that, The security check on the intermediate physical address includes: If the security information of the intermediate physical address is found in the random access memory (SRAM) of the memory protected page table (MPT), the security of the intermediate physical address is determined based on the security information.

6. The method according to claim 2, characterized in that, After obtaining the first leaf page table, the process also includes: The security information of the intermediate physical address is stored in the random access memory (SRAM) of the L2TLB and the memory protection page table (MPT).

7. The method according to claim 2, characterized in that, If the security information of the target physical address is found in the random access memory (SRAM) of the memory protected page table (MPT), after obtaining the first leaf page table, the security information of the target physical address and the access protection information are stored together in the L2TLB. And / or, if the security information of the target physical address is not found in the random access memory (SRAM) of the memory protection page table (MPT), after performing an access protection check on the intermediate physical address, a PTW query request for the MPT and a PTW query request for the PTE are initiated.

8. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

9. A computer-readable medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the table lookup method based on the RISC-V architecture as described in any one of claims 1 to 7.

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