A multiprocessor system, a data transmission method, and an electronic device

Abstract

This application belongs to the field of electronic technology, specifically relating to a multiprocessor system and data transmission method, and an electronic device. The multiprocessor system includes: multiple processors, each processor connected via a peer port; each processor includes: a computing core, a DMA module, and a peer port; the computing core is used to send access-related information to the DMA module, the access-related information including a target peer port; the DMA module is used to read corresponding first access data based on the access-related information and send the first access data to a first processor connected to the target peer port. This application can achieve high-performance communication without sacrificing processor computing throughput, thereby improving the problems existing in current multiprocessor systems.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a multiprocessor system and data transmission method, and electronic equipment. Background Technology

[0002] With the development of AI (Artificial Intelligence) technology, especially deep learning and large models, higher demands are being placed on computing systems. To meet the growing needs of computationally intensive, high-throughput, and high-reliability applications, multiprocessor systems have emerged.

[0003] In multiprocessor systems, cross-processor data communication is crucial. However, deep learning tasks frequently involve such communication interactions, and their overhead has become a key bottleneck limiting the performance of distributed deep learning. Assuming a multiprocessor system includes GPU A and GPU B, the current principle of cross-GPU (Graphics Processing Unit) data communication is as follows: Figure 1 As shown, the process includes the following steps: 1) The Streaming Multiprocessor (SM) in GPUA copies the data to be transferred from memory (MEM) to the SM's cache; 2) The SM transfers the copied data to GPUB; 3) GPUB stores the data in GPUB's memory. Because the SM's cache space is limited, this communication method only supports small-batch data transfers, resulting in low network bandwidth utilization and interference with computational tasks on the processor, leading to decreased computational efficiency. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a multiprocessor system and data transmission method and electronic device that can achieve high-performance communication without sacrificing processor computing throughput.

[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a multiprocessor system, including: a plurality of processors, each of the plurality of processors being connected via a Peer port; each processor including: a computing core, a DMA module, and a Peer port; the computing core being configured to send access-related information to the DMA module, the access-related information including a target Peer port; the DMA module being configured to read corresponding first access data based on the access-related information and send the first access data to a first processor connected to the target Peer port.

[0006] In the above embodiments, each processor is connected via a Peer port, enabling efficient peer-to-peer (P2P) transmission. Simultaneously, cross-processor data transfer is achieved through internal DMA controlled by internal processor threads (such as threads within the computing cores). The entire process requires no CPU (Central Processing Unit) intervention, reducing communication overhead without affecting processor computation. This allows for high-performance communication without sacrificing processor throughput, thus addressing the problems of existing multiprocessor systems. Furthermore, this transmission method is no longer limited by… Figure 1 The cache space limitation of SM can support large-volume data transfer.

[0007] In one possible implementation of the first aspect embodiment, the access-related information further includes a destination offset; the DMA module is further configured to: add the destination offset to the first access data to obtain second access data; and send the second access data to the first processor connected to the target Peer port.

[0008] In the above embodiments, by adding a destination offset to the first access data, data transmission across multiple processors can be achieved, rather than just point-to-point data transmission, thereby improving data transmission efficiency and meeting the communication needs of more complex scenarios.

[0009] In one possible implementation of the first aspect embodiment, each processor is further configured to: receive the second access data; if the destination offset in the second access data is the offset of the current processor, then write the second access data after removing the destination offset into the storage space corresponding to the current processor; if the destination offset in the second access data is not the offset of the current processor, then send the second access data to the second processor through the Peer port; wherein the second processor is the next processor located on the transmission path from the current processor to the destination processor and connected to the current processor, and the destination processor is the processor corresponding to the destination offset.

[0010] In the above embodiments, after receiving the second access data, each processor determines whether to continue forwarding the second access data by judging whether the destination offset in the second access data is the offset of the current processor itself. Each processor processes the data in the same way, so that the second access data can be forwarded to the destination processor, thus achieving efficient data transmission across multiple processors.

[0011] In one possible implementation of the first aspect embodiment, the computing core includes: a streaming multiprocessor and a driver module connected to a DMA module; the streaming multiprocessor is used to send access instructions; the driver module is used to parse each access instruction after receiving it, and send the parsed access-related information to the DMA module.

[0012] In the above embodiments, in order to achieve high-performance cross-processor data transfer, a new driver module is added, and the DMA module is started through the driver module. This enables the DMA module to achieve cross-processor data transfer without the intervention of the CPU (Central Processing Unit). In this way, the SM only needs to issue access instructions and no longer participates in other inter-chip communication, so as not to cause SM resource occupation or reduction of SM resources used for computing.

[0013] In one possible implementation of the first aspect embodiment, the number of DMA modules is multiple; the driver module is specifically configured to: parse each access instruction in the order in which each access instruction is received, and send the parsed access-related information to an idle DMA module.

[0014] In the above embodiments, by setting up multiple DMA modules, the driver module parses each access instruction in the order in which they are received, and sends the parsed access-related information to the idle DMA module. This improves access efficiency and ensures that data, tasks, or instructions are processed correctly in the expected order by processing them in the order in which they are sent.

[0015] In one possible implementation of the first aspect embodiment, the driving module includes: an input queue and a command parsing unit; the input queue is used to temporarily store access instructions from the streaming multiprocessor; the command parsing unit is used to obtain the access instructions in the input queue in a first-in-first-out order, parse the obtained access instructions, and send the parsed access-related information to the idle DMA module.

[0016] In the above implementation, an input queue is set up to temporarily store access instructions from the streaming multiprocessor to prevent instruction loss when the processing speed of the DMA module is insufficient. At the same time, a command parsing unit is set up to parse the access instructions and thereby start the DMA module to realize cross-processor data transfer.

[0017] In one possible implementation of the first aspect embodiment, the number of DMA modules is multiple, the access instruction includes a DMA identifier, and the driver module is specifically configured to: determine the idle DMA module according to the state of each DMA module; parse an access instruction whose DMA identifier matches the DMA identifier of the idle DMA module, and send the parsed access-related information to the idle DMA module.

[0018] In the above implementation, a DMA identifier can be added to the access instruction so that the access instruction can only be executed by the specified DMA module. By first identifying the idle DMA module and then selecting the access instruction with the same DMA identifier for parsing based on the idle DMA module, it is beneficial to realize complex data communication and improve the system's concurrent processing capability.

[0019] In one possible implementation of the first aspect embodiment, the driving module includes: multiple input queues, an arbitration unit, and a command parsing unit; each input queue is used to temporarily store access instructions with the same DMA identifier from the streaming multiprocessor; the arbitration unit is used to determine the idle DMA module according to the state of each DMA module, and to obtain access instructions in the input queue whose DMA identifier matches the DMA identifier of the idle DMA module in a first-in-first-out order; the command parsing unit is used to parse the received access instructions and send the parsed access-related information to the idle DMA module.

[0020] In the above implementation, by setting up multiple input queues, each input queue temporarily stores only access instructions with the same DMA identifier. At the same time, after the arbitration unit determines the idle DMA module, it arbitrates the access instructions in the multiple input queues according to the idle DMA module to determine the current priority execution order of each input queue. The input queue containing the access instructions whose DMA identifier matches the DMA identifier of the idle DMA module is selected first. Then, the access instructions in the input queue are obtained in a first-in-first-out order and sent to the command parsing unit for parsing, so that the specified DMA module can execute the specified access instruction.

[0021] In one possible implementation of the first aspect embodiment, the number of DMA modules is multiple, and the driving module is specifically used to: parse each access instruction according to the order in which each access instruction is received to obtain access-related information; if the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy, temporarily store the currently parsed access-related information, and send the temporarily stored access-related information to the corresponding idle DMA module when the DMA module corresponding to the DMA identifier is idle.

[0022] In the above embodiments, the access instructions can be parsed in the order they are received, and then it can be determined whether the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy. If busy, the access-related information of the currently parsed access instruction is temporarily stored. When the DMA module corresponding to the DMA identifier is idle later, the previously stored access-related information is sent to the corresponding idle DMA module. In this way, the specified DMA module can be used to execute the specified access instruction.

[0023] In one possible implementation of the first aspect embodiment, the driving module includes: a first input queue, a second input queue, and a command parsing unit; the first input queue is used to temporarily store access instructions from the streaming multiprocessor; the command parsing unit is used to obtain the access instructions in the first input queue in a first-in-first-out order, and parse the obtained access instructions; if the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy, the access-related information of the currently parsed access instruction is temporarily stored in the second input queue; the command parsing unit is also used to send the temporarily stored access-related information to the corresponding idle DMA module when the DMA module corresponding to the DMA identifier is idle.

[0024] In the above embodiments, two input queues can be set up to temporarily store access instructions and parsed access-related information respectively, so as to prevent instruction loss when the processing speed of the DMA module is insufficient. At the same time, a command parsing unit is set up to parse the access instructions and use it to start the DMA module to realize cross-processor data transfer.

[0025] Secondly, embodiments of this application also provide an electronic device, including a multiprocessor system provided as described in the first aspect embodiments and / or any possible implementation in conjunction with the first aspect embodiments.

[0026] Thirdly, embodiments of this application also provide a data transmission method applied to a multiprocessor system. The method includes: any processor in the multiprocessor system reads first access data, adds a destination offset to the first access data to obtain second access data, and sends the second access data to the first processor through a Peer port; the first processor receives the second access data, and if the destination offset in the second access data is not the offset of the first processor, then sends the second access data to the second processor through the Peer port; wherein the second processor is the next processor located on the transmission path from the first processor to the destination processor and connected to the first processor, and the destination processor is the processor corresponding to the destination offset.

[0027] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0029] Figure 1 This is a schematic diagram illustrating the interaction principle of cross-processor data communication in existing multiprocessor systems.

[0030] Figure 2a A schematic diagram of the structure of a multiprocessor system provided in an embodiment of this application is shown.

[0031] Figure 2b A schematic diagram of the structure of a multi-GPU system provided in an embodiment of this application is shown.

[0032] Figure 3 This illustration shows a schematic diagram of the connection between the first type of driver module and DMA module provided in an embodiment of this application.

[0033] Figure 4 This paper illustrates a schematic diagram of the connection between a second type of driver module and a DMA module provided in an embodiment of this application.

[0034] Figure 5 This paper illustrates a schematic diagram of the connection structure between a third type of driver module and a DMA module provided in an embodiment of this application.

[0035] Figure 6 A schematic flowchart of a data transmission method provided in an embodiment of this application is shown. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0037] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0038] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0039] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0040] Given the problems existing in current multiprocessor systems when conducting cross-processor data communication, such as low network bandwidth utilization and interference with computational tasks on the processor, leading to decreased computational efficiency, this application provides a novel multiprocessor system that achieves cross-processor data transfer by controlling internal DMA through threads within the processor (threads of the computing cores). The entire process requires no CPU (Central Processing Unit) intervention, reducing communication overhead without affecting processor computation, and achieving high-performance communication without sacrificing processor throughput.

[0041] The multiprocessor system provided in this application includes multiple (two or more) processors. Each of the multiple processors is connected to at least one processor through a Peer port, enabling peer-to-peer (P2P) transmission. Its schematic diagram is shown below. Figure 2a As shown. Figure 2a The example diagram shown contains four processors: processor A, processor B, processor C, and processor D. Each pair of processors is interconnected via a peer port.

[0042] It should be noted that a multiprocessor system must have at least two processors. When there are more than two processors, there are various ways to connect them, such as serial, fully connected, or partially serial and partially fully connected. The specific connection depends on the design requirements.

[0043] In a multiprocessor system, the multiple processors can be of the same type, such as all being GPUs, or they can include different types of processors, such as some being GPUs and some being processors other than GPUs.

[0044] In some possible implementations, the processor in a multiprocessor system includes, but is not limited to: GPU, Network Processor (NP), Accelerated Processing Unit, Multimedia Application Processor (MAP), microprocessor, etc.; it can also be Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; it can also be other conventional processors, etc.

[0045] The following will combine Figure 2b The multiprocessor system provided in the embodiments of this application will be described. Figure 2b Only a scenario with four GPUs (GPUA, GPUB, GPUC, and GPUD) is shown. GPUA is connected to GPUB and GPUD via a Peer port, and GPUB and GPUC are connected via a Peer port. The processors in this application are not limited to GPUs, and the number of processors is not limited to four. Therefore, the following cannot be used to describe the situation where... Figure 2b The GPUs and the number of GPUs shown are to be understood as limitations of this application. Furthermore, Figure 2b The example shown only illustrates the case of four GPUs connected in series. The connection between processors is not limited to series; it can be fully connected or other mainstream connection methods.

[0046] Each processor includes a computing core, a DMA (Direct Memory Access) module, and a peer port. Each processor has at least one computing core, one DMA module, and one peer port. In some possible implementations, there can be multiple DMA modules and peer ports, with each computing core connected to each DMA module, and each DMA module connected to each peer port. In other possible implementations, the number of DMA modules corresponds one-to-one with the number of peer ports, with each DMA module connected only to its corresponding peer port.

[0047] In some implementations, each processor may also include memory ( Figure 2b Not shown in the image, please refer to [link / reference]. Figure 1 In some possible implementations, the memory (MEM) may not belong to the processor (i.e., GPU) but may be a device independent of the processor, with each processor able to read data from external memory. This memory may be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0048] In some possible implementations, the computing core is used to send access-related information to the DMA module. The DMA module is used to read the corresponding first access data based on the access-related information and send the first access data to the first processor connected to the target peer port. The access-related information includes the target peer port, and also includes information needed to read the first access data, such as the access address and data length, so that the DMA module can read data of the same length from the memory space corresponding to the access address.

[0049] To enable data transfer across multiple processors, such as data transfer between GPUA and GPUB / C, the access information also includes a destination offset. In this case, the DMA module also adds the destination offset to the first accessed data to obtain the second accessed data, and then sends the second accessed data to the first processor connected to the target Peer port. When adding the destination offset, it can be added to the beginning or end of the first accessed data, or at another position agreed upon by both communicating parties.

[0050] In this implementation, each processor can correspond to an offset. The destination offset corresponding to the destination processor is added to the first access data. Then, the second access data (the first access data with the destination offset added) is sent to the first processor. Upon receiving the second access data, the first processor determines whether the destination offset in the second access data is the offset of the first processor. If the destination offset in the second access data is the offset of the first processor, the destination offset is removed from the second access data, and the second access data after removing the destination offset is written to the storage space corresponding to the first processor. If the destination offset in the second access data is not the offset of the first processor, the second access data is sent to the second processor through the Peer port. The second processor is the next processor located on the transmission path from the first processor to the destination processor and connected to the first processor.

[0051] After receiving the second access data, the second processor also processes it in the same way as the first processor. If the destination offset in the second access data is not the offset of the second processor, the second access data will be sent to the next processor connected to the second processor on the transmission path from the second processor to the destination processor. This process continues until the second access data is finally sent to the destination processor, thereby realizing data transmission across multiple processors and improving communication performance.

[0052] For example, when implementing data transfer between GPUA and GPUB / GPUC, after GPUA reads the first access data, it adds the offset of GPUC to the first access data to obtain the second access data. Then, it sends the second access data to GPUB. After receiving the second access data, GPUB finds that the offset in the second access data is not the offset of GPUB, so it sends the second access data to GPUC. After receiving the second access data, GPUC finds that the offset in the second access data is the offset of GPUC, so it removes the offset from the second access data and writes the second access data after removing the offset into the corresponding storage space of GPUC. This realizes the data transfer between GPUA and GPUB / GPUC.

[0053] If the access-related information also includes a destination offset, in this implementation, each processor is further configured to: receive second access data; if the destination offset in the second access data is the offset of the current processor, then write the second access data after removing the destination offset into the storage space corresponding to the current processor; if the destination offset in the second access data is not the offset of the current processor, then send the second access data to the second processor through the Peer port; wherein, the current processor is the processor that currently receives the second access data, the second processor is the next processor located on the transmission path from the current processor to the destination processor and connected to the current processor, and the destination processor is the processor corresponding to the destination offset.

[0054] Assuming the current processor is the first processor, after the second access data, if the destination offset in the second access data is the offset of the first processor, then the destination offset is removed from the second access data, and the second access data after removing the destination offset is written to the storage space corresponding to the first processor. If the destination offset in the second access data is not the offset of the first processor, then the second access data is sent to the second processor through the Peer port.

[0055] The computing core in a processor is the basic unit that performs actual computing tasks. Its core functions are instruction processing, data manipulation, and control flow. The structure of the computing core can differ between different types of processors; for example, the computing core of a GPU can differ from that of an NP (NP-based processor). In some possible implementations, the computing core includes a streaming multiprocessor (SM) and a driver module (SM_DMA_driver). The streaming multiprocessor is connected to the driver module, and the driver module is connected to each DMA module. Compared to... Figure 1 In the multiprocessor system shown, this application achieves high-performance cross-processor data transfer by adding a driver module and a DMA module. The driver module starts the DMA module, thereby enabling cross-processor data transfer without CPU (Central Processing Unit) intervention. This way, the SM (Semiconductor Module) only needs to issue access instructions and no longer participates in other inter-chip communication, thus avoiding SM resource consumption and reducing the amount of SM available for computation. Normally, the SM is used for computation; if it is used for… Figure 1 Inter-chip communication, as shown, leads to increased SM resource consumption, reducing the number of SMs available for computation and consequently decreasing computational efficiency.

[0056] The streaming multiprocessor is used to send access instructions. The driver module, upon receiving each access instruction, parses it and sends the parsed access-related information to the DMA module to initiate cross-processor data transfer. The driver module can parse each access instruction in a specified order. This specified order includes, but is not limited to, the order in which each access instruction is received; in some possible implementations, the specified order can also be a configured priority order.

[0057] The access instruction may include necessary information for reading the first access data (such as access address, data length, etc.), the target peer port, and may also include the destination offset and DMA identifier.

[0058] In the first implementation: if there are multiple DMA modules and the access instruction does not contain a DMA identifier, that is, each access instruction can be executed by any DMA module, then the driver module is specifically used to: parse each access instruction according to the order in which they are received, and send the parsed access-related information to the idle DMA module.

[0059] In some possible implementations under the first embodiment, such as Figure 3 As shown, the driver module includes an input queue and a command parsing unit. The input queue is connected to the streaming multiprocessor and the command parsing unit, respectively, and the command parsing unit is connected to each DMA module.

[0060] An input queue is used to temporarily store access instructions from the streaming multiprocessor. In some possible implementations, the streaming multiprocessor can directly store access instructions issued to the driver module into this input queue.

[0061] The command parsing unit is used to retrieve access commands from the input queue in a first-in-first-out order, parse the retrieved access commands, and send the parsed access-related information to the idle DMA module.

[0062] If the input queue described above is a first-in-first-out (FIFO) queue, the command parsing unit can retrieve the access instructions from the input queue sequentially. If the input queue described above is a random queue, in one possible implementation, the driver module further includes an arbitration unit, used to retrieve the access instructions from the input queue in a FIFO order and send the retrieved access instructions to the command parsing unit for parsing.

[0063] The arbitration unit and the command parsing unit can be parallel, and in some possible implementations, the arbitration unit can be integrated with the command parsing unit.

[0064] In the first implementation, the arbitration unit or command parsing unit can also be used to determine the idle DMA module based on the status of each DMA module.

[0065] Each DMA module can inform the arbitration unit or command parsing unit of its own status, which indicates whether the DMA module is idle or busy. When the DMA module is reading the first access data based on access-related information and has not yet sent it, it is in a busy state. When the DMA module has completed sending the first access data and is not participating in other tasks, it is in an idle state.

[0066] In the second implementation: if there are multiple DMA modules and the access instruction contains a DMA identifier, that is, each access instruction can only be executed by the specified DMA module, then the driver module is specifically used to: determine the idle DMA module according to the status of each DMA module; select the access instruction whose DMA identifier is consistent with the DMA identifier of the idle DMA module for parsing, and send the parsed access-related information to the idle DMA module.

[0067] In the second implementation, such as Figure 4 As shown, the driver module may include: multiple input queues, an arbitration unit, and a command parsing unit. The multiple input queues are connected to the streaming multiprocessor and the arbitration unit, respectively. The arbitration unit is connected to the command parsing unit, and the command parsing unit is connected to each DMA module. Furthermore, the arbitration unit is also connected to each DMA module.

[0068] Each input queue is used to temporarily store access instructions with the same DMA identifier from the streaming multiprocessor. This can be achieved by the streaming multiprocessor directly storing access instructions with the same DMA identifier into the same input queue when issuing access instructions, so that the access instructions in each input queue have the same DMA identifier.

[0069] The arbitration unit determines the idle DMA modules based on their status and retrieves access instructions from the input queue whose DMA identifier matches that of the idle DMA module, following a first-in-first-out (FIFO) order. After identifying the idle DMA modules, the arbitration unit arbitrates the access instructions in multiple input queues based on their availability to determine the current priority execution order of each input queue. It prioritizes the input queue containing access instructions whose DMA identifier matches that of the idle DMA module, then retrieves the access instructions from that queue in a FIFO order and sends them to the command parsing unit for parsing.

[0070] The command parsing unit is used to parse the received access command and send the parsed access-related information to the corresponding idle DMA module. After parsing the access command, the command parsing unit can obtain the DMA identifier contained in the access command, and then send the parsed access-related information to the DMA module corresponding to the DMA identifier.

[0071] In some possible implementations, the arbitration unit and the command parsing unit in the second implementation can be integrated together, such as the arbitration unit being integrated into the command parsing unit.

[0072] In the third implementation: if there are multiple DMA modules and the access instruction contains a DMA identifier, that is, each access instruction can only be executed by a specified DMA module, then the driver module is specifically used to: parse each access instruction according to the order in which they are received, obtain access-related information, and if the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy, temporarily store the currently parsed access-related information, and when the DMA module corresponding to the DMA identifier is idle, send the temporarily stored access-related information to the corresponding idle DMA module.

[0073] In the third implementation, such as Figure 5 As shown, the driver module may include a first input queue, a second input queue, and a command parsing unit. The first input queue is connected to the streaming multiprocessor and the command parsing unit, respectively. The command parsing unit is connected to each DMA module and the second input queue, respectively.

[0074] The first input queue is used to temporarily store access instructions from the streaming multiprocessor. In this implementation, access instructions with different DMA identifiers are temporarily stored in the same input queue.

[0075] The command parsing unit is used to retrieve access commands from the first input queue in a first-in-first-out (FIFO) order, parse the retrieved access commands, and if the DMA module corresponding to the DMA identifier in the currently parsed access command is busy, temporarily store the access-related information in the second input queue. When the DMA module corresponding to the DMA identifier becomes idle, the temporarily stored access-related information in the second input queue is sent to the corresponding idle DMA module.

[0076] In the third implementation, there can be multiple second input queues. Access-related information with the same DMA identifier is temporarily stored in the same input queue. In this way, when the corresponding DMA module is idle, the temporarily stored access-related information in the second input queue can be obtained in a first-in-first-out order and sent to the corresponding idle DMA module.

[0077] In one possible implementation, both the first and second input queues are first-in-first-out (FIFO) queues, allowing the command parsing unit to sequentially retrieve access instructions or access-related information from the input queues. If the first and second input queues are random queues, in one possible implementation, the driver module further includes an arbitration unit, used to retrieve access instructions from the first input queue in FIFO order, or retrieve access-related information from the second input queue in FIFO order, and send the retrieved access instructions and / or access-related information to the command parsing unit.

[0078] In this implementation, the arbitration unit and the command parsing unit can be parallel; in some possible implementations, the arbitration unit can be integrated with the command parsing unit. In a third implementation, the arbitration unit or the command parsing unit can also be used to determine the idle DMA modules based on the status of each DMA module.

[0079] In some possible implementations, access instructions can be partially missing a DMA flag, while others can include one, to enable complex data communication. For example, when executing a low-priority task, an access instruction without a DMA flag can be issued. When executing a high-priority task, a DMA flag can be added to the access instruction, allowing the driver module to prioritize access instructions with a DMA flag. In this approach, two input queues can be included: a first queue for temporarily storing access instructions without a DMA flag, and a second queue for temporarily storing access instructions with a DMA flag. When parsing access instructions, the driver module prioritizes those with a DMA flag, and only processes those without a DMA flag if no such instructions are available.

[0080] This application also provides a data transmission method, which is applied to the aforementioned multiprocessor system. The following describes the method in conjunction with... Figure 6 The data transmission method is described below. This data transmission method includes: S1 and S2.

[0081] S1: Any processor in the multiprocessor system reads the first access data, adds a destination offset to the first access data to obtain the second access data, and sends the second access data to the first processor through the Peer port.

[0082] In a multiprocessor system, the process of a processor reading the first accessed data may include: The computing core in the processor sends access-related information (including the destination offset) to the DMA module in the processor, and the DMA module reads the corresponding first access data based on the access-related information.

[0083] The process of the computing core sending access-related information to the DMA module in the processor may include: the streaming multiprocessor in the computing core issuing access instructions; the driver module in the computing core receiving each access instruction, parsing each access instruction, and sending the parsed access-related information to the DMA module.

[0084] The process by which the driver module parses each access instruction can be found in the three different implementation methods described above.

[0085] S2: The first processor receives the second access data. If the destination offset in the second access data is not the offset of the first processor, the second access data is sent to the second processor through the Peer port.

[0086] After receiving the second access data, the first processor determines whether the destination offset in the second access data is the offset of the first processor. If the destination offset in the second access data is not the offset of the first processor, the second access data is sent to the second processor through the Peer port. The second processor is the next processor located on the transmission path from the first processor to the destination processor and connected to the first processor. The destination processor is the processor corresponding to the destination offset.

[0087] The method further includes: if the destination offset in the second access data is the offset of the first processor, then removing the destination offset from the second access data; and writing the second access data after removing the destination offset into the storage space corresponding to the first processor.

[0088] The method further includes: the second processor receiving the second access data; if the destination offset in the second access data is not the offset of the second processor, then the second access data is sent through the Peer port to the next processor located on the transmission path from the second processor to the destination processor and connected to the second processor.

[0089] The data transmission method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned multiprocessor system embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned multiprocessor system embodiment. This application also provides an electronic device, which includes the multiprocessor system described above. This electronic device includes, but is not limited to, mobile phones, tablets, laptops, desktop computers, servers, workstations, game consoles, robots, and in-vehicle devices.

[0090] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0092] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0093] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0094] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multiprocessor system, characterized in that, include: Multiple processors, each of which is connected via a peer port; Each of the processors includes: a computing core and a DMA module and a Peer port, wherein the processor is not a CPU; The computing core is used to send access-related information to the DMA module, which includes the target peer port and the destination offset. The DMA module is used to read the corresponding first access data based on the access-related information, add the destination offset to the first access data to obtain second access data, and send the second access data to the first processor connected to the target Peer port. Each of the processors is also used for: Receive the second access data; If the destination offset in the second access data is the offset of the current processor, then the second access data after removing the destination offset is written into the storage space corresponding to the current processor. If the destination offset in the second access data is not the offset of the current processor, then the second access data is sent to the second processor through the Peer port; wherein, the second processor is the next processor located on the transmission path from the current processor to the destination processor and connected to the current processor, and the destination processor is the processor corresponding to the destination offset.

2. The multiprocessor system according to claim 1, characterized in that, The computing core includes: Streaming multiprocessors are used to send access commands; The driver module connected to the DMA module is used to parse each access instruction after receiving each access instruction, and send the parsed access-related information to the DMA module.

3. The multiprocessor system according to claim 2, characterized in that, The number of DMA modules is multiple; the driver module is specifically used for: Each access instruction is parsed according to the order in which they are received, and the access-related information obtained from the parsing is sent to the idle DMA module.

4. The multiprocessor system according to claim 3, characterized in that, The driving module includes: An input queue is used to temporarily store access instructions from the streaming multiprocessor; The command parsing unit is used to obtain access instructions from the input queue in a first-in-first-out order, parse the obtained access instructions, and send the parsed access-related information to the idle DMA module.

5. The multiprocessor system according to claim 2, characterized in that, The number of DMA modules is multiple, the access instruction includes a DMA identifier, and the driver module is specifically used for: Based on the status of each DMA module, the idle DMA modules are identified; The access instruction whose DMA identifier matches that of the idle DMA module is parsed, and the parsed access-related information is sent to the idle DMA module.

6. The multiprocessor system according to claim 5, characterized in that, The driving module includes: Multiple input queues, each for temporarily storing access instructions with the same DMA identifier from the streaming multiprocessor; An arbitration unit is used to determine the idle DMA module based on the status of each DMA module, and to obtain access instructions in the input queue whose DMA identifiers match the DMA identifiers of the idle DMA modules in a first-in-first-out order. The command parsing unit is used to parse the received access command and send the parsed access-related information to the idle DMA module.

7. The multiprocessor system according to claim 2, characterized in that, The number of DMA modules is multiple, and the driver module is specifically used for: Each access instruction is parsed according to the order in which they are received to obtain access-related information; If the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy, the access-related information is temporarily stored. When the DMA module corresponding to the DMA identifier becomes idle, the temporarily stored access-related information is sent to the corresponding idle DMA module.

8. The multiprocessor system according to claim 7, characterized in that, The driving module includes: A first input queue and a second input queue, wherein the first input queue is used to temporarily store access instructions from the streaming multiprocessor; The command parsing unit is used to obtain access instructions from the first input queue in a first-in-first-out order, and parse the obtained access instructions. If the DMA module corresponding to the DMA identifier in the currently parsed access instruction is busy, the access-related information of the currently parsed access instruction is temporarily stored in the second input queue. The command parsing unit is also used to send the temporarily stored access-related information to the corresponding idle DMA module when the DMA module corresponding to the DMA identifier is idle.

9. An electronic device, characterized in that, Including the multiprocessor system as described in any one of claims 1-8.

10. A data transmission method, characterized in that, Applied to a multiprocessor system as described in any one of claims 1-8, the method comprises: Any processor in the multiprocessor system reads the first access data, adds a destination offset to the first access data to obtain the second access data, and sends the second access data to the first processor through the Peer port; The first processor receives the second access data. If the destination offset in the second access data is not the offset of the first processor, the second access data is sent to the second processor through the Peer port. Wherein, the second processor is the next processor located on the transmission path from the first processor to the destination processor and connected to the first processor, and the destination processor is the processor corresponding to the destination offset.

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