移位寄存器、栅极驱动电路及显示面板
By introducing a pull-up module, a signal storage module, and an output module into the shift register, the control signal switches between different time periods, solving the threshold voltage drift problem caused by the long-term conduction of the output transistor and improving the stability of the gate control signal.
CN120977227BActive Publication Date: 2026-07-17GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2025-08-25
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
The prolonged conduction of the output transistor causes threshold voltage drift, affecting the quality of the gate control signal output by the shift register.
Method used
Design a shift register comprising a pull-up module, a signal storage module, and an output module. By controlling the signal of the first node to switch level states at different time periods, the bias stress time of the output transistor can be reduced.
Benefits of technology
By shortening the bias stress time of the output transistor, the stability of the output transistor is improved, and the quality of the gate control signal is enhanced.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN120977227B_ABST
Abstract
本申请提供一种移位寄存器、栅极驱动电路及显示面板，通过使移位寄存器包括上拉模块、信号存储模块和输出模块，且在第一时段使移位寄存器的第一节点的信号具有有效电平，在第二时段将第一节点的信号的电平信息存储至移位寄存器的第二节点，且在第三时段使第一节点的信号具有无效电平，在第四时段使第一节点的信号再次具有有效电平，从而使得第一节点的信号可以在对应具有有效电平的第一时段和第四时段之间的第三时段具有无效电平，以缩短输出模块中输出晶体管所受到的偏置应力的时长，改善输出晶体管长时间所受到的偏置应力的影响。
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