Display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes a driving component, a multiplexing circuit, connecting lines, and multiple pixel units. The driving component is disposed within a bonding area and includes a first output unit. The multiplexing circuit is disposed within a circuit area and includes a first circuit unit. The connecting lines connect the driving component and the multiplexing circuit, and include a first connecting line connecting the first circuit unit and the first output unit. The multiple pixel units are disposed within the display area and connected to the multiplexing circuit. The first connecting line includes winding segments distributed within the display area. This invention can improve the resolution of the display panel, reduce the wiring space outside the display area, and reduce the bezel width of the display panel, thereby achieving a narrow bezel display panel.

Description

[0001] This divisional application is a divisional application of Chinese patent application No. 202311070048.5, filed on August 23, 2023, entitled "Display Panel and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0003] Organic light-emitting diode (OLED) display panels have many advantages, such as self-illumination, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, and the ability to achieve flexible display and large-area full-color display. They are widely recognized in the industry as the display panels with the greatest development potential.

[0004] Currently, in related technologies, the technique of placing fanout lines in the display area (fanout in AA, FIAA) involves routing the fanout lines from the AA area and connecting them to the data lines, thereby reducing the area of ​​the bottom bezel occupied by the fanout lines. However, when there are a large number of data lines, there are also a large number of fanout lines connected to the data lines, which means that the AA area needs more space for routing the fanout lines, making it difficult to meet the requirements of high resolution. Summary of the Invention

[0005] This invention provides a display panel and display device that can reduce the wiring space of the first connecting line outside the display area and reduce the bezel width of the display panel.

[0006] This invention provides a display panel, which includes a display area, a bonding area, and a circuit area located between the display area and the bonding area;

[0007] The display panel also includes:

[0008] A driving component, disposed within the binding area, includes a first output unit;

[0009] A multiplexing circuit is disposed within the circuit area and includes a first circuit unit;

[0010] A connecting line is connected between the driving component and the multiplexing circuit, and includes a first connecting line connecting the first circuit unit and the first output unit;

[0011] Multiple pixel units are disposed within the display area and connected to the multiplexing circuit;

[0012] The first connecting line includes winding segments distributed within the display area.

[0013] In one embodiment of the present invention, the first connecting line further includes a first line segment extending from the bonding area to the circuit area and connected to the first output unit, and a second line segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit, wherein the winding segment is connected between the first line segment and the second line segment.

[0014] In one embodiment of the present invention, both the first line segment and the second line segment extend along a first direction, and the first direction is the direction from the binding area to the display area. The first line segment and the second line segment are staggered along the first direction, and the winding line segment is distributed in a bent shape within the display area.

[0015] In one embodiment of the present invention, the first output unit and the first circuit unit are offset along the first direction.

[0016] In one embodiment of the present invention, the multiplexing circuit includes a plurality of second circuit units, the plurality of first circuit units and the plurality of second circuit units are arranged along a second direction, the second direction intersects the first direction, the driving component includes a plurality of second output units, the plurality of first output units and the plurality of second output units are arranged along the second direction, and the connecting line further includes a plurality of second connecting lines;

[0017] The second connecting line extends along the first direction and connects the second circuit unit and the second output unit.

[0018] In one embodiment of the present invention, the connecting line includes a plurality of first connecting lines, and the plurality of winding segments of the plurality of first connecting lines do not intersect.

[0019] In one embodiment of the present invention, the connecting line includes at least one winding group, a winding group includes a plurality of winding segments, and the plurality of winding segments are nested one by one within the winding group.

[0020] In one embodiment of the present invention, the length of the binding area along the second direction is less than the length of the circuit area along the second direction, and the circuit area includes a first sub-area and a second sub-area, the second sub-area is aligned with the binding area along the first direction, and the first sub-area is connected to the second sub-area along the second direction;

[0021] The first circuit units are distributed in the first sub-region, and the second circuit units are distributed in the second sub-region.

[0022] In one embodiment of the present invention, a plurality of second output units include an edge second output unit located at the end of the driving component, and a first output unit connected to the first circuit unit on the side away from the second sub-region is located on the side of the first output unit connected to the first circuit unit on the side close to the second sub-region away from the edge second output unit.

[0023] In one embodiment of the present invention, within the driving assembly, among a plurality of second output units near the edge second output unit, a first output unit is spaced apart between two adjacent second output units, and among a plurality of second output units away from the edge second output unit, the plurality of second output units are arranged adjacent to each other.

[0024] In one embodiment of the present invention, the length of the winding segment of the first connecting line connected to the first circuit unit on the side away from the second sub-region is greater than the length of the winding segment of the first connecting line connected to the first circuit unit on the side close to the second sub-region.

[0025] In one embodiment of the present invention, the second circuit unit and the second output unit are aligned along the first direction.

[0026] In one embodiment of the present invention, the plurality of pixel units include a plurality of pixel unit groups arranged along the second direction, and the pixel unit groups include a plurality of pixel units arranged along the first direction;

[0027] In this configuration, one of the pixel unit groups is aligned with either one of the first circuit units or one of the second circuit units along the first direction.

[0028] In one embodiment of the present invention, the display panel further includes a plurality of data line groups, one of the data line groups being connected to one of the pixel unit groups, the data line group including at least two data lines extending along the first direction, the data lines being connected to the pixel units in the corresponding pixel unit group;

[0029] In this configuration, one of the data line groups is connected along the first direction to a corresponding first circuit unit or a second circuit unit.

[0030] In one embodiment of the present invention, the display panel includes a substrate and a thin film transistor layer disposed on the substrate, the first circuit unit includes a plurality of first multiplexed thin film transistors located in the thin film transistor layer, and the second circuit unit includes a plurality of second multiplexed thin film transistors located in the thin film transistor layer.

[0031] In this configuration, one first connection line is connected to the source of one of the first multiplexed thin-film transistors, one data line is connected to the drain of one of the first multiplexed thin-film transistors, one second connection line is connected to the source of one of the second multiplexed thin-film transistors, and one data line is connected to the drain of one of the second multiplexed thin-film transistors.

[0032] In one embodiment of the present invention, the display panel further includes a conductive layer disposed on the side of the thin film transistor layer away from the substrate, and a light-emitting device layer disposed on the side of the conductive layer away from the thin film transistor layer;

[0033] The conductive layer includes the first line segment, the second line segment, and the winding segment.

[0034] In one embodiment of the present invention, the first line segment partially overlaps with the second circuit unit, the second line segment extends from the boundary of the display area to the first circuit unit, and is connected to the source of the first multiplexed thin-film transistor.

[0035] According to the above-mentioned objectives of the present invention, embodiments of the present invention also provide a display device, the display device including the display panel.

[0036] The beneficial effects of this invention are as follows: A first connecting line is provided between the first circuit unit and the first output unit, allowing signals from the driving component to be transmitted to the display area via a multiplexing circuit. This reduces the number of data lines compared to related technologies. Furthermore, by incorporating winding segments in the first connecting line, the first circuit unit can be arranged in a preset position according to actual needs. This replaces the winding of fanout traces in related technologies with the winding segments of the first connecting line between the multiplexing circuit and the driving component, reducing the number of windings, increasing the available space in the display area, and improving the resolution of the display panel. Moreover, since the winding segments in the first connecting line are located within the display area, the winding segments avoid occupying space in the circuit area, thereby reducing the wiring space outside the display area and reducing the bezel width of the display panel, enabling a narrow bezel display panel. Attached Figure Description

[0037] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0038] Figure 1 This is a schematic diagram of a partial planar distribution structure of a display panel provided in an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of another partial planar distribution structure of the display panel provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a circuit structure for a first circuit unit and a second circuit unit provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of a circuit structure for a second circuit unit provided in an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of another partial planar distribution structure of the display panel provided in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of a planar distribution structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0045] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0046] This invention provides a display panel, please refer to... Figure 1 and Figure 2 The display panel includes a display area 101, a bonding area 1022, and a circuit area 1021 located between the display area 101 and the bonding area 1022.

[0047] Furthermore, the display panel also includes a driving component 10, a multiplexing circuit 20, connecting lines, and multiple pixel units 40; the driving component 10 is disposed in the bonding area 1022 and includes a first output unit 11; the multiplexing circuit 20 is disposed in the circuit area 1021 and includes a first circuit unit 21; the connecting lines connect the driving component 10 and the multiplexing circuit 20 and include a first connecting line 31 connecting the first circuit unit 21 and the first output unit 11; the multiple pixel units 40 are disposed in the display area 101 and connected to the multiple multiplexing circuits 20.

[0048] The first connecting line 31 includes winding segments 313 distributed within the display area 101.

[0049] In the implementation process, in this embodiment of the invention, a first connecting line 31 is provided between the first circuit unit 21 and the first output unit 11, so that the signal in the driving component 10 is transmitted to the display area 101 through the multiplexing circuit 20. Thus, the number of data lines in the first connecting line 31 can be reduced compared to the related technologies. By providing a winding segment 313 in the first connecting line 31, the first circuit unit 21 can be arranged according to a preset position. Thus, the winding of the fanout wiring in the related technologies can be replaced with the winding segment 313 of the first connecting line 31 between the multiplexing circuit 20 and the driving component 10 in this embodiment of the invention. This can reduce the number of windings, increase the available space in the display area 101, and help improve the resolution of the display panel. Furthermore, the winding segment 313 in the first connecting line 31 is located in the display area 101, avoiding the winding segment 313 occupying the space of the circuit area 1021. This can reduce the wiring space outside the display area 101, thereby reducing the bezel width of the display panel and realizing a narrow bezel display panel.

[0050] Specifically, please continue to combine Figure 1 and Figure 2 The display panel provided in this embodiment of the invention includes a display area 101 and a non-display area 102 adjacent to the display area 101, and the non-display area 102 may be disposed around the display area 101; and the non-display area 102 may include a bonding area 1022 located on at least one side of the display area 101 and a circuit area 1021 located between the bonding area 1022 and the display area 101.

[0051] Furthermore, the display panel also includes a plurality of pixel units 40 disposed in the display area 101, a driving component 10 disposed in the bonding area 1022, a multiplexing circuit 20 disposed in the circuit area 1021, and a plurality of connecting lines.

[0052] In this arrangement, multiple pixel units 40 are arranged in an array along a first direction M and a second direction N, with the first direction M being the direction from the binding area 1022 to the display area 101, and the second direction N intersecting with the first direction M.

[0053] In one embodiment, the first direction M is perpendicular to the second direction N.

[0054] The multiple pixel units 40 can be divided into multiple pixel unit groups arranged along the second direction N, and each pixel unit group includes multiple pixel units 40 arranged along the first direction M, that is, each pixel unit group includes a column of pixel units 40 arranged along the first direction M.

[0055] The driving component 10 includes a plurality of first output units 11 and a plurality of second output units 12; in one embodiment, the plurality of first output units 11 and the plurality of second output units 12 may be disposed on the side of the driving component 10 close to the display area 101.

[0056] The multiplexing circuit 20 includes multiple first circuit units 21 and multiple second circuit units 22. The connecting lines include multiple first connecting lines 31 and multiple second connecting lines 32. The first output unit 11 is connected to the first circuit unit 21 through the first connecting lines 31, and the second output unit 12 is connected to the second circuit unit 22 through the second connecting lines 32.

[0057] The first connecting line 31 includes a first line segment 311 connected to the first output unit 11 and extending from the binding area 1022 to the circuit area 1021, a second line segment 312 extending into the circuit area 1021 and connected to the first circuit unit 21, and a winding line segment 313 connected between the first line segment 311 and the second line segment 312 and located in the display area 101; one end of the second connecting line 32 is connected to the second output unit 12, and the other end is connected to the second circuit unit 22.

[0058] In this embodiment of the invention, a pixel unit group is aligned with a first circuit unit 21 or a second circuit unit 22 along a first direction M. The display panel also includes a plurality of data line groups disposed in the display area 101 along the first direction M. A data line group is connected to a first circuit unit 21 or a second circuit unit 22 along the first direction M. A data line group is connected to a pixel unit group. Each data line group includes at least two data lines 50, and the at least two data lines 50 are connected to the pixel unit 40 in the corresponding pixel unit group.

[0059] In one embodiment, the number of data lines 50 in the data line group is four.

[0060] It is understood that a first circuit unit 21 is connected through a first connection line 31, and then the signal is transmitted to at least two data lines 50 through the first circuit unit 21; or a second circuit unit 22 is connected through a second connection line 32, and then the signal is transmitted to at least two data lines 50 through the second circuit unit 22, so as to realize the multiplexing function of the multiplexing circuit 20.

[0061] The length of the binding area 1022 along the second direction N is less than the length of the circuit area 1021 along the second direction N, which will result in some driving components 10 and some multiplexing circuits 20 being unable to be aligned; in one embodiment, the circuit area 1021 includes a second sub-area 1032 aligned with the binding area 1022 and a first sub-area 1031 connected to the second sub-area 1032 along the second direction N.

[0062] In this embodiment of the invention, the first circuit unit 21 is disposed in the first sub-region 1031, and the second circuit unit 22 is disposed in the second sub-region 1032, so that the first circuit unit 21 and the second circuit unit 22 can be aligned with the corresponding pixel unit group along the first direction M, so as to avoid the need to set fan-out lines in the display area 101 for winding corresponding data lines, thereby saving wiring space and reducing signal interference.

[0063] It should be noted that, in this embodiment of the invention, the display panel may include a substrate, a thin-film transistor layer disposed on the substrate, a conductive layer disposed on the side of the thin-film transistor layer away from the substrate, and a light-emitting device layer disposed on the side of the conductive layer away from the thin-film transistor layer. Further, the light-emitting device layer includes an anode layer disposed on the side of the conductive layer away from the thin-film transistor layer, a light-emitting layer disposed on the side of the anode layer away from the conductive layer, and a cathode layer disposed on the side of the light-emitting layer away from the anode layer. The winding segment 313 of the first connecting line 31 may be located in the conductive layer, and the winding segment 313 may overlap with each pixel unit 40 without affecting the normal light emission of the pixel unit 40. In addition, the thin-film transistor layer includes display thin-film transistors disposed in each pixel unit 40. The display thin-film transistors include source and drain electrodes. The conductive layer may also include a transition portion connecting the source and drain electrodes and the anode layer, and the winding segment 313 is spaced apart from the transition portion.

[0064] In one embodiment, the first output unit 11 and the first circuit unit 21 are offset from each other along the first direction M, and the second output unit 12 and the second circuit unit 22 are aligned with each other along the first direction M. A first connecting line 31 connects to a first circuit unit 21, and a second connecting line 32 connects to a second circuit unit 22.

[0065] Please combine Figure 1 , Figure 3 as well as Figure 4 The first circuit unit 21 includes a first multiplexed thin-film transistor T1 located in the thin-film transistor layer, and the first multiplexed thin-film transistor T1 includes an active layer, a gate, a source, and a drain. The second circuit unit 22 includes a second multiplexed thin-film transistor T2 located in the thin-film transistor layer, and the second multiplexed thin-film transistor T2 includes an active layer, a gate, a source, and a drain.

[0066] In the multiplexing circuit 20, for the first circuit unit 21, a first connection line 31 is connected to the source of a plurality of first multiplexed thin-film transistors T1, a data line 50 is connected to the drain of a first multiplexed thin-film transistor T1, and a first control line 61 is connected to the gate of a first multiplexed thin-film transistor T1. Therefore, in the first circuit unit 21, the plurality of first multiplexed thin-film transistors T1 can be selectively turned on or off via the plurality of first control lines 61, allowing the first connection line 31 and the plurality of first thin-film transistors T1 to transmit signals to the plurality of data lines 50. Figure 3 Taking a first circuit unit 21 connected to four data lines 50 as an example. Similarly, for the second circuit unit 22, a second connection line 32 is connected to the source of multiple second multiplexed thin-film transistors T2, a data line 50 is connected to the drain of one second multiplexed thin-film transistor T2, and a second control line 62 is connected to the gate of one second multiplexed thin-film transistor T2. Therefore, in the second circuit unit 22, multiple second multiplexed thin-film transistors T2 can be selectively turned on or off via multiple second control lines 62, allowing one second connection line 32 and multiple second thin-film transistors T2 to transmit signals to multiple data lines 50. Figure 4 The example shown is a second circuit unit 22 connected to four data lines 50. It is understood that this should be considered in conjunction with... Figure 1 and Figure 3 Since the first connecting line 31 is connected to the first circuit unit 21 via the first line segment 311, the winding line segment 313, and the second line segment 312 in sequence, and the second line segment 312 is offset from the corresponding first circuit unit 21 along the first direction M, the winding line segment 313 is bent within the display area 101 and wound back to connect to the second line segment 312, so that the second line segment 312 can be aligned with the corresponding first circuit unit 21 along the first direction M. Therefore, the second line segment 312 extends from the boundary of the display area 101 into the first circuit unit 21 and connects to the source of the first multiplexed thin-film transistor T1, extending in the same direction as the data line 50 into the first circuit unit 21. Figure 3 As shown.

[0067] Understandable Figure 3 and Figure 4The diagram below is merely a schematic representation of the distribution of the first circuit unit 21, the second circuit unit 22, and the circuit lines provided in this embodiment of the invention. The specific distribution can be adjusted according to actual needs and is not limited here.

[0068] Furthermore, the first output unit 11 and the second circuit unit 22 can be aligned along the first direction M. It should be noted that the first line segment 311 and the second line segment 312 are both located in the conductive layer. When the first line segment 311 extends from the bonding area 1022 into the circuit area 1021, it can pass through the second circuit unit 22. That is, the second line segment 312 can partially overlap with the second circuit unit 22 and also partially overlap with the second multiplexed thin film transistor T2.

[0069] It should be noted that in this embodiment of the invention, the first circuit unit 21 and the second circuit unit 22 are set in the area corresponding to the corresponding pixel unit group. Then, the connection between the first circuit unit 21 and the first output unit 11, and the connection between the second circuit unit 22 and the second output unit 12 are realized through the first connecting line 31 and the second connecting line 32. Since the first output unit 11 and the first circuit unit 21 are staggered along the first direction M, there will be line segments in the first connecting line 31 that intersect with the first direction M, such as the winding line segment 313.

[0070] Continuing from the above, both the first line segment 311 and the second line segment 312 extend along the first direction M, and the first line segment 311 and the second line segment 312 are staggered along the first direction M. The winding line segment 313 is distributed in a bent shape within the display area 101. That is, in this embodiment of the invention, the first line segment 311 and the second line segment 312 located outside the display area 101 in the first connecting line 31 are set as straight segments, while the winding line segment 313, which is curved or broken, is set within the display area 101. This can effectively reduce the wiring space outside the display area 101, thereby reducing the bezel width. In addition, in this embodiment of the invention, by setting a winding line in the first connecting line 31 between the first output unit 11 and the first circuit unit 21, signal transmission is achieved while the first circuit unit 21 can be aligned with the corresponding pixel unit group along the first direction M. Thus, the data lines in the data line group corresponding to the pixel unit group are also aligned. The data line 50 can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four. Compared with the related technology, the related technology requires setting multiple fanout traces corresponding one-to-one with multiple data lines 50 for winding. In this embodiment of the invention, the winding of the fanout traces is replaced by the winding segment 313 in the first connecting line 31 between the first circuit unit 21 and the first output unit 11. The number of first connecting lines 31 is less than the number of data lines 50, that is, less than the number of fanout traces in the related technology. This avoids a large number of fanout traces being wound in the display area 101, and allows a smaller number of first connecting lines 31 to be wound, thereby reducing the space for winding in the display area 101, simplifying the wiring difficulty, and reducing signal interference.

[0071] Furthermore, since the second output unit 12 and the second circuit unit 22 are aligned along the first direction M, the second connecting line 32 is connected between the second output unit 12 and the second circuit unit 22 along the first direction M.

[0072] Furthermore, the multiple winding segments 313 in the multiple first connecting lines 31 do not intersect, in order to reduce the difficulty of wiring.

[0073] In one embodiment, the plurality of connecting lines include at least one winding group, and a winding group includes a plurality of winding segments 313, which are nested one by one within the winding group. The winding segments 313 in the plurality of first connecting lines 31 are nested one by one, i.e., the winding segments 313 are arranged in a loop; the winding segment 313 in the first connecting line 31 connected to the first circuit unit 21 near the second sub-region 1032 is located inside the loop, and the winding segment 313 in the first connecting line 31 connected to the first circuit unit 21 away from the second sub-region 1032 is located outside the loop. Further, the length of the winding segment 313 in the first connecting line 31 connected to the first circuit unit 21 away from the second sub-region 1032 is greater than the length of the winding segment 313 in the first connecting line 31 connected to the first circuit unit 21 near the second sub-region 1032.

[0074] In one embodiment, please refer to Figure 1 Within the drive assembly 10, at least one second output unit 12 is spaced between two first output units 11, for example, one second output unit 12 is spaced between two first output units 11. Furthermore, the plurality of second output units 12 includes an edge second output unit 121 located at the end of the drive assembly 10. A first output unit 11 connected to a first circuit unit 21 on the side away from the second sub-region 1032 is located on the side of the first circuit unit 21 connected to the side near the second sub-region 1032 that is away from the edge second output unit 121. Further, among the plurality of second output units 12 near the edge second output unit 121, one first output unit 11 is spaced between two adjacent second output units 12, and among the plurality of second output units 12 away from the edge second output unit 121, the plurality of second output units 12 are arranged adjacent to each other.

[0075] Continuing from the above, in one embodiment of the present invention, please refer to... Figure 2 and Figure 5P1 to P610 are multiple circuit units in the multiplexing circuit 20, and S1 to S610 are multiple output units in the drive assembly 10; wherein P1 to P200 are first circuit units 21, P201 to P610 are second circuit units 22, S1 to S200 are first output units 11, and S201 to S610 are second output units 12. In this embodiment of the invention, multiple circuit units from P1 to P610 can be aligned according to their respective data line groups or pixel unit groups, so that the multiple circuit units from P1 to P610 are arranged in sequence; further, the edge second output unit 121 at the end of the driving component 10 is S201, and from S201 to the right are arranged in sequence as S201, S202, S199...S399, S2, S400, S1, S401, S402...S609, S610, wherein the multiple second output units 12 include S201 to S610, and the multiple second output units 12 are arranged in sequence; the multiple first output units 11 include S1 to S200, and the multiple first output units 11 are arranged in reverse order.

[0076] Since P1, connected to S1, is located in the first sub-region 1031 furthest from the second sub-region 1032, the winding segment 313 corresponding to S1 has the longest length, making S1 the furthest from S201 among S1 to S200. P200, connected to S200, is located in the first sub-region 1031 closest to the second sub-region 1032, therefore, the winding segment 313 corresponding to S2 has the shortest length, making S200 adjacent to S201. Similarly, the remaining first output units 11 are arranged according to the position of the first circuit units 21 they are connected to, so that S1 to S200 are arranged in reverse order from left to right, and the end of the driving component 10 is the edge second output unit 121 (S210). There is an interval of S200 between S201 and S202, an interval of S199 between S202 and S203 (not shown in the figure), an interval of S2 between S399 and S400, and an interval of S1 between S400 and S401. Continuing from the above, in this embodiment of the invention, the first output unit 11 is arranged in reverse order in the driving component 10, while the second output unit 12 is arranged in sequence, and the first output unit 11 and the second output unit 12 are arranged alternately in random order. In conjunction with the multiple nested winding segments 313 in the first connecting line 31, multiple circuit units P1 to P610 can be arranged in sequence, that is, the circuit units can be aligned with the corresponding data line group or pixel unit group.

[0077] Further, please refer to Figure 6 ,in, Figure 6The first connecting line 31, the second connecting line 32, the drive component 10, and the multiplexing circuit 20 on the left and right sides are arranged symmetrically. This is understandable. Figure 6 The multiple winding segments 313 on the left side of the middle section form a winding group, while Figure 6 The multiple winding segments 313 on the right side of the middle form a winding group; similarly, the connection between the multiplexing circuit 20 and the pixel unit group and data line group is the same, and will not be described again here.

[0078] In summary, in this embodiment of the invention, the first line segment 311 and the second line segment 312 located outside the display area 101 in the first connecting line 31 are set as straight lines, while the curved or broken line winding segment 313 is set inside the display area 101. This effectively reduces the wiring space outside the display area 101, thereby reducing the bezel width. Furthermore, in this embodiment of the invention, by setting a winding in the first connecting line 31 between the first output unit 11 and the first circuit unit 21, signal transmission is achieved while the first circuit unit 21 can be aligned with the corresponding pixel unit group along the first direction M. Thus, the data lines 50 in the data line group corresponding to the pixel unit group can be connected to the corresponding first circuit unit 21 along the first direction M. Since there are at least two data lines 50 in each data line group, for example, there can be four, this embodiment of the invention avoids a large number of data lines 50 being wound inside the display area 101, while allowing a smaller number of first connecting lines 31 to be wound. This reduces the wiring arrangement space inside the display area 101, simplifies the wiring difficulty, and reduces signal interference.

[0079] In addition, embodiments of the present invention also provide a display device, which includes the display panel described in the above embodiments.

[0080] Since the display device is provided with the display panel provided in the above embodiments of the present invention, the display device has the same beneficial effects as the above-described display panel.

[0081] In one embodiment, the display device may include a television, computer, mobile phone, tablet, and other display devices.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] The above provides a detailed description of a display panel and display device provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, The display panel includes a display area and a non-display area adjacent to the display area, the non-display area being disposed around the display area; and the non-display area includes a bonding area located on at least one side of the display area and a circuit area located between the display area and the bonding area; The display panel also includes: A driving component, disposed within the binding area, includes a first output unit; A multiplexing circuit is disposed within the circuit area and includes a first circuit unit; A connecting line is connected between the driving component and the multiplexing circuit, and includes a first connecting line connecting the first circuit unit and the first output unit; Multiple pixel units are disposed in the display area and connected to the multiplexing circuit. The multiple pixel units include multiple pixel unit groups arranged along a second direction. The pixel unit group includes multiple pixel units arranged along a first direction. The first direction is the direction from the binding area to the display area. The second direction intersects with the first direction. One pixel unit group is aligned with one of the first circuit units along the first direction. The first connecting line includes a winding segment distributed within the display area, a first line segment extending from the bonding area to the circuit area and connected to the first output unit, and a second line segment extending from the boundary of the display area to the circuit area and connected to the first circuit unit. The winding segment is connected between the first line segment and the second line segment. Both the first line segment and the second line segment extend along the first direction and are staggered along the first direction. The winding segment is distributed in a bent shape within the display area.

2. The display panel of claim 1, wherein, The first output unit and the first circuit unit are staggered along the first direction.

3. The display panel of claim 1, wherein, The connecting line includes multiple first connecting lines, and the multiple winding segments of the multiple first connecting lines do not intersect.

4. The display panel according to claim 3, characterized in that, The connecting line includes at least one winding group, and a winding group includes multiple winding segments, wherein the multiple winding segments are nested one by one within the winding group.

5. The display panel according to any one of claims 1 to 4, characterized in that, The multiplexing circuit includes multiple second circuit units, and the multiple first circuit units and multiple second circuit units are arranged along the second direction. The driving component includes multiple second output units, and the multiple first output units and multiple second output units are arranged along the second direction. The connecting line also includes multiple second connecting lines. The second connecting line extends along the first direction and connects the second circuit unit and the second output unit.

6. The display panel according to claim 5, characterized in that, The length of the binding area along the second direction is less than the length of the circuit area along the second direction, and the circuit area includes a first sub-area and a second sub-area. The second sub-area is aligned with the binding area along the first direction, and the first sub-area is connected to the second sub-area along the second direction. The plurality of the first circuit units are distributed in the first sub-region, and the plurality of the second circuit units are distributed in the second sub-region.

7. The display panel according to claim 6, characterized in that, The plurality of second output units include an edge second output unit located at the end of the drive assembly, and a first output unit connected to the first circuit unit on the side away from the second sub-region is located on the side of the first output unit connected to the first circuit unit on the side close to the second sub-region away from the edge second output unit.

8. The display panel according to claim 7, characterized in that, Within the drive assembly, among the plurality of second output units near the edge second output unit, there is a first output unit spaced apart between two adjacent second output units, and among the plurality of second output units away from the edge second output unit, the plurality of second output units are arranged adjacent to each other.

9. The display panel according to claim 6, characterized in that, The length of the winding segment of the first connecting line connected to the first circuit unit on the side away from the second sub-region is greater than the length of the winding segment of the first connecting line connected to the first circuit unit on the side closer to the second sub-region.

10. The display panel according to claim 6, characterized in that, The connecting line includes multiple first connecting lines, and multiple winding segments of the multiple first connecting lines are arranged in a loop. The winding segment of the first connecting line connected to the first circuit unit near the second sub-region is located inside the loop, and the winding segment of the first connecting line connected to the first circuit unit away from the second sub-region is located outside the loop.

11. The display panel according to claim 5, characterized in that, The second circuit unit and the second output unit are aligned along the first direction.

12. The display panel according to claim 5, characterized in that, One of the pixel unit groups is aligned with one of the second circuit units along the first direction.

13. The display panel according to claim 5, characterized in that, The display panel further includes multiple data line groups, one of the data line groups being connected to one of the pixel unit groups. Each data line group includes at least two data lines extending along the first direction, and the data lines are connected to the pixel units in the corresponding pixel unit group. In this configuration, one of the data line groups is connected along the first direction to a corresponding first circuit unit or a second circuit unit.

14. The display panel according to claim 13, characterized in that, The display panel includes a substrate and a thin-film transistor layer disposed on the substrate. The first circuit unit includes a plurality of first multiplexed thin-film transistors located in the thin-film transistor layer, and the second circuit unit includes a plurality of second multiplexed thin-film transistors located in the thin-film transistor layer. In this configuration, one first connection line is connected to the source of one of the first multiplexed thin-film transistors, one data line is connected to the drain of one of the first multiplexed thin-film transistors, one second connection line is connected to the source of one of the second multiplexed thin-film transistors, and one data line is connected to the drain of one of the second multiplexed thin-film transistors.

15. The display panel according to claim 14, characterized in that, The display panel further includes a conductive layer disposed on the side of the thin film transistor layer away from the substrate, and a light-emitting device layer disposed on the side of the conductive layer away from the thin film transistor layer; The conductive layer includes the first line segment, the second line segment, and the winding segment.

16. The display panel according to claim 15, characterized in that, The winding segment overlaps with the pixel unit.

17. The display panel according to claim 14, characterized in that, The first line segment partially overlaps with the second circuit unit, and the second line segment extends from the boundary of the display area to the first circuit unit and is connected to the source of the first multiplexed thin-film transistor.

18. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 17.

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