Non-volatile two-terminal memory read method and related products

Abstract

The application discloses a nonvolatile two-terminal memory reading method and related products, and relates to the technical field of semiconductors. The nonvolatile two-terminal memory comprises at least one nonvolatile two-terminal storage unit, and the nonvolatile two-terminal storage unit comprises at least a switching unit and a nonvolatile two-terminal storage unit. The reading circuit comprises: a pre-charging module configured to pre-charge a bit line to generate a characteristic current flowing through the storage unit; a conversion module configured to amplify the characteristic current to obtain an amplified current, and use the amplified current to pull down a reading input signal; a biasing module configured to generate a pull-up current for pulling up the reading input signal; and a reading module configured to output storage data of the nonvolatile two-terminal storage unit according to the reading input signal. The technical scheme of the application helps to improve the reading margin of the memory.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor technology. More specifically, this invention relates to a method for reading a non-volatile two-dimensional memory and related products. Background Technology

[0002] In high-density storage scenarios, the scale of the storage array increases significantly, requiring bit lines to connect more storage cells. This leads to a substantial increase in trace length, and the parasitic resistance (R) and capacitance (C) on the bit lines increase with the bit line length, forming a large RC load. During read operations, the bit lines need to generate detectable voltage differences through charging and discharging to distinguish the storage state of the storage cells. An excessive RC load will significantly prolong the charging and discharging time of the bit lines, causing the voltage difference between different storage states to fail to reach the threshold range that the sensitive amplifier can recognize, resulting in read failure. Moreover, in high-density storage arrays, the number of storage cells connected to the bit lines increases dramatically, significantly increasing the leakage current of unselected storage cells. This leakage current will be superimposed on the bit line charging and discharging process, reducing the read margin.

[0003] In view of this, the present invention provides a non-volatile two-ended memory read method and related products to improve the accuracy of memory read operations. Summary of the Invention

[0004] In order to at least solve one or more technical problems described in the background section above, the present invention proposes the following technical solutions and several embodiments thereof.

[0005] In a first aspect, the present invention discloses a non-volatile two-ended memory read circuit, the non-volatile two-ended memory including at least one non-volatile two-ended storage section, the non-volatile two-ended storage section including at least a switching unit and a non-volatile two-ended storage cell, the read circuit including: a pre-charge module configured to pre-charge a bit line to generate a characteristic current flowing through the storage cell; a conversion module configured to: amplify the characteristic current to obtain an amplified current; and use the amplified current to pull down a read input signal; a bias module configured to generate a pull-up current for pulling up the read input signal; and a read module configured to output stored data of the non-volatile two-ended storage cell according to the read input signal.

[0006] In a second aspect, the present invention discloses a non-volatile two-terminal memory, including the circuitry described in the first aspect.

[0007] In a third aspect, the present invention discloses a method for reading a non-volatile two-ended memory, the memory including at least one non-volatile two-ended storage section, the non-volatile two-ended storage section including at least a switching unit and a non-volatile two-ended storage cell, the method comprising: pre-charging a word line to generate a characteristic current flowing through the storage cell; amplifying the characteristic current to obtain an amplified current; using the amplified current to pull down a read input signal; using a pull-up current to pull up the read input signal; and outputting stored data of the non-volatile two-ended storage cell according to the read input signal.

[0008] According to the technical solution of the present invention, the bit line where the target memory cell is located is first pre-charged to generate a characteristic current flowing through the target memory cell. This characteristic current is then amplified to obtain an amplified current. After the amplified current and the pull-down current compete for the pull-up and pull-down of the read input signal of the read module, the read module is used to output the data stored in the target memory cell based on the read input signal. If the target memory cell is in a low-resistance state, the characteristic current is relatively large, generally greater than 10μA. The amplified current obtained by amplifying the characteristic current is much larger than the bias current, thereby helping to improve the read margin of the memory. Attached Figure Description

[0009] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the invention are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein: Figure 1 An exemplary schematic diagram of a memory according to some embodiments of the present invention is shown.

[0010] Figure 2 An exemplary structural diagram of a ReRAM memory cell in some embodiments of the present invention is shown.

[0011] Figure 3 An exemplary structural diagram of a storage array according to some embodiments of the present invention is shown.

[0012] Figure 4 An exemplary schematic diagram of the peripheral circuitry in some embodiments of the present invention is shown.

[0013] Figure 5 An exemplary schematic diagram of a sensitive amplifier readout circuit according to some embodiments of the present invention is shown.

[0014] Figure 6 An exemplary schematic diagram of a non-volatile two-terminal memory read circuit according to some embodiments of the present invention is shown.

[0015] Figure 7An exemplary structural diagram of a storage array according to some embodiments of the present invention is shown.

[0016] Figure 8 An exemplary schematic diagram of a non-volatile two-terminal memory read circuit according to some embodiments of the present invention is shown.

[0017] Figure 9 An exemplary schematic diagram of a differential signal amplifier in some embodiments of the present invention is shown.

[0018] Figure 10 An exemplary structural diagram of the conversion module in some embodiments of the present invention is shown.

[0019] Figure 11 An exemplary schematic diagram of a non-volatile two-terminal memory read circuit according to some embodiments of the present invention is shown.

[0020] Figure 12 Timing diagrams of non-volatile two-terminal memory read circuits in some embodiments of the present invention are shown. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that the terms "first," "second," etc., in the claims, specification, and drawings of this invention are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of this invention indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0023] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0024] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0026] Storage devices such as cache, main memory, and solid-state drives (SSDs) are core components of computing systems, and their performance and architecture directly affect the functionality of the entire system.

[0027] Figure 1 Exemplary schematic diagrams of a memory 100 according to some embodiments of the present invention are shown. For example... Figure 1 As shown, in some embodiments, the memory 100 includes a memory stack 110, peripheral circuits 120, and a communication connection 130 disposed between the memory stack 110 and the peripheral circuits 120.

[0028] The storage stack 110 is the physical carrier for actual data storage and can be obtained by three-dimensional integration technology from multiple storage arrays 111. The storage array 111 can be composed of multiple rows and columns of storage units. The storage units can include switching units and storage units. The storage units can be dynamic random access memory (DRAM) storage units, static random access memory (SRAM) storage units, resistive random access memory (ReRAM) storage units, spin-transfer torque magnetoresistive random access memory (STT-MRAM) storage units, phase change memory (PCM) storage units, ferroelectric random access memory (FeRAM) storage units, or flash memory storage units.

[0029] Figure 2 Exemplary structural diagrams of ReRAM memory cells in some embodiments of the present invention are shown. For example... Figure 2 As shown, a ReRAM memory cell includes an upper electrode, a resistive switching layer, and a lower electrode. The upper and lower electrodes can be metal electrodes, such as those made of aluminum (Al), titanium (Ti), or copper (Cu). The resistive switching layer can be a metal oxide material, such as zinc oxide (ZnO), magnesium oxide (MgO), or zirconium oxide (ZrO). x Titanium oxide (TiO) x Materials include aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₅), and hafnium oxide (HfO₂). The resistive switching layer can change its resistance value according to the voltage across its terminals. In some embodiments, a high-voltage pulse can be applied to the resistive switching layer, causing it to exhibit a low-resistance state (LRS); in other embodiments, a low-voltage pulse can be applied, causing it to become a high-resistance state (HRS). Furthermore, the resistive switching layer will maintain its resistance value even after the memory cell loses power.

[0030] Figure 3 Exemplary structural diagrams of storage arrays according to some embodiments of the present invention are shown. For example... Figure 3 As shown, the memory array 111 consists of multiple rows and columns of memory sections, accessed via horizontal and vertical wires, commonly referred to as word lines (WL), source lines (SL), and bit lines (BL). A memory section can be deployed between two source lines and adjacent bit lines and word lines. Each memory section includes memory cells and switching units. The memory cells can be two-ended memory cells, such as ReRAM memory cells; the switching units can be metal-oxide-semiconductor field-effect transistors (MOSFETs). When using a MOSFET as a switching unit, the MOSFET's gate is connected to the word line, and the current flowing to the memory cell can be controlled by adjusting the word line voltage; the MOSFET's source is connected to the source line, and its drain is connected to the lower electrode of the memory cell. The upper electrode of the memory cell is connected to the bit line, and the switching unit can be used to control access to the memory cell. In a computing system, data can be represented using fixed-point or floating-point numbers with multiple bits. In some embodiments, the storage array 111 uses each storage cell to store the value 0 / 1 of each bit, and multiple storage cells correspond to one data element; for example, when the storage cell is a ReRAM storage cell, logic 1 can be stored in the low-resistivity state of the resistive switching layer and logic 0 can be stored in the high-resistivity state of the resistive switching layer.

[0031] Back Figure 1 The peripheral circuit 120 connects the storage array 111 to the external system and is responsible for coordinating the read and write operations, address encoding, signal processing and other functions of the storage array 111 to ensure the correct transmission and processing of data.

[0032] Figure 4 Exemplary schematic diagrams of peripheral circuits in some embodiments of the present invention are shown. For example... Figure 4 As shown, in some embodiments, the peripheral circuit 120 includes a row multiplexer 121, a column multiplexer 122, a row address decoder 123, a read / write driver circuit 124, a control circuit 125, a column address decoder 126, a sensitive amplifier 127, and a data buffer 128. The data reading operation in the memory 100 is the process by which the peripheral circuit 120 retrieves target data from the storage array 111 based on an externally input address signal. Throughout the reading process, the control circuit 125 performs timing control and logic coordination for each step. The externally input address signal is divided into a row address and a column address, used to locate the specific storage cell where the data to be read needs to be. The row address and column address are transmitted to the row address decoder 123 and the column address decoder 126, respectively. The row address decoder 123 decodes the row address to determine the row where the target storage cell is located. The row multiplexer 121 connects the read / write driver circuit 124 to the storage array 111, enabling the read / write driver circuit 124 to activate the word line of the target storage cell. The column address decoder 126 decodes the column address to determine the column where the target storage cell is located; the column multiplexer 122 connects the sensitive amplifier 127 to the storage array 111 so that the information stored in the target storage cell can be sensed and processed by the sensitive amplifier 127, and the sensing result of the sensitive amplifier can be temporarily stored in the data buffer 128.

[0033] Figure 5 Exemplary schematic diagrams of sensitive amplifier readout circuits in some embodiments of the present invention are shown, which can be applied in ReRAM memory. For example... Figure 5As shown, in some embodiments, the sensitive amplifier readout circuit includes: a power supply voltage VDD; a target memory cell; a bit line; a sensitive amplifier, which is a latching sensitive amplifier composed of cross-coupled inverter pairs; a switching unit S1, which is an N-type MOSFET (N-MOSFET) with an input signal WL; a precharge switch S3, which is a P-type MOSFET (P-MOSFET) with an input signal PRGb; a first sensitive amplifier enable switch S2, which is an N-MOSFET with an input signal SAENb; and a second sensitive amplifier enable switch S5, which is a P-MOSFET. SFET, with input signal SAENb; bias switch S4, a P-MOSFET with input signal PBIAS; first sensitive amplifier output enable switch S7, a P-MOSFET with input signal SAEOb; second sensitive amplifier output enable switch S9, an N-MOSFET with input signal SAEOb; third sensitive amplifier output enable switch S6, an N-MOSFET with input signal SAEOb; reference voltage switch S8, a P-MOSFET with input signal SA_REF; and a latch. In some embodiments, based on Figure 5 The sensitive amplifier readout circuit shown acquires the data stored in the target memory cell in three stages: 1. The pre-charge phase includes bit line pre-charge and read input signal pre-charge. The input signal PRGb of S3 is set low, thus turning on S3; the input signals SAENb of S2 and S5 are set low, thus turning on S5 and turning off S2; the input signal PBIAS of S4 is set low, thus turning on S4; thereby, the bit line containing the target memory cell and the read input signal SA_IN of the sensitive amplifier are pre-charged to VDD.

[0034] 2. Development Stage. The input signal WL of S1 is set to high, thus turning on S1 and generating a characteristic current flowing through the target memory cell. At this time, for the read input signal SA_IN of the sensitive amplifier, there is a pull-up current, i_bias, flowing from VDD through S4 and S5, and a pull-down current, i_cell, the characteristic current. It can be understood that i_bias tends to pull SA_IN up to VDD, while i_cell tends to pull SA_IN down to ground. Furthermore, if the target memory cell is in a low-impedance state, the characteristic current is large, and SA_IN decreases significantly; if the target memory cell is in a high-impedance state, the characteristic current is small, and SA_IN remains basically near VDD. The sensitive amplifier amplifies the voltage difference between the reference voltage and SA_IN into a digital logic level. For example, the reference voltage is the midpoint of SA_IN corresponding to the low-impedance and high-impedance states of the memory cell. If SA_IN is less than the reference voltage, the sensitive amplifier outputs a high level; if SA_IN is greater than the reference voltage, the sensitive amplifier outputs a low level.

[0035] 3. Output Stage. Set the input signal SAEOb of S7, S9, and S6 to low level, thereby turning on S7 and turning off S9 and S6, connecting the sensitive amplifier to the latch. Set the latch output enable signal OE to high level. The latch latches the output of the sensitive amplifier as the digital signal DOUT. For example, if the sensitive amplifier outputs a high level, DOUT takes the value 1; if the sensitive amplifier outputs a low level, DOUT takes the value 0.

[0036] In ReRAM, read margin refers to the difference in signal (such as voltage or current) between the high-resistivity and low-resistivity states that can be effectively detected by a sensitive amplifier during a read operation. The larger the difference, the more sufficient the read margin, and the lower the risk of false reads. In high-density storage scenarios, the size of the storage array increases significantly, and bit lines need to connect more memory cells, resulting in a substantial increase in trace length. The parasitic resistance and capacitance on the bit lines increase with the bit line length, forming a large RC load. During a read operation, the bit lines need to form a detectable voltage difference through charging and discharging to distinguish between the high-resistivity and low-resistivity states. An excessive RC load will significantly prolong the charging and discharging time of the bit lines, causing the voltage difference between the high-resistivity and low-resistivity states to fail to reach the threshold range that the sensitive amplifier can detect, resulting in read failure. Moreover, in high-density storage arrays, the number of memory cells connected to the bit lines increases dramatically, and the leakage current of unselected memory cells increases significantly. This leakage current will be superimposed on the bit line charging and discharging process, reducing the read margin.

[0037] In order to at least partially solve one or more of the technical problems mentioned above, the present invention provides a non-volatile two-ended memory read method and related products to improve the accuracy of memory read operations.

[0038] Figure 6 Exemplary schematic diagrams of non-volatile two-ended memory read circuits in some embodiments of the present invention are shown. For example... Figure 6 As shown, in some embodiments, the non-volatile two-ended memory includes at least one non-volatile two-ended storage section, which includes at least a switching unit and a non-volatile two-ended storage cell. The read circuit includes: a pre-charge module configured to pre-charge the bit line to generate a characteristic current flowing through the storage cell; a conversion module configured to: amplify the characteristic current to obtain an amplified current; and use the amplified current to pull down the read input signal; a bias module configured to generate a pull-up current for pulling up the read input signal; and a read module configured to output the stored data of the non-volatile two-ended storage cell according to the read input signal.

[0039] In some embodiments, the non-volatile two-way memory read circuit provided by the present invention can be implemented in the peripheral circuit 120, used to retrieve the data stored in the target memory cell from the non-volatile two-way memory according to the externally input address signal. The non-volatile two-way memory may include a memory stack, peripheral circuitry, and a communication connection between the memory stack and the peripheral circuitry. The memory stack can be obtained by three-dimensional integration of multiple memory arrays, and the memory array can be composed of multiple rows and columns of non-volatile two-way memory units. Each memory unit includes a switching unit and non-volatile two-way memory cells. The non-volatile two-way memory cells can be memory cells that store data through two electrodes and memory material, and can retain the stored data even after power failure, such as ReRAM memory cells, STT-MRAM memory cells, and PCM memory cells. In the following text, the technical solution of the present invention is mainly described using ReRAM memory cells as an example. For other types of non-volatile two-way memory cells, similar technical solutions can be used. The preceding text has already combined... Figure 3 This provides an implementation method for a storage array, in Figure 3 In the memory array shown, the switching unit can be a MOSFET, such as an N-MOSFET or a P-MOSFET. Another memory array implementation will be provided next.

[0040] Figure 7 Exemplary structural diagrams of storage arrays according to some embodiments of the present invention are shown. For example... Figure 7As shown, the memory array includes word lines and bit lines. A memory section can be deployed within the area formed by two adjacent word lines and two adjacent bit lines. The memory section includes non-volatile two-ended memory cells and a selector. The selector can be a bidirectional diode-type selector or other non-linear selection devices, such as a bidirectional threshold switch (OTS) or a metal-insulator transition (MIT). The selector is used to control access to the series-connected non-volatile two-ended memory cells.

[0041] In some embodiments, the bit lines in the non-volatile two-way memory are pre-charged to generate a characteristic current flowing through the memory cell. For example, by pre-charging the bit line of the target ReRAM memory cell and turning on the switch unit connected in series with the target memory cell, a characteristic current flowing through the target memory cell can be generated. If the target memory cell is in a low-resistance state, the characteristic current is larger; if the target memory cell is in a high-resistance state, the characteristic current is smaller. Thus, by detecting the magnitude of the characteristic current, it can be determined whether the target memory cell is in a low-resistance state or a high-resistance state, and thus determine whether the data stored in the target memory cell is logic 1 or logic 0.

[0042] In some embodiments, a conversion module amplifies the characteristic current to obtain an amplified current, which is used to pull down the read input signal of the read module, and a bias module generates a pull-up current for pulling up the read input signal. In some embodiments, the characteristic current is amplified to obtain an amplified current using the current control characteristics of active devices such as bipolar junction transistors (BJTs) or MOSFETs. In other embodiments, an operational amplifier is used to amplify the characteristic current through a negative feedback configuration to obtain an amplified current. It is understood that the read input signal can be an input signal of the read module; for example, the read input signal is input to the read module in voltage form so that the read module can determine whether the data stored in the target memory cell is logic 1 or logic 0 based on the read input signal. In some embodiments, the read input signal is connected to the power supply voltage of the read circuit via a bias module and grounded via a conversion module, so that the bias module can generate a pull-up current for pulling up the read input signal, and the conversion module can use the amplified current to pull down the read input signal.

[0043] It is understandable that reading the input signal can reflect the magnitude of the characteristic current, so the read module can be used to output the stored data of the non-volatile two-terminal memory cell based on the read input signal.

[0044] According to the technical solution of the present invention, the bit line where the target memory cell is located is first pre-charged to generate a characteristic current flowing through the target memory cell. This characteristic current is then amplified to obtain an amplified current. After the amplified current and the pull-down current compete for the pull-up and pull-down of the read input signal of the read module, the read module is used to output the data stored in the target memory cell based on the read input signal. It is understood that if the target memory cell is in a low-resistance state, the characteristic current is relatively large, generally greater than 10μA. The amplified current obtained by amplifying the characteristic current is much larger than the bias current, thereby helping to improve the read margin of the memory.

[0045] Figure 8 Exemplary schematic diagrams of non-volatile two-ended memory read circuits in some embodiments of the present invention are shown. For example... Figure 8 As shown, in some embodiments, the precharge module includes a precharge switch, a precharge first terminal, and a precharge second terminal; the precharge switch is connected to the power supply voltage of the read circuit through the precharge first terminal; the precharge switch is connected to the first terminal of the non-volatile two-terminal storage unit through the precharge second terminal.

[0046] Understandably, the precharge switch controls the on / off connection between the target memory cell and the power supply to the read circuit. When the precharge switch is on, the target memory cell is connected to the power supply via its first terminal and a bit line. The precharge switch can be a MOSFET, such as an N-MOSFET or a P-MOSFET. Figure 8 As shown, in some embodiments, the second end of the target storage unit is connected to the switching unit.

[0047] In some embodiments, the read module includes a differential signal amplifier configured to output stored data based on the difference between the read input signal and the reference signal.

[0048] It is understandable that both the input signal and the reference signal can be voltage signals. The input signal is the voltage signal obtained after the characteristic current of the target memory cell and the pull-up current compete through pull-up and pull-down actions, thus reflecting the characteristic current and the resistance of the target memory cell. In some embodiments, the value of the reference signal is determined based on the values ​​of the input signal in the low-impedance state and the high-impedance state of the memory cell. For example, if the maximum or expected value of the input signal in the low-impedance state is denoted as 'a', and the minimum or expected value of the input signal in the high-impedance state is denoted as 'b', then the reference signal can be (a+b) / 2. The differential signal amplifier can distinguish between the high-impedance and low-impedance states of the memory cell by comparing the input signal and the reference signal. When the input signal is greater than the reference signal, the memory cell is considered to be in a high-impedance state, and the data stored in the memory cell is logic 0; when the input signal is less than the reference signal, the memory cell is considered to be in a low-impedance state, and the data stored in the memory cell is logic 1.

[0049] Figure 9 Exemplary schematic diagrams of differential signal amplifiers in some embodiments of the present invention are shown. For example... Figure 9 As shown, in some embodiments, the differential signal amplifier includes a latch composed of a first inverter and a second inverter cross-coupled. The first inverter consists of T3 and T5 connected in series, and the second inverter consists of T4 and T6 connected in series. T3 and T4 are P-MOSFETs, and T5 and T6 are N-MOSFETs. The gates of T3 and T5 together serve as the input of the first inverter, and the drains of T3 and T5 are connected to each other, serving as the output of the first inverter. The gates of T4 and T6 together serve as the input of the second inverter, and the drains of T4 and T6 are connected to each other, serving as the output of the second inverter. The latch can be constructed by cross-coupling the first and second inverters. Specifically, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, thereby forming a positive feedback loop.

[0050] In some embodiments, a first inverter is connected in series with a first input switch T1, and a second inverter is connected in series with a second input switch T2. Both T1 and T2 are P-MOSFETs. The gate of T1 is connected to the reference signal input terminal and the drain is connected to the source of T3. The gate of T2 is connected to the read input signal input terminal and the drain is connected to the source of T4. The sources of T1 and T2 are connected together to the power supply voltage VDD of the read circuit.

[0051] In some embodiments, the output of the first inverter is grounded through the first latch output enable switch T7, and the output of the second inverter is grounded through the second latch enable switch T8. During the stage where the read module outputs the stored data of the non-volatile two-terminal memory cells based on the read input signal, T7 and T8 are in the off state, thus obtaining output O1 at the output of the first inverter and output O2 at the output of the second inverter. For example, when O1 is low and O2 is high, it can be considered that the voltage of the reference signal is less than the voltage of the read input signal, the memory cell is in a high-impedance state, and the data stored in the memory cell is logic 0; when O1 is high and O2 is low, it can be considered that the voltage of the read input signal is less than the voltage of the reference signal, the memory cell is in a low-impedance state, and the data stored in the memory cell is logic 1.

[0052] In some embodiments, the conversion module includes: a first current mirror configured to amplify a characteristic current by a set ratio to obtain an amplified current; and / or a second current mirror configured to convert the amplified current into a pull-down current for reading an input signal.

[0053] Figure 10 An exemplary structural diagram of the conversion module in some embodiments of the present invention is shown. In some embodiments, the first current mirror amplifies the characteristic current by a factor of m to obtain an amplified current, where the value of m can be a value within (1, 5), for example, m is 4.5. Figure 10 As shown, in some embodiments, the first current mirror includes four P-MOSFETs, namely PM1, PM2, PM3, and PM4; wherein the sources of PM2 and PM4 are both connected to the power supply voltage VDD of the read circuit, and their gates are commonly connected to the bit line (BL) where the target memory cell is located; the source of PM3 is connected to the drain of PM4, the source of PM1 is connected to the drain of PM2, the drain of PM1 is connected to the bit line where the target memory cell is located, and the gates of PM1 and PM3 are commonly connected to the first current mirror enable signal ENb. The aspect ratio of a MOSFET refers to the ratio of the lateral dimension to the longitudinal dimension of the transistor channel. In some embodiments, PM3 and PM4 have the same aspect ratio, PM1 and PM2 have the same aspect ratio, and the aspect ratio of PM3 and PM4 is m times the aspect ratio of PM1 and PM2. Therefore, the current on the PM3 and PM4 side is m times the current on the PM1 and PM2 side, that is, the amplified current is m times the characteristic current.

[0054] In some embodiments, the conversion module includes a second current mirror that converts the amplified current into a pull-down current for reading the input signal, and the amplified current and the pull-down current are of the same magnitude. Figure 10As shown, in some embodiments, the second current mirror includes four N-MOSFETs, namely NM1, NM2, NM3, and NM4. Among them, the gates of NM3 and NM4 are commonly connected to the second current mirror enable signal EN. The drain of NM3 is connected to the drain of PM3, the drain of NM4 is connected to the read input signal, the sources of NM2 and NM1 are grounded, the drain of NM1 is connected to the source of NM3, the drain of NM2 is connected to the source of NM4, and the gates of NM1 and NM2 are commonly connected to the drain of PM3. In some embodiments, the read circuit controls the operating states of the two current mirrors through the first current mirror enable signal ENb and the second current mirror enable signal EN.

[0055] Figure 11 FIG. shows an exemplary schematic diagram of a non-volatile two-terminal memory read circuit in some embodiments of the present invention. Figure 11 The shown read circuit can be understood as being obtained by introducing Figure 5 the shown conversion module on the basis of the shown read circuit. Therefore, Figure 10 objects with the same names in Figure 11 and Figure 5 indicate the same devices or signals. The explanations of Figure 10 and Figure 5 in the previous text are equally applicable to Figure 10 , and will not be elaborated here. Figure 11

[0056] Figure 12 FIG. shows a timing diagram of a non-volatile two-terminal memory read circuit in some embodiments of the present invention. According to Figure 12 it can be understood that the process of the read circuit obtaining the data stored in the storage unit includes three stages: In the first stage, PRGb and SAENb are turned on to pre-charge the bit line and the read input signal SA_IN.

[0057] In the second stage, the switch unit is turned on to generate a characteristic current i_cell flowing through the target storage unit. The first current mirror amplifies the characteristic current into an amplified current, and the magnitude of the amplified current is m*i_cell. The amplified current is compared with the pull-down current and the pull-up current i_bias as a comparison current to generate the read input signal SA_IN of the sense amplifier. When the target storage unit is in a low-resistance state, m*i_cell >> i_bias, so SA_IN will quickly discharge to a low voltage state. When the target storage unit is in a high-resistance state, m*i_cell < i_bias, and SA_IN will remain at the high voltage pre-charged in the first stage.

[0058] In the third stage, the sense amplifier compares the voltage difference between the read input signal and the reference voltage and outputs it to the latch Latch. The read operation ends, and the read input signal and the bit line are reset to a low level.

[0059] It can be understood that the non-volatile two-terminal memory read circuit provided by the present invention uses a current mirror to amplify the sampled characteristic current, which can physically block the connection between the input end of the sensitive sensor and the parasitic resistance capacitance of the bit line. On the one hand, this increases the current of the read operation, while reducing the parasitic resistance capacitance load of the bit line seen by the input end of the sensitive sensor, thereby improving the voltage and charging speed of the bit line pre-charge and accelerating the discharge speed of the input end of the sensitive sensor. Although the characteristic current is amplified when reading the high-resistance state, the characteristic current in the high-resistance state is generally less than 1 μA. When designing the circuit, controlling the amplification factor m can still make m*i_cell < i_bias; when reading the low-resistance state, the characteristic current is generally greater than 10 μA, so the characteristic current in the low-resistance state will be much greater than i_bias after amplification, thereby increasing the read margin.

[0060] The present invention also discloses a non-volatile two-terminal memory, which includes the circuit according to the foregoing embodiments.

[0061] The present invention also discloses a method for reading a non-volatile two-terminal memory. The memory includes at least one non-volatile two-terminal storage unit, and the non-volatile two-terminal storage unit at least includes a switch unit and a non-volatile two-terminal storage cell; the method includes: pre-charging the word line to generate a characteristic current flowing through the storage cell; amplifying the characteristic current to obtain an amplified current; using the amplified current to pull down the read input signal; using a pull-up current to pull up the read input signal; and outputting the stored data of the non-volatile two-terminal storage cell according to the read input signal.

[0062] Corresponding to the non-volatile two-terminal memory read circuit disclosed in the present invention as described above, the present invention discloses the following embodiments for the method of reading a non-volatile two-terminal memory: In some embodiments, the method further includes: pre-charging the storage cell through the power supply voltage of the read circuit of the memory; and using a pre-charge switch to control the power supply voltage to pre-charge the storage cell.

[0063] In some embodiments, the method further includes: using a differential signal amplifier to output the stored data according to the difference between the read input signal and the reference signal.

[0064] In some embodiments, the differential signal amplifier includes a latch formed by cross-coupling a first inverter and a second inverter; the method further includes: using the latch to output the stored data according to the difference between the read input signal and the reference signal.

[0065] In some embodiments, the method further includes: using a first current mirror to amplify the characteristic current by a predetermined ratio to obtain an amplified current; and using a second current mirror to convert the amplified current into a pull-down current.

[0066] In summary, the specific functions implemented by the non-volatile two-ended memory and the non-volatile two-ended memory reading method provided in the embodiments of this specification can be explained in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments. Therefore, they will not be repeated here.

[0067] It should be noted that, for the sake of brevity, this invention describes some methods and their embodiments as a series of actions and combinations thereof. However, those skilled in the art will understand that the solution of this invention is not limited to the order of the described actions. Therefore, based on the disclosure or teachings of this invention, those skilled in the art will understand that some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art will understand that the embodiments described in this invention can be considered as optional embodiments, that is, the actions or modules involved are not necessarily essential for the implementation of one or more solutions of this invention. In addition, depending on the solution, the description of some embodiments of this invention also has different emphases. In view of this, those skilled in the art will understand that parts not described in detail in a certain embodiment of this invention can also refer to the relevant descriptions of other embodiments.

Claims

1. A non-volatile two-dimensional memory read circuit, characterized in that, The non-volatile two-terminal memory includes at least one non-volatile two-terminal storage section, the non-volatile two-terminal storage section includes at least a switching unit and non-volatile two-terminal storage units, and the read circuit includes: A pre-charge module configured to pre-charge the bit line to generate a characteristic current flowing through the memory cell; The conversion module is configured as follows: Amplify the characteristic current to obtain an amplified current; and The amplified current is used to pull down and read the input signal; A bias module configured to generate a pull-up current for pulling up the read input signal; The read module is configured to output the stored data of the non-volatile two-terminal storage unit according to the read input signal.

2. The circuit according to claim 1, characterized in that, The pre-charging module includes a pre-charging switch, a first pre-charging terminal, and a second pre-charging terminal. The pre-charge switch is connected to the power supply voltage of the reading circuit through the pre-charge first terminal; The precharge switch is connected to the first end of the non-volatile two-terminal storage unit via the second precharge terminal.

3. The circuit according to claim 1, characterized in that, The reading module includes a differential signal amplifier; The differential signal amplifier is configured to output the stored data based on the difference between the read input signal and the reference signal.

4. The circuit according to claim 3, characterized in that, The differential signal amplifier includes a latch consisting of a first inverter and a second inverter cross-coupled.

5. The circuit according to claim 3, characterized in that, The conversion module includes: A first current mirror, configured to amplify the characteristic current by a predetermined ratio to obtain the amplified current; and / or A second current mirror is configured to convert the amplified current into a pull-down current for pulling down the read input signal.

6. A non-volatile two-dimensional memory, comprising the circuitry according to any one of claims 1-5.

7. A method for reading a non-volatile two-ended memory, the memory comprising at least one non-volatile two-ended storage section, the non-volatile two-ended storage section comprising at least a switching unit and non-volatile two-ended storage cells, characterized in that, include: The word lines are pre-charged to generate a characteristic current flowing through the memory cell; The characteristic current is amplified to obtain an amplified current; The amplified current is used to pull down and read the input signal; Use a pull-up current to pull up the read input signal; as well as The stored data of the non-volatile two-terminal storage unit is output according to the read input signal.

8. The method according to claim 7, characterized in that: The memory cell is pre-charged using the power supply voltage of the memory's read circuit; and A precharge switch is used to control the power supply voltage to precharge the memory cell.

9. The method according to claim 7, characterized in that, A differential signal amplifier is used to output the stored data based on the difference between the read input signal and the reference signal.

10. The method according to claim 9, wherein the differential signal amplifier comprises a latch consisting of a first inverter and a second inverter cross-coupled; characterized in that, The latch is used to output the stored data based on the difference between the read input signal and the reference signal.

11. The method according to claim 7, characterized in that: The characteristic current is amplified by a first current mirror at a set ratio to obtain the amplified current; and A second current mirror is used to convert the amplified current into a pull-down current.

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