多通道高速低功耗逐次逼近型模数转换器、系统和方法
By designing a multi-channel structure and a non-binary DAC capacitor array, combined with a digital error correction circuit, the power consumption and speed issues of traditional SARADCs in high-precision and high-speed applications are solved, realizing a low-power, high-conversion-speed, and high-precision analog-to-digital converter design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI UNIV
- Filing Date
- 2025-08-26
- Publication Date
- 2026-07-17
AI Technical Summary
Traditional successive approximation analog-to-digital converters (SARADCs) are difficult to design with low power consumption in high-precision and high-speed applications. The large size of the capacitor array leads to chip area expansion, slow conversion speed and high power consumption, and capacitor matching and parasitic effects seriously affect conversion accuracy.
It adopts a multi-channel structure, combining an auxiliary ADC and a main ADC, using a non-binary DAC capacitor array and digital error correction circuit, and realizes multi-channel sampling, quantization and output through a multiplexer, eliminating the need for high-level capacitor switching of the main ADC, reducing power consumption and improving conversion speed and accuracy.
While maintaining low power consumption, it improves the conversion speed and accuracy of the analog-to-digital converter, achieving the dual goals of chip area reduction and economic benefits, and solving the performance bottleneck of traditional SARADCs in high-precision and high-speed applications.
Smart Images
Figure CN120979427B_ABST