Relay method and device for enhancing equal-ratio reproduction signal of differential transmission waveform

Abstract

The method comprises the following steps: performing high-speed analog-to-digital conversion under synchronous clock control on a positive electrode signal and a negative electrode signal after common-mode rejection to generate a digital positive electrode data stream and a digital negative electrode data stream; comparing the time sequence and the level state of the digital positive data stream and the negative data stream, and identifying and extracting effective differential data points; based on the time sequence distribution characteristics of the effective differential data points, the phase and frequency of a system bit stream clock are adjusted, and a self-adaptive sampling clock signal is generated; according to the self-adaptive sampling clock signal, performing time sequence alignment and scaling processing on the effective differential data points, and reconstructing a data output stream with an equal bit rate; and converting the reconstructed data output stream into a differential driving signal and outputting the differential driving signal. The problems of waveform distortion, signal duty proportion relation change, noise accumulation and the like in the existing signal transmission through a relay technology are solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of industrial communication and relates to a differential transmission waveform isometric reproduction signal enhancement relay method and device. BACKGROUND

[0002] In an industrial control system, with the expansion of field bus network coverage and the improvement of real-time data interaction requirements, long-distance, high-fidelity signal transmission has become a key technical difficulty. The traditional signal transmission mode has problems such as complex wiring, weak anti-interference ability, serious signal attenuation, and the like, and is difficult to meet the current system requirements for low delay, high synchronism and high reliability.

[0003] Differential communication is widely used in the field of industrial communication due to its good common-mode rejection capability. However, in the process of long-distance transmission, the signal will still be distorted, the duty cycle will change, and noise will accumulate due to line loss, noise introduction and improper relay processing. The existing relay equipment mainly adopts hardware copying or data storage forwarding mode to realize signal enhancement, the former is easy to cause signal distortion and distortion to accumulate with the increase of relay stages, and the latter introduces uncertain delay, affecting the real-time and stability of the system.

[0004] Therefore, it is urgent to propose a relay method and device that can improve the transmission robustness while maintaining the integrity of the signal to meet the application requirements in high-speed and high-reliability scenarios. SUMMARY

[0005] Therefore, the application solves the technical problems of waveform distortion, duty cycle change, noise accumulation and uncontrollable relay delay caused by inaccurate signal sampling, clock desynchronization, non-standard data frame structure and unreasonable bus state control in the existing relay technology.

[0006] The application provides the following technical solutions: A differential transmission waveform isometric reproduction signal enhancement relay method, comprising the following steps: step one: separating the differential signal into a positive path and a negative path, and synchronously performing real-time detection and dynamic filtering of common-mode noise on the positive path and the negative path to generate positive signals and negative signals after common-mode rejection; Step two: performing high-speed analog-to-digital conversion on the positive signals and the negative signals after common-mode rejection under synchronous clock control to generate digital positive data stream and digital negative data stream; comparing the time sequence and level state of the digital positive data stream and the negative data stream, identifying and extracting valid differential data points; Step three: based on the timing distribution characteristics of the effective differential data points, adjust the phase and frequency of the system bit stream clock to generate an adaptive sampling clock signal; according to the adaptive sampling clock signal, perform timing alignment and scaling processing on the effective differential data points to reconstruct an equal-bit-rate data output stream; convert the reconstructed data output stream into a differential drive signal and output.

[0007] In specific implementation, the input differential signal is separated into positive path (P line) and negative path (N line), and common mode noise detection circuit in parallel is used to monitor common mode interference in real time; based on dynamic threshold filtering algorithm, common mode noise is filtered out synchronously to generate positive signal and negative signal after common mode suppression.

[0008] It should be noted that the dynamic filtering algorithm adjusts the filtering parameters according to the real-time noise spectrum to avoid signal distortion caused by fixed filtering. In the actual measurement of industrial environment data, the common mode rejection ratio is more than 80dB.

[0009] Further, the positive / negative signal after common mode suppression is subjected to synchronous clock controlled ADC sampling: a double-channel 12-bit high-speed ADC is used, and the positive / negative sampling is strictly synchronized to the same system clock rising edge; the effective differential data points are identified: the real-time differential value is calculated:

[0010] Through the configurable threshold D th Determine single level, and perform majority voting on multiple sampling results in a single data bit to determine the final level value.

[0011] It should be noted that the weighting coefficient K p And K d Adaptively adjust according to channel impedance; the majority voting mechanism significantly reduces the instantaneous interference error rate.

[0012] Further, the clock adaptation is based on the jump edge trigger period detection of the effective differential data points, and the system bit stream clock phase and frequency are dynamically adjusted through continuous period ratio analysis. In signal reconstruction, the data points are time-aligned according to the adaptive sampling clock, and the equal-bit-rate data stream is reconstructed through the scaling algorithm to eliminate duty cycle distortion. The reconstructed data stream is converted into a differential drive signal conforming to the RS-485 standard; the output signal swing rate control is ±0.5V / ns.

[0013] It should be noted that the scaling algorithm preserves the amplitude ratio relationship of the original signal to realize equal-ratio reproduction of the waveform; the adaptive clock synchronization accuracy is significantly improved, and an equal-bit-rate data output stream is reconstructed, and the reconstructed data output stream is converted into a differential drive signal and output.

[0014] Further improved on the basis of embodiment one, Figure 2 The flow chart of the differential transmission waveform is shown in the embodiment of the application. The identification method comprises: In some embodiments, the comparison of the timing and level state of the digitized positive data stream and the negative data stream, the identification and extraction of the effective differential data points, specifically includes: multiple synchronous sampling is performed in each data bit clock cycle, and the positive sampling value and the negative sampling value are obtained respectively; the real-time difference value is obtained according to the positive sampling value and the negative sampling value, the single-level result is judged by comparing the real-time difference value with the first preset threshold value, and the final level value of a single data bit is determined according to the single-level results of multiple samplings of a single data bit.

[0015] In one possible embodiment, the real-time difference value is obtained according to the positive sampling value and the negative sampling value, the single-level result is judged by comparing the real-time difference value with the first preset threshold value, and the final level value of a single data bit is determined according to the single-level results of multiple samplings of a single data bit, specifically including: when the real-time difference value is greater than the first preset threshold value, the single-level result is judged as a high level; when the real-time difference value is less than the first preset threshold value, the single-level result is judged as a low level; the level results of multiple samplings in a single data bit are processed, when the sum of the multiple processing results is greater than the majority, the final level value of a single data bit is determined as a high level; and when the sum of the multiple processing results is less than or equal to the majority, the final level value of a single data bit is determined as a low level.

[0016] In specific implementation, multiple synchronous samplings are performed in each data bit clock cycle, for example, 8 samplings are performed in each bit cycle, and the positive path sampling value DP ( n ) and the negative path sampling value DN ( n ) are captured simultaneously; the real-time difference value is calculated according to the formula:

[0017] The real-time difference value is compared with the first preset threshold value D ( n ): D th If D ( n )>, D th the single sampling is determined as a high level, and the value is 1.

[0018] If D ( n )< D th ​If the single sample is low, assign 0 to the data bit.

[0019] Sum all the samples in a single data bit period: Determine the final level according to the accumulated value: If the accumulated value is greater than 0, the final level of the data bit is high. If the accumulated value is less than 0, the final level of the data bit is low.

[0020] It should be noted that by sampling each data bit 8 times and using the majority value strategy, the error rate is effectively reduced and the signal recognition accuracy is improved.

[0021] In some embodiments, the step of adjusting the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the effective differential data points to generate an adaptive sampling clock signal specifically includes: triggering a period detection process by the signal transition edge of the effective differential data points; capturing the actual duration sequence of consecutive signal periods within a fixed time window; calculating the ratio of the average duration of consecutive signal periods in the sequence to the reference period; when the ratio continuously meets the preset tolerance condition, locking the current clock frequency and updating the reference period of the system bit stream clock; when the ratio exceeds the preset tolerance range, triggering the next round of synchronization cycle based on the current actual period sequence.

[0022] In specific implementation, the rising edge / falling edge of the effective differential data points is used to trigger period detection, and the edge detection sensitivity is configurable; within a fixed time window, for example, 16 clocks by default, consecutive signal periods are captured, and the high / low level duration sequence is recorded in real time: the ratio of the average duration of consecutive M periods to the reference period is calculated: the reference period takes the first complete period value. When the ratio continuously meets the preset tolerance condition, the current clock frequency is locked and the reference period of the system bit stream clock is updated; when the ratio exceeds the preset tolerance range, the next round of synchronization cycle is triggered based on the current actual period sequence.

[0023] It should be noted that the window expansion mechanism can improve the capture success rate in a noisy environment, and the continuous tolerance determination avoids false locking caused by instantaneous interference.

[0024] In one possible embodiment, the actual duration sequence of consecutive signal periods is composed of alternating high level duration and low level duration; the ratio calculation is only performed when all high level periods and low level periods form a complete period combination; the step of locking the current clock frequency includes: synchronously adjusting the clock phase compensation amount and the frequency division coefficient according to the ratio result; the step of triggering the next round of synchronization cycle includes: resetting the period capture counter and dynamically expanding the capture duration of the fixed time window.

[0025] In implementation, the period detection window is triggered by detecting signal edge jump, and the length of high and low level period is captured in fixed time window. Based on 16 period window analysis, if the ratio of subsequent period to the first period is within the preset threshold range, the current clock frequency is confirmed, and the reference clock is updated; otherwise, the next period comparison is continued until the correct frequency is locked. This mechanism ensures that the repeater can dynamically adapt to the clock frequency change of the host or slave, avoiding data misplacement caused by clock drift.

[0026] In some embodiments, the timing alignment and scaling processing of the valid differential data points according to the adaptive sampling clock signal to reconstruct an equal bit rate data output stream comprises: assembling the valid differential data points into a standardized data frame structure; the standardized data frame structure comprises: a start bit represented by low level for a plurality of continuous clock periods; a data bit arranged in the order of high bit first for a plurality of continuous clock periods; a stop bit represented by high level for a plurality of continuous clock periods; wherein the clock period ratio of the start bit, data bit and stop bit is a fixed value, and the sum of the period number of the start bit and stop bit is greater than the period number of the data bit.

[0027] In implementation, after detecting valid data, a data frame is automatically assembled according to the format of “4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)”. The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window.

[0028] In one possible embodiment, the standardized data frame is protocol parsed to identify the start bit, data bit and stop bit; a timeout detection is synchronously started, when the stop bit is not completely received within a plurality of continuous clock periods from the start bit, it is determined that the communication is timed out and the receiving state is reset; the length of the timeout detection is proportional to the total period number of the standardized data frame.

[0029] In implementation, the received signal is protocol parsed to identify the start bit, data bit and stop bit. At the same time, a timeout detection mechanism of 16 clock periods is set, if the data reception is not completed within the specified time, it is determined that the communication fails and the receiving state is reset. This mechanism ensures the integrity and consistency of data reception.

[0030] In one possible embodiment, in the process of converting the reconstructed data output stream into a differential driving signal and outputting: the bus enable signal is continuously maintained in an effective state within the complete transmission period of the data frame; the complete transmission period covers the period from the start bit to the end of the stop bit; when the bus enable signal is in an effective state, the bus is prohibited from entering a high resistance state.

[0031] In a specific implementation, after detecting valid data, the data frame is automatically assembled in the format of "4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)". The sending process strictly follows the rising edge trigger of the system clock to ensure that the center of the data window is aligned. At the same time, the sending enable is kept high during the entire data period to prevent the bus from entering a high resistance state. After each group of data is sent, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus remains in a high resistance state, the current communication is terminated.

[0032] In some embodiments, according to any of the above embodiments, after completing the sending of a group of standardized data frames: a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely sent; no low-level signal corresponding to a new start bit is detected within a plurality of continuous clock cycles; the bus state remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames.

[0033] In a specific implementation, after completing the sending of a group of standardized data frames: a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely sent; no low-level signal corresponding to a new start bit is detected within a plurality of continuous clock cycles; the bus state remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames. After each group of data is sent, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus remains in a high resistance state, the current communication is terminated.

[0034] In a second aspect, the application also provides a schematic block diagram of a relay device for enhancing the isometric reproduction of a differential transmission waveform signal, which comprises: an adaptive common-mode filtering module for synchronously performing real-time detection and dynamic filtering of common-mode noise on the positive path and the negative path to generate positive signals and negative signals after common-mode suppression; a high-speed ADC sampling module for performing high-speed analog-to-digital conversion of the positive signals and the negative signals after common-mode suppression under the control of a synchronous clock to generate digitized positive data stream and digitized negative data stream; a data extraction game module for comparing the timing and level state of the digitized positive data stream and the negative data stream, identifying and extracting valid differential data points; an adaptive clock algorithm unit for adjusting the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the valid differential data points to generate an adaptive sampling clock signal; a data isometric reproduction module for performing timing alignment and proportional scaling processing on the valid differential data points according to the adaptive sampling clock signal to reconstruct an isometric rate data output stream; and a bus driving module for converting the reconstructed data output stream into a differential driving signal and outputting the differential driving signal.

[0035] Specifically, the relay device comprises an adaptive common-mode filtering module, which separates the input differential signal into a positive path (P line) and a negative path (N line), and monitors common-mode interference in real time through a common-mode noise detection circuit in parallel with the double paths; based on a dynamic threshold filtering algorithm, the common-mode noise is filtered out synchronously to generate positive and negative signals after common-mode suppression.

[0036] It should be noted that the dynamic filtering algorithm adjusts the filtering parameters according to the real-time noise spectrum, avoiding signal distortion caused by fixed filtering. In the actual industrial environment data, the common-mode rejection ratio reaches more than 80dB.

[0037] Further, a high-speed ADC sampling module is used for high-speed analog-to-digital conversion of the positive and negative signals after common-mode suppression under the control of a synchronous clock, to generate digitized positive and negative data streams. Specifically, the positive / negative signals after common-mode suppression are subjected to synchronous clock-controlled ADC sampling: a double-channel 12-bit high-speed ADC is used, and the positive / negative sampling is strictly synchronized to the rising edge of the same system clock; effective differential data points are identified: the real-time differential value is calculated:

[0038] The configurable threshold D th determines the final level value by majority voting on the multiple sampling results in a single data bit.

[0039] It should be noted that the weighting coefficient K p and K d is adaptively adjusted according to the channel impedance; the majority voting mechanism significantly reduces the instantaneous interference misjudgment rate.

[0040] Further, a data extraction game module is used for comparing the timing and level state of the digitized positive and negative data streams, identifying and extracting effective differential data points; comparing the timing and level state of the digitized positive and negative data streams, identifying and extracting effective differential data points, specifically including: multiple synchronous sampling is performed in each data bit clock period to obtain positive and negative sampling values; the real-time difference value is obtained according to the positive and negative sampling values, and the single level result is determined by comparing the real-time difference value with a first preset threshold; the final level value of a single data bit is determined according to the single level result of multiple samplings of a single data bit.

[0041] In one possible embodiment, the real-time difference value is obtained according to the positive electrode sampling value and the negative electrode sampling value, the single-level result is determined by comparing the real-time difference value with a first preset threshold value, the final level value of a single data bit is determined according to the single-level results of multiple samplings of the single data bit, and specifically, when the real-time difference value is greater than the first preset threshold value, the single-level result is determined as a high level; when the real-time difference value is less than the first preset threshold value, the single-level result is determined as a low level; the level results of multiple samplings in a single data bit are processed, when the sum of the multiple processing results is greater than a majority, the final level value of the single data bit is determined as a high level; and when the sum of the multiple processing results is less than or equal to the majority, the final level value of the single data bit is determined as a low level.

[0042] In a specific implementation, multiple synchronous samplings are performed on each data bit clock cycle, for example, 8 samplings are performed on each bit cycle, and the positive electrode path sampling value DP ( n ) and the negative electrode path sampling value DN ( n ) are captured simultaneously; a real-time difference value is calculated according to a formula:

[0043] D ( n ) is compared with a first preset threshold value D th : If D ( n )> D th , it is determined that the single sampling is a high level, and the value is 1.

[0044] If D ( n )< D th , it is determined that the single sampling is a low level, and the value is 0.

[0045] The sum of all sampling results in a single data bit cycle is calculated: The final level is determined according to the accumulated value: When the final level is a high level, the data bit final level is a high level. When the final level is a low level, the data bit final level is a low level.

[0046] It should be noted that by performing 8 samplings on each data bit and adopting the majority value strategy, the bit error rate is effectively reduced, and the signal recognition accuracy is improved.

[0047] ​​​Further, the adaptive clock algorithm unit adjusts the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the effective differential data points to generate an adaptive sampling clock signal, specifically including: triggering a period detection process through the signal edge jump of the effective differential data points; capturing the actual duration sequence of consecutive signal periods within a fixed time window; calculating the ratio of the average duration of consecutive signal periods in the sequence to the reference period; when the ratio continuously meets the preset tolerance condition, locking the current clock frequency and updating the reference period of the system bit stream clock; when the ratio exceeds the preset tolerance range, triggering the next round of synchronization cycle based on the current actual period sequence.

[0048] In specific implementation, the rising edge / descending edge of the effective differential data points is used to trigger period detection, and the edge detection sensitivity can be configured; within a fixed time window, for example, 16 clocks by default, consecutive signal periods are captured, and the high / low level duration sequence is recorded in real time: the ratio of the average duration of consecutive M periods to the reference period is calculated: the reference period takes the first complete period value. When the ratio continuously meets the preset tolerance condition, the current clock frequency is locked and the reference period of the system bit stream clock is updated; when the ratio exceeds the preset tolerance range, the next round of synchronization cycle is triggered based on the current actual period sequence.

[0049] It should be noted that the window expansion mechanism can improve the capture success rate in a noisy environment, and the continuous tolerance determination avoids false locking caused by instantaneous interference.

[0050] In one possible embodiment, the actual duration sequence of the consecutive signal periods is composed of alternating high level duration and low level duration; the ratio calculation is only performed when all high level periods and low level periods form a complete period combination; the step of locking the current clock frequency includes: synchronously adjusting the clock phase compensation amount and the frequency division coefficient according to the ratio result; the step of triggering the next round of synchronization cycle includes: resetting the period capture counter and dynamically expanding the capture duration of the fixed time window.

[0051] In specific implementation, the period detection window is triggered by detecting the signal edge jump, and the high / low level period length is captured within a fixed time window. Based on 16-period window analysis, if the ratio of the subsequent period to the first period is within the preset threshold range, the current clock frequency is confirmed, and the reference clock is updated; otherwise, the next period comparison is continued until the correct frequency is locked. This mechanism ensures that the repeater can dynamically adapt to the clock frequency change of the host or slave, avoiding data misplacement caused by clock drift.

[0052] Further, a data isometric reproduction module is configured to perform timing alignment and proportional scaling processing on the effective differential data points according to the adaptive sampling clock signal to reconstruct an isometric bit rate data output stream.

[0053] In this embodiment, the data isoparic reproduction module can perform timing alignment and scaling processing on the effective differential data points according to the adaptive sampling clock signal to reconstruct an isoparic bit rate data output stream, including: assembling the effective differential data points into a standardized data frame structure; the standardized data frame structure includes: a start bit represented by a low level for a plurality of continuous clock periods; a data bit arranged in the order of high bit first for a plurality of continuous clock periods; a stop bit represented by a high level for a plurality of continuous clock periods; wherein the clock period ratio of the start bit, the data bit and the stop bit is a fixed value, and the sum of the clock period of the start bit and the stop bit is greater than the clock period of the data bit.

[0054] In specific implementation, after detecting valid data, a data frame is automatically assembled in the format of “4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)”. The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window.

[0055] In a possible embodiment, the standardized data frame is protocol-analyzed to identify the start bit, the data bit and the stop bit; a timeout detection is synchronously started, when the stop bit is not completely received within a plurality of continuous clock periods starting from the start bit, it is determined that the communication is timed out and the receiving state is reset; the length of the timeout detection is proportional to the total number of clock periods of the standardized data frame.

[0056] In specific implementation, the received signal is protocol-analyzed to identify the start bit, the data bit and the stop bit. At the same time, a 16-clock-period timeout detection mechanism is set, if the data reception is not completed within the specified time, it is determined that the communication fails and the receiving state is reset. This mechanism ensures the integrity and consistency of data reception.

[0057] In a possible embodiment, in the process of converting the reconstructed data output stream into a differential driving signal and outputting: the bus enable signal is continuously maintained in an effective state within the complete transmission period of the data frame; the complete transmission period covers the period from the start bit to the end of the stop bit; when the bus enable signal is in the effective state, the bus is prohibited from entering the high resistance state.

[0058] In specific implementation, after detecting valid data, a data frame is automatically assembled in the format of “4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)”. The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window. At the same time, the sending enable is maintained at a high level during the entire data period to prevent the bus from entering the high resistance state. After each group of data transmission is completed, a 16-bit period silence detection mechanism is started, if there is no new start signal and the bus is continuously in the high resistance state, the current communication is terminated.

[0059] Further, a bus driving module is configured to convert the reconstructed data output stream into a differential driving signal and output the differential driving signal.

[0060] In this embodiment, after a set of standardized data frames are transmitted, a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely transmitted; no new start bit corresponding to a low level signal is detected within a plurality of continuous clock cycles; the bus state continuously remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames.

[0061] In particular implementation, after a set of standardized data frames are transmitted, a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely transmitted; no new start bit corresponding to a low level signal is detected within a plurality of continuous clock cycles; the bus state continuously remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames. After each set of data transmission is completed, a silence period detection mechanism of 16-bit period is started, and if there is no new start signal and the bus continuously remains at a high resistance state, the current communication is terminated.

[0062] As described above, by using the technical solutions, the present application solves the technical problems of waveform distortion, duty cycle variation, noise accumulation and uncontrollable relay delay caused by inaccurate signal sampling, clock desynchronization, non-standard data frame structure and unreasonable bus state control in the existing relay technology, significantly improves the stability, robustness and real-time performance of signal transmission, and is suitable for long-distance, high-precision and high real-time industrial communication systems.

[0063] In order to make the above objectives, features and advantages of the present application more apparent and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0065] Figure 1 Fig. 1 shows one of the flow diagrams of the differential transmission waveform equal proportion replication signal enhanced relay method of the embodiments of the present application; Figure 2Fig. 2 shows a flow diagram of a method for relaying a differential transmission waveform isometric signal enhanced signal according to an embodiment of the present application; Figure 3 Fig. 3 shows a schematic block diagram of a relaying device for relaying a differential transmission waveform isometric signal enhanced signal according to an embodiment of the present application. DETAILED DESCRIPTION

[0066] Embodiments of the present application are described in detail below with reference to the accompanying drawings, wherein the same or similar notations used throughout the drawings and the specification denote the same or similar elements or elements with the same or similar functions. The embodiments described below are exemplary only, and are used to explain the present application, but are not to be understood as limiting the present application.

[0067] In the present application, unless specifically defined and limited otherwise, the terms "mounting", "connected", "connection", "fixed", and the like are to be construed broadly, for example, can be fixed connection, can be detachable connection, or can be integrated; can be mechanical connection, or can be electrical connection; can be directly connected, or can be indirectly connected through an intermediate medium; can be internal communication of two elements, or can be interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0068] In the present application, unless specifically defined and limited otherwise, the first feature is "on" or "under" the second feature, which can be direct contact between the first and second features, or indirect contact between the first and second features through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0069] The differential transmission waveform isometric signal enhanced relaying method and device according to the present application, the specific implementation steps are as follows: Embodiment one: Figure 1 Fig. 1 shows a flow diagram of a method for relaying a differential transmission waveform isometric signal enhanced signal according to an embodiment of the present application, which includes: Step one: separate the differential signal into positive and negative paths, and perform real-time detection and dynamic filtering of common-mode noise on the positive and negative paths simultaneously to generate positive and negative signals after common-mode rejection; Step two: high-speed analog-to-digital conversion of the positive signal and the negative signal after common-mode suppression under synchronous clock control to generate digitized positive data stream and digitized negative data stream; comparison of the timing and level state of the digitized positive data stream and the negative data stream to identify and extract valid differential data points; Step three: adjustment of the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the valid differential data points to generate an adaptive sampling clock signal; timing alignment and proportional scaling processing of the valid differential data points according to the adaptive sampling clock signal to reconstruct an equal-bit-rate data output stream; conversion of the reconstructed data output stream into a differential drive signal and output.

[0070] In specific implementation, the input differential signal is separated into a positive path (P line) and a negative path (N line), and a common-mode noise detection circuit in parallel with the double paths is used to monitor common-mode interference in real time; a dynamic threshold filtering algorithm is used to filter out common-mode noise synchronously to generate positive and negative signals after common-mode suppression.

[0071] It should be noted that the dynamic filtering algorithm adjusts the filtering parameters according to the real-time noise spectrum to avoid signal distortion caused by fixed filtering. In the actual measurement of industrial environment data, the common-mode rejection ratio is more than 80 dB.

[0072] Further, the positive / negative signals after common-mode suppression are subjected to synchronous clock-controlled ADC sampling: a double-channel 12-bit high-speed ADC is used, and the positive / negative sampling is strictly synchronized to the rising edge of the same system clock; valid differential data points are identified: the real-time differential value is calculated:

[0073] Through a configurable threshold D th Determine a single level, and perform majority voting on multiple sampling results within a single data bit to determine the final level value.

[0074] It should be noted that the weighting coefficient K p And K d Adaptive adjustment according to channel impedance; the majority voting mechanism significantly reduces the instantaneous interference error rate.

[0075] Further, clock adaptation is based on the jump edge trigger period detection of valid differential data points, and the system bit stream clock phase and frequency are dynamically adjusted through continuous period ratio analysis. During signal reconstruction, the data points are time-aligned according to the adaptive sampling clock, and an equal-bit-rate data stream is reconstructed through a proportional scaling algorithm to eliminate duty cycle distortion. Differential drive output: the reconstructed data stream is converted into a differential drive signal that meets the RS-485 standard; the output signal swing rate control is ±0.5V / ns.

[0076] It should be noted that the proportional scaling algorithm preserves the original signal amplitude ratio, realizes isometric reproduction of waveforms, significantly improves the adaptive clock synchronization accuracy, reconstructs an isometric bit rate data output stream, and converts the reconstructed data output stream into a differential driving signal and outputs the same.

[0077] On the basis of Embodiment One, further improvements are made, Figure 2 A flowchart of a differential transmission waveform isometric reproduction signal enhanced relay method of an embodiment of the application is shown, and the identification method comprises: In some embodiments, the comparison of the timing and level state of the digitized positive electrode data stream and the negative electrode data stream, the identification and extraction of valid differential data points specifically comprises: multiple synchronous samplings are performed within each data bit clock cycle to obtain positive sampling values and negative sampling values respectively; real-time difference values are obtained according to the positive sampling values and the negative sampling values, a single level result is determined by comparing the real-time difference values with a first preset threshold value; and a final level value of a single data bit is determined according to the single level results of multiple samplings of the single data bit.

[0078] In one possible embodiment, the obtaining of real-time difference values according to the positive sampling values and the negative sampling values, the determination of a single level result by comparing the real-time difference values with a first preset threshold value, and the determination of a final level value of a single data bit according to the single level results of multiple samplings of the single data bit specifically comprise: when the real-time difference value is greater than the first preset threshold value, the single level is determined to represent a high level; when the real-time difference value is less than the first preset threshold value, the single level is determined to represent a low level; the level results of multiple samplings within a single data bit are processed, and when a sum value of the multiple processing results is greater than a majority, the final level value of the single data bit is determined to be a high level; and when the sum value of the multiple processing results is less than or equal to the majority, the final level value of the single data bit is determined to be a low level.

[0079] In specific implementation, multiple synchronous samplings are performed for each data bit clock cycle, for example, 8 samplings are performed for each bit cycle, and positive path sampling values DP ( n ) and negative path sampling values DN ( n ) are captured simultaneously;

[0080] D ( n ) is compared with a first preset threshold value D th D ( n ) D ​​​th If the single sample is high, assign 1.

[0081] If D ( n )< D th If the single sample is low, assign 0.

[0082] Sum all the samples in a single data bit period: Determine the final level according to the accumulated value: If the accumulated value is greater than 4, the final level of the data bit is high; If the accumulated value is less than 4, the final level of the data bit is low.

[0083] It should be noted that by sampling each data bit 8 times and using the majority value strategy, the error rate is effectively reduced and the signal recognition accuracy is improved.

[0084] In some embodiments, based on the timing distribution characteristics of the effective differential data points, the phase and frequency of the system bit stream clock are adjusted to generate an adaptive sampling clock signal, specifically including: triggering a period detection process through the signal transition edge of the effective differential data points; capturing the actual duration sequence of consecutive signal periods within a fixed time window; calculating the ratio of the average duration of consecutive multiple signal periods in the sequence to the reference period; when the ratio continuously satisfies the preset tolerance condition, locking the current clock frequency and updating the reference period of the system bit stream clock; when the ratio exceeds the preset tolerance range, triggering the next round of synchronization cycle based on the current actual period sequence.

[0085] In specific implementation, the rising edge / falling edge of the effective differential data points is used to trigger period detection, and the edge detection sensitivity is configurable; within a fixed time window, for example, 16 clocks by default, consecutive signal periods are captured within the period, and the high / low level duration sequence is recorded in real time: the ratio of the average duration of consecutive M periods to the reference period is calculated: the reference period takes the first complete period value. When the ratio continuously satisfies the preset tolerance condition, the current clock frequency is locked and the reference period of the system bit stream clock is updated; when the ratio exceeds the preset tolerance range, the next round of synchronization cycle is triggered based on the current actual period sequence.

[0086] It should be noted that the window expansion mechanism can improve the capture success rate in a noisy environment, and the continuous tolerance determination avoids false locking caused by instantaneous interference.

[0087] In one possible embodiment, the actual duration sequence of the continuous signal period is composed of alternating high level duration and low level duration; the ratio calculation is only performed when all high level periods and low level periods form a complete period combination; the step of locking the current clock frequency includes: synchronously adjusting the clock phase compensation amount and the frequency division coefficient according to the ratio result; the step of triggering the next round of synchronization cycle includes: resetting the period capture counter and dynamically extending the capture duration of the fixed time window.

[0088] In implementation, the period detection window is triggered by detecting signal edge transition, and the high and low level period length is captured within the fixed time window. Based on 16 period window analysis, if the ratio of the subsequent period to the first period is within the preset threshold range, the current clock frequency is confirmed, and the reference clock is updated; otherwise, the next period comparison is continued until the correct frequency is locked. This mechanism ensures that the repeater can dynamically adapt to the clock frequency change of the host or slave, avoiding data misplacement caused by clock drift.

[0089] In some embodiments, the timing alignment and scaling processing of the valid differential data points according to the adaptive sampling clock signal to reconstruct an equal bit rate data output stream includes: assembling the valid differential data points into a standardized data frame structure; the standardized data frame structure includes: a start bit represented by a low level for a plurality of continuous clock periods; a data bit arranged in the order of high bit first for a plurality of continuous clock periods; a stop bit represented by a high level for a plurality of continuous clock periods; wherein the clock period number ratio of the start bit, data bit and stop bit is a fixed value, and the sum of the period numbers of the start bit and stop bit is greater than the period number of the data bit.

[0090] In implementation, after detecting valid data, a data frame is automatically assembled in the format of "4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)". The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window.

[0091] In one possible embodiment, the standardized data frame is protocol parsed to identify the start bit, data bit and stop bit; a timeout detection is synchronously started, and when the stop bit is not completely received within the plurality of continuous clock periods starting from the start bit, it is determined that the communication is timed out and the receiving state is reset; the length of the timeout detection is proportional to the total period number of the standardized data frame.

[0092] In implementation, the received signal is protocol parsed to identify the start bit, data bit and stop bit. At the same time, a timeout detection mechanism of 16 clock periods is set, and if the data reception is not completed within the specified time, it is determined that the communication fails and the receiving state is reset. This mechanism ensures the integrity and consistency of data reception.

[0093] In one possible embodiment, in the process of converting the reconstructed data output stream into a differential drive signal and outputting: the bus enable signal is kept active during the entire transmission period of a data frame; the entire transmission period covers the period from the start bit to the stop bit; when the bus enable signal is active, the bus is prohibited from entering a high impedance state.

[0094] In specific implementation, after detecting valid data, a data frame is automatically assembled in the format of "4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)". The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window. At the same time, the sending enable is kept high during the entire data period to prevent the bus from entering a high impedance state. After each group of data is sent, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus is continuously in a high impedance state, the current communication is terminated.

[0095] In some embodiments, according to any one of the above embodiments, after completing the sending of a group of standardized data frames: start the silence period determination process and continuously monitor the bus state; when the following conditions are met simultaneously, release the bus control right: the stop bit of the current data frame has been completely sent; no low-level signal corresponding to the new start bit is detected within a plurality of continuous clock cycles; the bus state continuously stays at a preset idle level; the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames.

[0096] In specific implementation, after completing the sending of a group of standardized data frames: start the silence period determination process and continuously monitor the bus state; when the following conditions are met simultaneously, release the bus control right: the stop bit of the current data frame has been completely sent; no low-level signal corresponding to the new start bit is detected within a plurality of continuous clock cycles; the bus state continuously stays at a preset idle level; the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames. After each group of data is sent, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus is continuously in a high impedance state, the current communication is terminated.

[0097] Embodiment Two Figure 3A schematic block diagram of a relay device for enhancing the isometric reproduction signal of a differential transmission waveform of an embodiment of the present application is shown, and the relay device comprises: an adaptive common-mode filtering module, configured to perform real-time detection and dynamic filtering of common-mode noise on the positive path and the negative path synchronously, to generate positive signals and negative signals after common-mode suppression; a high-speed ADC sampling module, configured to perform high-speed analog-digital conversion of the positive signals and the negative signals after common-mode suppression under synchronous clock control, to generate digitized positive data stream and digitized negative data stream; a data extraction game module, configured to compare the time sequence and level state of the digitized positive data stream and the negative data stream, to identify and extract valid differential data points; an adaptive clock algorithm unit, configured to adjust the phase and frequency of the system bit stream clock based on the time sequence distribution characteristics of the valid differential data points, to generate an adaptive sampling clock signal; a data isometric reproduction module, configured to perform time sequence alignment and proportional scaling processing on the valid differential data points according to the adaptive sampling clock signal, to reconstruct an isometric rate data output stream; and a bus driving module, configured to convert the reconstructed data output stream into a differential driving signal and output the differential driving signal.

[0098] Specifically, the relay device comprises an adaptive common-mode filtering module, which separates the input differential signal to a positive path (P line) and a negative path (N line), and monitors common-mode interference in real time through a common-mode noise detection circuit in parallel connection with the double paths; and synchronously filters out common-mode noise based on a dynamic threshold filtering algorithm, to generate positive signals and negative signals after common-mode suppression.

[0099] It should be noted that the dynamic filtering algorithm adjusts the filtering parameters according to the real-time noise spectrum, to avoid signal distortion caused by fixed filtering. In the measured industrial environment data, the common-mode suppression ratio is above 80 dB.

[0100] Further, the high-speed ADC sampling module is configured to perform high-speed analog-digital conversion of the positive signals and the negative signals after common-mode suppression under synchronous clock control, to generate digitized positive data stream and digitized negative data stream. Specifically, the positive / negative signals after common-mode suppression are subjected to synchronous clock control ADC sampling: a double-channel 12-bit high-speed ADC is adopted, and the positive / negative sampling is strictly synchronized to the same system clock rising edge; valid differential data points are identified: the real-time differential value is calculated:

[0101] The configurable threshold D th The single level is determined, and the majority voting is performed on the multiple sampling results in a single data bit, to determine the final level value.

[0102] It should be noted that the weighting coefficient K p And K dAccording to the channel impedance self-adaptive adjustment; the majority voting mechanism significantly reduces the instantaneous interference misjudgment rate.

[0103] Further, the data extraction game module is used for comparing the time sequence and level state of the digitized positive electrode data stream and the negative electrode data stream, identifying and extracting effective differential data points; comparing the time sequence and level state of the digitized positive electrode data stream and the negative electrode data stream, identifying and extracting effective differential data points, specifically comprising: multiple synchronous sampling is performed in each data bit clock cycle, and positive sampling values and negative sampling values are respectively acquired; a real-time difference value is acquired according to the positive sampling values and the negative sampling values, a single level result is judged by comparing the real-time difference value with a first preset threshold value; and a final level value of a single data bit is determined according to the single level results of multiple samplings of the single data bit.

[0104] In one possible embodiment, the real-time difference value is acquired according to the positive sampling values and the negative sampling values, the single level result is judged by comparing the real-time difference value with a first preset threshold value, and the final level value of the single data bit is determined according to the single level results of multiple samplings of the single data bit, specifically comprising: when the real-time difference value is greater than the first preset threshold value, the single level is judged to be a high level; when the real-time difference value is less than the first preset threshold value, the single level is judged to be a low level; the level results of multiple samplings in a single data bit are processed, when a sum value of the multiple processing results is greater than a majority, the final level value of the single data bit is determined to be a high level; and when the sum value of the multiple processing results is less than or equal to the majority, the final level value of the single data bit is determined to be a low level.

[0105] In specific implementation, multiple synchronous samplings are performed in each data bit clock cycle, for example, 8 samplings are performed in each bit cycle, and positive path sampling values DP ( n ) and negative path sampling values DN ( n ) are simultaneously captured; a real-time difference value is calculated according to a formula:

[0106] D ( n ) is compared with a first preset threshold value D th : If D ( n ) D th , a single sampling is determined to be a high level, and the value is 1.

[0107] If D ( n ) D ​th If the single sample is low, it is assigned a value of 0.

[0108] Sum all the sample results in a single data bit period: Determine the final level according to the accumulated value: When the final level of the data bit is high; When the final level of the data bit is low.

[0109] It should be noted that by sampling each data bit 8 times and using the majority value strategy, the error rate is effectively reduced and the signal recognition accuracy is improved.

[0110] Further, the adaptive clock algorithm unit adjusts the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the effective differential data points to generate an adaptive sampling clock signal, specifically including: triggering a period detection process through the signal transition edge of the effective differential data points; capturing the actual duration sequence of consecutive signal periods within a fixed time window; calculating the ratio of the average duration of consecutive multiple signal periods in the sequence to the reference period; when the ratio continuously satisfies the preset tolerance condition, locking the current clock frequency and updating the reference period of the system bit stream clock; when the ratio exceeds the preset tolerance range, triggering the next round of synchronization cycle based on the current actual period sequence.

[0111] In specific implementation, the rising edge / falling edge of the effective differential data points is used to trigger period detection, and the edge detection sensitivity is configurable; within a fixed time window, for example, 16 clocks by default, consecutive signal periods are captured within the period, and the high / low level duration sequence is recorded in real time: the average duration of consecutive M periods is calculated and compared with the reference period: the reference period takes the first complete period value. When the ratio continuously satisfies the preset tolerance condition, the current clock frequency is locked and the reference period of the system bit stream clock is updated; when the ratio exceeds the preset tolerance range, the next round of synchronization cycle is triggered based on the current actual period sequence.

[0112] It should be noted that the window expansion mechanism can improve the capture success rate in a noisy environment, and the continuous tolerance determination avoids false locking caused by instantaneous interference.

[0113] In one possible embodiment, the actual duration sequence of the continuous signal period is composed of alternating high level duration and low level duration; the ratio calculation is only performed when all high level periods and low level periods form a complete period combination; the step of locking the current clock frequency includes: synchronously adjusting the clock phase compensation amount and the frequency division coefficient according to the ratio result; the step of triggering the next round of synchronization cycle includes: resetting the period capture counter and dynamically extending the capture duration of the fixed time window.

[0114] In implementation, the period detection window is triggered by detecting signal edge transition, and the high and low level period length is captured within the fixed time window. Based on 16 period window analysis, if the ratio of the subsequent period to the first period is within the preset threshold range, the current clock frequency is confirmed, and the reference clock is updated; otherwise, the next period comparison is continued until the correct frequency is locked. This mechanism ensures that the repeater can dynamically adapt to the clock frequency change of the host or slave, avoiding data misalignment caused by clock drift.

[0115] Further, a data isometric reproduction module is configured to perform timing alignment and scaling processing on the effective differential data points according to the adaptive sampling clock signal, and reconstruct an isometric bit rate data output stream.

[0116] In this embodiment, the data isometric reproduction module can perform timing alignment and scaling processing on the effective differential data points according to the adaptive sampling clock signal, and reconstruct an isometric bit rate data output stream, including: assembling the effective differential data points into a standardized data frame structure; the standardized data frame structure includes: a start bit represented by a low level for a plurality of continuous clock periods; a data bit arranged in the order of high bit first for a plurality of continuous clock periods; a stop bit represented by a high level for a plurality of continuous clock periods; wherein the clock period ratio of the start bit, the data bit and the stop bit is a fixed value, and the sum of the period numbers of the start bit and the stop bit is greater than the period number of the data bit.

[0117] In implementation, after detecting the effective data, the data frame is automatically assembled in the format of “4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)”. The sending process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window.

[0118] In one possible embodiment, the standardized data frame is protocol-analyzed to identify the start bit, the data bit and the stop bit; a timeout detection is synchronously started, and when the stop bit is not completely received within the plurality of continuous clock periods starting from the start bit, it is determined that the communication is timed out and the receiving state is reset; the length of the timeout detection is proportional to the total period number of the standardized data frame.

[0119] In a specific implementation, the received signal is protocol-analyzed to identify start bits, data bits, and stop bits. A 16-clock-cycle timeout detection mechanism is also set up. If the data reception is not completed within the specified time, the communication is determined to have failed and the reception state is reset. This mechanism ensures the integrity and consistency of data reception.

[0120] In one possible embodiment, in the process of converting the reconstructed data output stream into a differential drive signal and outputting: the bus enable signal is kept in an active state during the entire transmission period of a data frame; the entire transmission period covers the period from the start bit to the end of the stop bit; and the bus is prohibited from entering a high-impedance state when the bus enable signal is in the active state.

[0121] In a specific implementation, after detecting valid data, a data frame is automatically assembled in the format of "4-bit start bit (low level) + 8-bit data bit (high bit first) + 2-bit stop bit (high level)". The transmission process strictly follows the rising edge trigger of the system clock to ensure the center alignment of the data window. At the same time, the transmission enable is kept at a high level during the entire data period to prevent the bus from entering a high-impedance state. After each group of data transmission is completed, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus remains in a high-impedance state, the current communication is terminated.

[0122] Further, the bus driving module is configured to convert the reconstructed data output stream into a differential drive signal and output.

[0123] In this embodiment, after completing the transmission of a group of standardized data frames: a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely transmitted; no low-level signal corresponding to a new start bit has been detected within a plurality of continuous clock cycles; the bus state remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames.

[0124] In a specific implementation, after completing the transmission of a group of standardized data frames: a silence period determination process is started, and the bus state is continuously monitored; when the following conditions are met simultaneously, the bus control right is released: the stop bit of the current data frame has been completely transmitted; no low-level signal corresponding to a new start bit has been detected within a plurality of continuous clock cycles; the bus state remains at a preset idle level; and the number of the plurality of continuous clock cycles is proportional to the total number of periods of the standardized data frames. After each group of data transmission is completed, a 16-bit period of silence detection mechanism is started. If there is no new start signal and the bus remains in a high-impedance state, the current communication is terminated.

[0125] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary, and are not to be interpreted as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A relay method for signal enhancement by proportionally reproducing differential transmission waveforms, characterized in that the steps include... include: S1: Separate the differential signal into the positive and negative paths, and simultaneously perform real-time detection and dynamic filtering of common-mode noise on the positive and negative paths to generate common-mode suppressed positive and negative signals; S2: Perform high-speed analog-to-digital conversion on the positive and negative signals after common-mode suppression under synchronous clock control to generate digital positive and digital negative data streams; Compare the timing and level states of the digitized positive electrode data stream and the negative electrode data stream to identify and extract valid differential data points; S3: Based on the timing distribution characteristics of the effective differential data points, adjust the phase and frequency of the system bit stream clock to generate an adaptive sampling clock signal; Based on the adaptive sampling clock signal, the effective differential data points are time-aligned and scaled to reconstruct a data output stream with equal bit rate; The reconstructed data output stream is converted into a differential drive signal and then output.

2. The method according to claim 1, characterized in that, The step of comparing the timing and level states of the digitized positive data stream and the negative data stream to identify and extract valid differential data points specifically includes: Multiple synchronous samples are performed within each data bit clock cycle to obtain the positive and negative sample values ​​respectively. The real-time difference between the positive and negative sample values ​​is obtained, and the single-level result is determined by comparing the real-time difference with a first preset threshold. The final level value of a single data bit is determined based on the single level result obtained from multiple samplings of a single data bit.

3. The method according to claim 2, characterized in that, The real-time difference is obtained based on the positive and negative sample values, and the single-level result is determined by comparing the real-time difference with a first preset threshold. The final level value of a single data bit is determined based on the single level result obtained from multiple samplings of a single data bit, specifically including: When the real-time difference is greater than the first preset threshold, the single level is determined to be a high level. When the real-time difference is less than a first preset threshold, the single level is determined to be a low level. The level results of multiple samples within a single data bit are processed. When the sum of the multiple processing results is greater than a majority, the final level value of the single data bit is determined to be high. When the sum of the results of the multiple processing steps is less than or equal to a majority, the final level value of a single data bit is determined to be low.

4. The method according to claim 1, characterized in that, The step of adjusting the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the effective differential data points to generate an adaptive sampling clock signal specifically includes: The signal transition edge triggering period detection process is achieved through the effective differential data points; Capture the actual duration sequence of continuous signal periods within a fixed time window; Calculate the ratio of the average duration of multiple consecutive signal periods in the sequence to the reference period; When the ratio continuously meets the preset tolerance condition, the current clock frequency is locked and the reference period of the system bit stream clock is updated; When the ratio exceeds the preset tolerance range, the next round of synchronization cycle is triggered based on the current actual cycle sequence.

5. The method according to claim 4, characterized in that, The actual duration sequence of the continuous signal period consists of alternating high-level durations and low-level durations; The ratio calculation is performed only when all high-level periods and low-level periods form a complete cycle combination; The step of locking the current clock frequency includes: synchronously adjusting the clock phase compensation amount and the frequency division coefficient according to the ratio result; The steps for triggering the next round of synchronization loop include: resetting the periodic capture counter and dynamically extending the capture duration of the fixed time window.

6. The method according to claim 1, characterized in that, The step of performing timing alignment and scaling processing on the effective differential data points according to the adaptive sampling clock signal to reconstruct a data output stream with equal bit rate includes: The effective differential data points are assembled into a standardized data frame structure; The standardized data frame structure includes: The start bit for multiple consecutive clock cycles is indicated by a low level; Data bits for multiple consecutive clock cycles are arranged in the order of most significant bit first; A stop bit for multiple consecutive clock cycles is indicated by a high level; The ratio of clock cycles for the start bit, data bit, and stop bit is a fixed value, and the sum of the clock cycles for the start bit and stop bit is greater than the clock cycles for the data bit.

7. The method according to claim 6, characterized in that, The standardized data frame is parsed according to the protocol to identify the start bit, data bits and stop bit; Synchronous start timeout detection: if the stop bit is not completely received within multiple consecutive clock cycles starting from the start bit, a communication timeout is determined and the receiving state is reset. The duration of the timeout detection is proportional to the total number of cycles of the standardized data frame.

8. The method according to claim 6, characterized in that, In the process of converting the reconstructed data output stream into a differential drive signal and outputting it: The bus enable signal remains active throughout the entire transmission cycle of the data frame. The complete transmission cycle covers the period from the start bit to the stop bit; When the bus enable signal is active, the bus is prevented from entering the high impedance state.

9. The method according to any one of claims 1 to 8, characterized in that, After completing the transmission of a set of standardized data frames: Initiate the silent period determination process and continuously monitor the bus status; Bus control is released when all of the following conditions are met: The stop bits of the current data frame have been completely transmitted; No low-level signal corresponding to the new start bit was detected in multiple consecutive clock cycles; The bus state remains at the preset idle level; The number of consecutive clock cycles is proportional to the total number of cycles of the standardized data frame.

10. A relay device for signal enhancement by proportional reproduction of differential transmission waveforms, employing the relay method for signal enhancement by proportional reproduction of differential transmission waveforms as described in any one of claims 1-9, wherein the relay device is characterized in that... : An adaptive common-mode filtering module is used to simultaneously perform real-time detection and dynamic filtering of common-mode noise on the positive and negative electrode paths, generating positive and negative electrode signals after common-mode suppression. A high-speed ADC sampling module is used to perform high-speed analog-to-digital conversion on the positive and negative signals after common-mode rejection under synchronous clock control, generating digital positive data stream and digital negative data stream; The data extraction and game theory module is used to compare the timing and level states of the digitized positive electrode data stream and the negative electrode data stream, and to identify and extract effective differential data points. An adaptive clock algorithm unit is used to adjust the phase and frequency of the system bit stream clock based on the timing distribution characteristics of the effective differential data points, and generate an adaptive sampling clock signal. The data proportional reproduction module is used to perform timing alignment and scaling processing on the effective differential data points according to the adaptive sampling clock signal, and reconstruct a data output stream with equal bit rate; The bus driver module is used to convert the reconstructed data output stream into differential drive signals and output them.

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