A semiconductor device

Abstract

This invention discloses a semiconductor device. It includes a semiconductor body, comprising a first surface, a second surface, a well region, a first region, and a first groove. The first groove includes a first sub-groove and a second sub-groove that are connected. In a direction perpendicular to the first surface pointing towards the second surface, the size of the second sub-groove is larger than the size of the first sub-groove. Along the direction from the first surface to the second surface, the perpendicular distance between the first sub-groove and the second surface is smaller than the perpendicular distance between the well region and the second surface. The device also includes a first insulating layer; a shielding gate; a first strain-insulating layer; a second insulating layer; a control gate; a second groove disposed in the first region, the depth of which is less than the thickness of the first region; a second strain-insulating layer; the first strain-insulating layer and the second strain-insulating layer are used to apply stress to both ends of the channel region; a source electrode; and a drain electrode. The technical solution of this invention can improve channel carrier mobility and reduce channel resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] Power metal-oxide-semiconductor field-effect transistors (MOSFETs) offer advantages such as fast switching speed, high input impedance, and ease of driving, making them widely used power devices. Shielded-gate power MOSFETs are an advanced type of power MOSFET that has emerged in recent years, with their core advantages lying in high-frequency and high-efficiency applications. By integrating a shielded gate below the control gate to form a shielded-gate power MOSFET, this structure significantly reduces gate-drain capacitance, effectively suppressing voltage oscillations caused by the Miller effect, thereby reducing switching losses. Simultaneously, optimized charge balance design enables the device to achieve lower on-resistance within the same chip area, breaking through the traditional silicon limit and increasing power density. Therefore, shielded-gate MOSFETs are widely used in server power supplies, photovoltaic inverters, and on-board chargers for new energy vehicles, contributing to system efficiency and enabling miniaturized designs.

[0003] Shielded-gate power MOSFETs typically have low breakdown voltages and low epitaxial resistivity, resulting in a relatively high proportion of channel resistance in the total on-resistance. To further optimize the trade-off between breakdown voltage and on-resistance, it is necessary to reduce the channel resistance. Channel mobility is a key parameter determining channel resistance; improving channel carrier mobility can effectively reduce channel resistance, thereby reducing the overall device resistance and achieving lower power consumption. Therefore, improving the channel carrier mobility of shielded-gate power MOSFETs has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a semiconductor device to improve channel carrier mobility and reduce channel resistance.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising:

[0006] The semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the semiconductor body also includes a first groove; the first groove extends from the first surface into the semiconductor body and is located on the same side of the well region and the first region; the first groove includes a first sub-groove and a second sub-groove; the first sub-groove and the second sub-groove are connected, the second sub-groove is located on the side of the first sub-groove away from the first surface, and in a direction perpendicular to the first surface pointing to the second surface, the size of the second sub-groove is larger than the size of the first sub-groove; along the direction from the first surface to the second surface, the vertical distance between the first sub-groove and the second surface is smaller than the vertical distance between the well region and the second surface;

[0007] The first insulating layer is located on the bottom surface and sidewalls of the second sub-groove;

[0008] The shielding gate is located on the side of the first insulating layer away from the second sub-groove;

[0009] A first strain insulating layer is located within a second sub-groove. The vertical projection of the first strain insulating layer on the second surface covers the vertical projection of the shielding gate on the second surface and the vertical projection of the first insulating layer on the second surface.

[0010] The second insulating layer is located on the sidewall of the first sub-groove;

[0011] The control gate is located within the first sub-recess and on the side of the second insulating layer away from the well region;

[0012] The first region is provided with a second groove in the direction from the first surface to the second surface. The depth of the second groove is less than the thickness of the first region. The second groove is located on the side of the first region close to the second insulating layer.

[0013] The second strain insulating layer is located in the second groove; the first strain insulating layer and the second strain insulating layer are used to apply stress to both ends of the channel region to improve the carrier mobility in the channel region, and the channel region is located on the side of the well region close to the second insulating layer.

[0014] The source electrode is located on the first surface;

[0015] The drain electrode is located on the second surface.

[0016] Optionally, the second sub-groove is provided with a concave structure near the apex of the first sub-groove, and the edge of the concave structure is recessed into the second sub-groove.

[0017] Optionally, in the direction perpendicular to the first surface and pointing to the second surface, the size of the concave structure is equal to the difference between the size of the second sub-groove and the size of the first sub-groove.

[0018] Optionally, the second insulating layer is provided with a third groove, the third groove is connected to the second groove, the depth of the third groove is equal to the depth of the second groove, and the second strain insulating layer is also located in the third groove and in contact with the control gate.

[0019] Optionally, the materials of the first strain insulation layer and the second strain insulation layer are the same; or, the materials of the first strain insulation layer and the second strain insulation layer are different.

[0020] Optionally, the material of the first strain insulation layer includes silicon nitride or aluminum oxide; and / or, the material of the second strain insulation layer includes silicon nitride or aluminum oxide.

[0021] Optionally, the first conductivity type is N-type, and the first strain insulation layer and the second strain insulation layer generate tensile stress in the channel region.

[0022] Optionally, the first conductivity type is P-type, and the first strain insulation layer and the second strain insulation layer generate compressive stress on the channel region.

[0023] Optionally, the semiconductor device further includes: a third insulating layer; the third insulating layer is located within the second sub-groove, between the first strain insulating layer and the shielding gate, and between the first strain insulating layer and the first insulating layer.

[0024] Optionally, the semiconductor body further includes a second region configured with a second conductivity type and located on the first surface; the second region is in contact with the first region.

[0025] The technical solution of this invention involves setting a first strain-insulating layer and a second strain-insulating layer at both ends of the channel region. By adjusting the growth process conditions of the first and second strain-insulating layers, expansion stress or contraction stress can be applied inside the first and second strain-insulating layers. This applies expansion or contraction stress to both ends of the channel region, altering the crystal lattice structure, reducing carrier scattering, and significantly improving carrier mobility within the channel region. With increased carrier mobility in the channel region, the resistance of the semiconductor device decreases during conduction, and the conduction current increases at the same voltage, thereby reducing conduction losses. The first strain-insulating layer can also isolate the control gate and the shielding gate. Furthermore, in the direction perpendicular to the first surface pointing to the second surface, the size of the second sub-groove is larger than the size of the first sub-groove. In the direction perpendicular to the first surface pointing to the second surface, the vertical distance between the first sub-groove and the second surface is smaller than the vertical distance between the well region and the second surface. This allows the first strain insulating layer to have better contact with the silicon below the channel region, and the second strain insulating layer to have better contact with the silicon above the channel region. This ensures that the stress generated by the first strain insulating layer and the second strain insulating layer is transmitted to the channel region, improving the carrier mobility in the channel region and thus improving the performance of the semiconductor device.

[0026] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic cross-sectional view of another semiconductor device provided according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure by which the first strain insulation layer and the second strain insulation layer generate tensile stress in the channel region according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure by which the first strain insulation layer and the second strain insulation layer generate compressive stress in the channel region according to an embodiment of the present invention.

[0032] Figure 5 This is a cross-sectional structural schematic diagram of another semiconductor device provided according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0034] Figures 7-14 According to the embodiments of the present invention Figure 6 Schematic diagrams of the cross-sectional structures corresponding to each step in the process. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 1As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104, the first region 104 being configured with a first conductivity type and located on the first surface 101, and the well region 103 being configured with a second conductivity type and located on the side of the first region 104 away from the first surface 101; the semiconductor body 100 also includes a first groove; the first groove extends from the first surface 101 into the semiconductor body 100 and is located on the same side of the well region 103 and the first region 104; the first groove includes a first sub-groove. 105 and second sub-groove 106; the first sub-groove 105 and the second sub-groove 106 are connected, the second sub-groove 106 is located on the side of the first sub-groove 105 away from the first surface 101, and in the direction X perpendicular to the first surface 101 pointing to the second surface 102, the size of the second sub-groove 106 is larger than the size of the first sub-groove 105; along the direction Y pointing from the first surface 101 to the second surface 102, the perpendicular distance L1 between the first sub-groove 105 and the second surface 102 is smaller than the perpendicular distance L2 between the well region 103 and the second surface 102; the first insulating layer 200 is located on the bottom surface of the second sub-groove 106. The first insulating layer 200 is located on the sidewall of the first sub-recess 105, and the second insulating layer 107 is located in the second sub-recess 106. The first strain insulating layer 300 is located within the second sub-recess 106, and its vertical projection on the second surface 102 covers both the vertical projection of the shielding gate 30 and the first insulating layer 200 on the second surface 102. The second insulating layer 400 is located on the sidewall of the first sub-recess 105. The control gate 40 is located within the first sub-recess 105 and on the side of the second insulating layer 400 away from the well region 103. The first region 104 is provided with the second recess 107. Along the direction Y from the first surface 101 to the second surface 102, the depth of the second groove 107 is less than the thickness of the first region 104, and the second groove 107 is located on the side of the first region 104 near the second insulating layer 400; the second strain insulating layer 500 is located in the second groove 107; the first strain insulating layer 300 and the second strain insulating layer 500 are used to apply stress to both ends of the channel region 50 to improve the carrier mobility in the channel region 50, and the channel region 50 is located on the side of the well region 103 near the second insulating layer 400; the source 60 is located on the first surface 101; and the drain 70 is located on the second surface 102.

[0038] In this embodiment of the invention, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type dopant ions in the P-well region can be aluminum (Al) ions or boron (B) ions.

[0039] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed by one or more epitaxial processes on the substrate 10, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0040] The shielding gate 30 can be made of polysilicon. The control gate 40 can also be made of polysilicon. A first insulating layer 200 is used to insulate the semiconductor body 100 and the shielding gate 30. The first insulating layer 200 can be an oxide layer. The shielding gate 30 is typically connected to a fixed potential (e.g., ground) to shield the control gate 40 from the influence of high drain voltage. The control gate 40 is used to control the conduction and turn-off of the channel. A second insulating layer 400 is used to insulate the semiconductor body 100 and the control gate 40. The second insulating layer 400 can be an oxide layer. Metal is deposited on the first surface 101 to form the source 60. Metal is deposited on the second surface 102 to form the drain 70. The deposited metal can be titanium (Ti), nickel (Ni), or silver (Ag).

[0041] In the direction X perpendicular to the first surface 101 and pointing to the second surface 102, the size of the second sub-groove 106 is larger than the size of the first sub-groove 105. Compared to the prior art where the size of the second sub-groove 106 is smaller than or equal to the size of the first sub-groove 105, the technical solution of this embodiment of the invention ensures that the stress generated by the first strain insulating layer 300 is transmitted to the channel region 50 by setting a wider second sub-groove 106, thereby improving the carrier mobility in the channel region 50. In the direction Y perpendicular to the first surface 101 and pointing to the second surface 102, the vertical distance L1 between the first sub-groove 105 and the second surface 102 is smaller than the vertical distance L2 between the well region 103 and the second surface 102. This ensures that the stress generated by the first strain insulating layer 300 is transmitted to the channel region 50 and makes the shielding gate 30 closer to the drain 70, which can effectively disperse the electric field generated by the high voltage of the drain 70, avoid electric field concentration in the channel region 50, and improve the withstand voltage capability of the semiconductor device.

[0042] The first strain insulating layer 300 and the second strain insulating layer 500 apply stress to both ends of the channel region 50, which can change the crystal lattice structure, reduce carrier (electron or hole) scattering, and significantly improve carrier mobility. With the increased carrier mobility in the channel region 50, the resistance of the semiconductor device decreases during conduction, and the conduction current under the same voltage increases, thereby reducing conduction losses. Specifically, the first strain insulating layer 300 applies stress to the channel region 50 through the epitaxial layer between the first strain insulating layer 300 and the channel region 50. The second strain insulating layer 500 applies stress to the channel region 50 through the first region 104 between the second strain insulating layer 500 and the channel region 50.

[0043] The technical solution of this invention involves setting a first strain-insulating layer and a second strain-insulating layer at both ends of the channel region. By adjusting the growth process conditions of the first and second strain-insulating layers, expansion stress or contraction stress can be applied inside the first and second strain-insulating layers. This applies expansion or contraction stress to both ends of the channel region, altering the crystal lattice structure, reducing carrier scattering, and significantly improving carrier mobility within the channel region. With increased carrier mobility in the channel region, the resistance of the semiconductor device decreases during conduction, and the conduction current increases at the same voltage, thereby reducing conduction losses. The first strain-insulating layer can also isolate the control gate and the shielding gate. Furthermore, in the direction perpendicular to the first surface pointing to the second surface, the size of the second sub-groove is larger than the size of the first sub-groove. In the direction perpendicular to the first surface pointing to the second surface, the vertical distance between the first sub-groove and the second surface is smaller than the vertical distance between the well region and the second surface. This allows the first strain insulating layer to have better contact with the silicon below the channel region, and the second strain insulating layer to have better contact with the silicon above the channel region. This ensures that the stress generated by the first strain insulating layer and the second strain insulating layer is transmitted to the channel region, improving the carrier mobility in the channel region and thus improving the performance of the semiconductor device.

[0044] In an optional embodiment of the present invention, reference is made to... Figure 1 The second sub-groove 106 is provided with an inwardly recessed structure 109 near the top corner of the first sub-groove 105, and the edge of the inwardly recessed structure 109 is recessed into the second sub-groove 106.

[0045] In this embodiment of the invention, the apex of the second sub-groove 106 near the first sub-groove 105 is configured as a concave structure 109 to avoid local electric field concentration and improve the withstand voltage performance and reliability of the semiconductor device. Furthermore, the concave structure 109 increases the area of ​​silicon that transmits the stress applied to the channel region 50 by the first strain insulating layer 300, ensuring that the stress generated by the first strain insulating layer 300 is transmitted to the channel region 50 and improving the carrier mobility of the channel region 50.

[0046] In an optional embodiment of the present invention, reference is made to... Figure 1 In the direction X perpendicular to the first surface 101 and pointing to the second surface 102, the size of the concave structure 109 is equal to the difference between the size of the second sub-groove 106 and the size of the first sub-groove 105.

[0047] In this embodiment of the invention, in the direction X perpendicular to the first surface 101 pointing to the second surface 102, the size of the concave structure 109 is set to be equal to the difference between the size of the second sub-groove 106 and the size of the first sub-groove 105. This can achieve a smooth transition between the first sub-groove 105, the concave structure 109, and the second sub-groove 106, forming a continuous and smooth transition structure without abrupt steps. This avoids the superposition of local stress, prevents interference with the carrier movement path in the channel region 50, and improves the performance of the semiconductor device.

[0048] Figure 2 This is a schematic cross-sectional view of another semiconductor device provided according to an embodiment of the present invention. Figure 2 As shown, with Figure 1 The difference in the structure shown is that the second insulating layer 400 is provided with a third groove 110, the third groove 110 is connected to the second groove 107, the depth of the third groove 110 is equal to the depth of the second groove 107, and the second strain insulating layer 500 is also located in the third groove 110 and in contact with the control gate 40.

[0049] In this embodiment of the invention, the second strain-insulating layer 500 is located not only within the second groove 107 but also within the third groove 110, contacting the control gate 40. This enhances stress transfer efficiency, increases the stress exerted by the second strain-insulating layer 500 on the channel region 50, and improves the carrier mobility of the channel region 50. Furthermore, the third groove 110 occupies only the vertical space of the second insulating layer 400, without increasing the device size. This strengthens the strain effect while ensuring miniaturized device design and improving the integration density of the semiconductor device.

[0050] In an optional embodiment of the present invention, reference is made to... Figure 1 The materials of the first strain insulation layer 300 and the second strain insulation layer 500 are the same; or, the materials of the first strain insulation layer 300 and the second strain insulation layer 500 are different.

[0051] In this embodiment of the invention, the materials of the first strain insulating layer 300 and the second strain insulating layer 500 are the same, which simplifies the fabrication process, reduces process complexity, improves mass production consistency, ensures the coordinated matching of stress direction and magnitude, optimizes interface compatibility, and improves the long-term reliability of semiconductor devices. Alternatively, the materials of the first strain insulating layer 300 and the second strain insulating layer 500 can be different to meet the local environmental requirements at different locations and improve the performance of semiconductor devices.

[0052] In an optional embodiment of the present invention, reference is made to... Figure 1 The material of the first strain insulating layer 300 includes silicon nitride or aluminum oxide; and / or, the material of the second strain insulating layer 500 includes silicon nitride or aluminum oxide.

[0053] In this embodiment of the invention, both the first strain insulating layer 300 and the second strain insulating layer 500 are made of insulating materials with high stress, which can apply stress to both ends of the channel region 50 and improve the carrier mobility within the channel region 50. The material of the first strain insulating layer 300 includes, but is not limited to, silicon nitride (Si3N4) or aluminum oxide (Al2O3). The material of the second strain insulating layer 500 includes, but is not limited to, silicon nitride or aluminum oxide.

[0054] Figure 3 This is a schematic diagram of the structure by which the first strain insulation layer and the second strain insulation layer generate tensile stress in the channel region according to an embodiment of the present invention, as shown below. Figure 1 and Figure 3 As shown, the first conductivity type is N-type, and the first strain insulation layer 300 and the second strain insulation layer 500 generate tensile stress on the channel region 50.

[0055] In this embodiment of the invention, for an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. The first region 104 is an N+ doped region, the well region 103 is a P-well region, and the second region 108 can be a P+ doped region. When the semiconductor device is an N-channel MOSFET, the first strain insulating layer 300 and the second strain insulating layer 500 have inward contraction stress, which in turn generates tensile stress at both ends of the channel region 50, thereby increasing the electron mobility within the channel region 50.

[0056] Figure 4This is a schematic diagram of the structure by which the first strain insulating layer and the second strain insulating layer generate compressive stress in the channel region according to an embodiment of the present invention, as shown below. Figure 1 and Figure 4 As shown, the first conductivity type is P-type, and the first strain insulating layer 300 and the second strain insulating layer 500 generate compressive stress on the channel region 50.

[0057] In this embodiment of the invention, for a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. The first region 104 is a P+ doped region, the well region 103 is an N-well region, and the second region 108 can be an N+ doped region. When the semiconductor device is a P-channel MOSFET, the first strain insulating layer 300 and the second strain insulating layer 500 have outward expanding stress, which in turn generates compressive stress at both ends of the channel region 50, increasing the hole mobility within the channel region 50.

[0058] Figure 5 This is a cross-sectional structural schematic diagram of another semiconductor device provided according to an embodiment of the present invention, such as... Figure 5 As shown, the semiconductor device further includes a third insulating layer 600; the third insulating layer 600 is located within the second sub-groove 106, between the first strain insulating layer 300 and the shielding gate 30, and between the first strain insulating layer 300 and the first insulating layer 200.

[0059] In this embodiment of the invention, the third insulating layer 600 can be an oxide layer. The third insulating layer 600 protects the shielding gate 30 and the first insulating layer 200, preventing material interdiffusion and interface reactions. Direct contact between the first strain insulating layer 300 and the shielding gate 30 and the first insulating layer 200 may lead to parasitic capacitance between them due to differences in dielectric properties, affecting the gate signal response speed. The third insulating layer 600 enhances electrical isolation performance and prevents leakage current and parasitic capacitance.

[0060] In an optional embodiment of the present invention, reference is made to... Figure 1 The semiconductor body 100 also includes a second region 108, which is configured as a second conductivity type and located on the first surface; the second region is in contact with the first region.

[0061] In this embodiment of the invention, the conductivity type of the second region 108 is the same as that of the well region 103, both being set to the second conductivity type. For an N-type MOSFET, the second region 108 can be a P+ doped region, with a higher ion concentration than that of the well region 103. By setting the second region 108, a good ohmic contact can be formed with the source 60.

[0062] In an optional embodiment of the present invention, reference is made to... Figure 1The semiconductor device also includes a passivation layer 80 located on the first surface 101, covering the control gate 40, the second insulating layer 400, and the second strain insulating layer 500. The passivation layer 80 serves to isolate moisture, oxygen, or dust from the external environment, preventing these substances from penetrating the semiconductor device and causing corrosion, short circuits, or performance degradation. The material of the passivation layer 80 includes, but is not limited to, silicon oxide, silicon nitride, or polyimide.

[0063] Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 6 As shown, the method for fabricating this semiconductor device includes:

[0064] S110. A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other.

[0065] refer to Figure 7 A semiconductor body 100 is provided, comprising a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed by one or more epitaxial processes on the substrate 10, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The ion concentration of the epitaxial layer 20 is determined by the breakdown voltage of the semiconductor device.

[0066] S111, A first sub-groove is formed on the first surface.

[0067] refer to Figure 8 A first sub-groove 105 is formed on the first surface 101 through photolithography and etching processes. The depth of the first sub-groove 105 is determined by the length of the control gate.

[0068] S112, A first mask layer is formed on the sidewall of the first sub-groove.

[0069] refer to Figure 9 A hard mask layer is deposited on the bottom surface and sidewalls of the first sub-groove 105, and the hard mask layer on the bottom surface of the first sub-groove 105 is etched away by photolithography and etching processes, leaving only the first mask layer 112 on the sidewalls of the first sub-groove 105.

[0070] S113. A second sub-groove is formed on the side of the first sub-groove away from the first surface.

[0071] refer to Figure 10With the first mask layer 112 as protection, reactive ion etching is used to etch out the second sub-groove 106 of the shielding gate portion. The width of the second sub-groove 106 is greater than the width of the first sub-groove 105. The first sub-groove 105 and the second sub-groove 106 are connected.

[0072] S114. A first insulating layer is formed on the bottom surface and sidewalls of the second sub-groove.

[0073] refer to Figure 11 On the bottom surface and sidewalls of the second sub-groove 106, a first insulating layer 200 is grown by thermal growth or chemical vapor deposition.

[0074] S115, a shielding gate is formed on the side of the first insulating layer away from the second sub-groove.

[0075] refer to Figure 12 Polysilicon is filled on the side of the first insulating layer 200 away from the second sub-groove 106, and polysilicon etch-back is performed to form the shielding gate 30.

[0076] S116, A first strain insulation layer is formed in the second sub-groove.

[0077] refer to Figure 13 A first strain insulating layer 300 is formed within the second sub-groove 106. The growth conditions of the first strain insulating layer 300 are controlled to generate contractile or expansion stress within it. The first mask layer 112 is removed to expose the silicon layer.

[0078] S117. A second insulating layer is formed on the sidewall of the first sub-groove, and a control gate is formed in the first sub-groove.

[0079] refer to Figure 14 A second insulating layer 400 is thermally grown on the sidewall of the first sub-recess 105. Polysilicon is filled into the first sub-recess 105, and polysilicon etch-back is performed to form the control gate 40.

[0080] S118. A first region and a second region are formed on the first surface, and a trap region is formed on the side of the first region away from the first surface.

[0081] refer to Figure 1 A first region 104 and a second region 108 are formed on the first surface 101 by ion implantation, and a trap region 103 is formed on the side of the first region 104 away from the first surface 101 by ion implantation.

[0082] It should be noted that the first region 104, the second region 108 and the well region 103 can be formed in this step or when the semiconductor body 100 is provided, and no specific limitation is made here.

[0083] S119, A second groove is formed in the first region.

[0084] refer to Figure 1 A second groove 107 is formed in the first region 104 by photolithography and etching. Along the direction Y from the first surface 101 to the second surface 102, the depth of the second groove 107 is less than the thickness of the first region 104, and the second groove 107 is located on the side of the first region 104 near the second insulating layer 400.

[0085] refer to Figure 2 Furthermore, a third groove 110 can be formed in the second insulating layer 400 by photolithography and etching processes. The third groove 110 is connected to the second groove 107, and the depth of the third groove 110 is equal to the depth of the second groove 107.

[0086] S120, A second strain insulation layer is formed in the second groove.

[0087] refer to Figure 1 A second strain insulation layer 500 is formed within the second groove 107. The growth conditions of the second strain insulation layer 500 are controlled to generate contractile or expansion stress within it.

[0088] refer to Figure 2 Furthermore, a second strain insulating layer 500 can be formed in the third groove 110, which contacts the control gate 40.

[0089] Then, a source electrode 60 is formed by depositing metal on the first surface 101, and a drain electrode 70 is formed by depositing metal on the second surface 102. This results in a structure as follows: Figure 1 or Figure 2 The semiconductor device shown.

[0090] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region, the first region being configured with a first conductivity type and located on the first surface, and the well region being configured with a second conductivity type and located on the side of the first region away from the first surface; the semiconductor body further includes a first groove; the first groove extends from the first surface into the semiconductor body and is located on the same side of the well region and the first region; the first groove includes a first sub-groove and a second sub-groove; the first sub-groove and the second sub-groove are connected, the second sub-groove is located on the side of the first sub-groove away from the first surface, and in a direction perpendicular to the first surface pointing to the second surface, the size of the second sub-groove is larger than the size of the first sub-groove; along the direction from the first surface to the second surface, the vertical distance between the first sub-groove and the second surface is smaller than the vertical distance between the well region and the second surface; The first insulating layer is located on the bottom surface and sidewalls of the second sub-groove; The shielding gate is located on the side of the first insulating layer away from the second sub-groove; A first strain insulating layer is located within the second sub-groove, and the vertical projection of the first strain insulating layer on the second surface covers the vertical projection of the shielding gate on the second surface and the vertical projection of the first insulating layer on the second surface. The second insulating layer is located on the sidewall of the first sub-groove; The control gate is located within the first sub-recess and on the side of the second insulating layer away from the well region; The first region is provided with a second groove in the direction from the first surface to the second surface. The depth of the second groove is less than the thickness of the first region. The second groove is located on the side of the first region close to the second insulating layer. The second strain insulating layer is located within the second groove; the first strain insulating layer and the second strain insulating layer are used to apply stress to both ends of the channel region to improve the carrier mobility in the channel region, and the channel region is located on the side of the well region close to the second insulating layer; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The second sub-groove has a concave structure near the apex of the first sub-groove, and the edge of the concave structure is recessed into the second sub-groove.

3. The semiconductor device according to claim 2, characterized in that, In the direction perpendicular to the first surface and pointing towards the second surface, the size of the concave structure is equal to the difference between the size of the second sub-groove and the size of the first sub-groove.

4. The semiconductor device according to claim 1, characterized in that, The second insulating layer is provided with a third groove, which is connected to the second groove. The depth of the third groove is equal to the depth of the second groove. The second strain insulating layer is also located in the third groove and contacts the control gate.

5. The semiconductor device according to claim 1, characterized in that, The material of the first strain insulation layer is the same as the material of the second strain insulation layer; or, the material of the first strain insulation layer is different from the material of the second strain insulation layer.

6. The semiconductor device according to claim 5, characterized in that, The material of the first strain insulation layer includes silicon nitride or aluminum oxide; and / or, the material of the second strain insulation layer includes silicon nitride or aluminum oxide.

7. The semiconductor device according to claim 1, characterized in that, The first conductivity type is N-type, and the first strain insulation layer and the second strain insulation layer generate tensile stress on the channel region.

8. The semiconductor device according to claim 1, characterized in that, The first conductivity type is P-type, and the first strain insulating layer and the second strain insulating layer generate compressive stress on the channel region.

9. The semiconductor device according to claim 1, characterized in that, Also includes: The third insulating layer is located within the second sub-groove, between the first strain insulating layer and the shielding gate, and between the first strain insulating layer and the first insulating layer.

10. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a second region, which is configured with a second conductivity type and is located on the first surface; the second region is in contact with the first region.

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