A topcon solar cell and a preparation method thereof

Abstract

The application discloses a kind of TOPCon solar cell and preparation method thereof, belong to solar cell field, form the laminated structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer on the back of silicon wafer, form first phosphorus-doped polysilicon layer and second phosphorus-doped polysilicon layer after phosphorus diffusion, wherein the phosphorus doping concentration of the first phosphorus-doped polysilicon layer is lower than the phosphorus doping concentration of the second phosphorus-doped polysilicon layer.The application controls the distribution of phosphorus atoms in the doped polysilicon layer, so that the phosphorus doping concentration near the silicon substrate in the area contacted by the metal electrode is low, and the passivation performance between the tunneling oxide layer and the silicon substrate is improved.The phosphorus doping concentration near the metal electrode is high, which improves the contact performance, thereby reducing the entry of phosphorus atoms into the silicon matrix and increasing the temperature window of phosphorus diffusion.

Description

Technical Field

[0001] This invention relates to the field of solar cells, and more specifically, to a TOPCon solar cell and its fabrication method. Background Technology

[0002] TOPCon solar cells are high-efficiency cells based on carrier selective collection passivated contact structures, characterized by the fabrication of a tunneling silicon oxide (SiO2) layer on the back of the cell. x The passivation contact structure, composed of a polysilicon oxide layer and a heavily doped silicon thin film (poly-Si), provides excellent surface and field passivation for the back side of the silicon wafer. The ultrathin silicon oxide layer allows electrons to tunnel into the polysilicon layer while blocking hole transport, reducing recombination current. The lateral transport characteristics of the doped polysilicon layer reduce series resistance. These two characteristics together improve the open-circuit voltage, fill factor, and conversion efficiency of the battery, making it the most likely next-generation high-efficiency battery technology to achieve mass production.

[0003] In the production of TOPCon solar cells, an ultrathin tunneling oxide layer and a heavily doped silicon thin film are deposited on the back of a silicon wafer using the LPCVD method, followed by phosphorus doping in a tube diffusion furnace. Currently, to further improve the electrical performance of TOPCon solar cells, production lines increase the phosphorus doping concentration in the heavily doped silicon thin film to enhance the passivation effect between the poly-Si layer and the silicon wafer and improve the contact between the poly-Si layer and the metal electrode. However, as the phosphorus doping concentration in the poly-Si layer increases, phosphorus atoms diffuse into the silicon substrate, weakening the passivation effect at the interface between the oxide layer and the silicon wafer, ultimately affecting the cell efficiency. Summary of the Invention

[0004] To address the shortcomings and deficiencies of existing technologies, this invention provides a TOPCon solar cell and its fabrication method. By forming a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer on the back of a silicon wafer, it improves the problem of phosphorus atoms diffusing into the silicon wafer due to excessive phosphorus doping, weakening the passivation effect at the interface between the oxide layer and the silicon substrate, while simultaneously increasing the surface doping concentration. The technical solution is as follows:

[0005] A method for fabricating a TOPCon solar cell includes the following steps:

[0006] Step 1: Select silicon wafers and perform cleaning and texturing, front-side boron diffusion, and etching and alkaline polishing treatments in sequence;

[0007] Step 2: A tunneling oxide layer, a first amorphous silicon layer, a first PSG layer, a second amorphous silicon layer, and a second PSG layer are sequentially deposited on the back side of the silicon wafer to form a stacked structure.

[0008] Step 3: Perform phosphorus diffusion annealing on the silicon wafer to form a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer;

[0009] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0010] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0011] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0012] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0013] Preferably, in the stacked structure of step two, the thickness of the first amorphous silicon layer is less than the thickness of the second amorphous silicon layer.

[0014] Preferably, the deposition of the stacked structure in step two specifically includes: introducing O2 gas at a flow rate of 30,000-40,000 sccm and depositing the tunneling oxide layer at a temperature of 550-650°C; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the first amorphous silicon layer at a temperature of 500-600°C; then introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the first PSG layer at a temperature of 750-850°C; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the second amorphous silicon layer at a temperature of 500-600°C; and finally introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the second PSG layer at a temperature of 750-850°C.

[0015] Preferably, the thicknesses of the stacked structures are as follows: the thickness of the tunneling oxide layer is 1~2nm, the thickness of the first amorphous silicon layer is 10~50nm, the thickness of the first PSG layer is 1~10nm, the thickness of the second amorphous silicon layer is 50~200nm, and the thickness of the second PSG layer is 30~80nm.

[0016] Preferably, the annealing treatment for phosphorus diffusion in step three specifically includes: placing the silicon wafer in a tube diffusion furnace and annealing it at a temperature of 850~950°C under a nitrogen atmosphere to obtain the phosphorus-doped polycrystalline silicon layer.

[0017] Preferably, the phosphorus-doped polycrystalline silicon layer comprises a first phosphorus-doped polycrystalline silicon layer and a second phosphorus-doped polycrystalline silicon layer, wherein the thickness of the phosphorus-doped polycrystalline silicon layer is 60~250 nm and the sheet resistance is 50~150 Ω / cm. 2 .

[0018] Preferably, the phosphorus doping concentration of the first phosphorus-doped polysilicon layer is lower than that of the second phosphorus-doped polysilicon layer; the doping concentration of the second phosphorus-doped polysilicon layer is (0.1~1.5) E21atom / cm. 3 The doping concentration of the first phosphorus-doped polycrystalline silicon layer is (1~10) E19atom / cm. 3 .

[0019] Preferably, the step seven, in which the metal electrode makes ohmic contact with the back of the silicon wafer, specifically includes: the metal electrode passing through the antireflection layer on the back of the silicon wafer and contacting the phosphorus-doped polycrystalline silicon layer.

[0020] The present invention also provides a TOPCon solar cell, which is prepared by the above-described method.

[0021] The beneficial effects of adopting the technical solution of the present invention are as follows:

[0022] This invention forms a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer on the back side of a silicon wafer. After phosphorus diffusion, the distribution of phosphorus atoms in the doped polycrystalline silicon layer is controlled, resulting in a low phosphorus doping concentration near the silicon substrate in the region where the metal electrode contacts, which, together with the tunneling oxide layer, improves the passivation performance between the metal electrode and the silicon substrate. The high phosphorus doping concentration near the metal electrode improves the contact performance, thereby reducing the entry of phosphorus atoms into the silicon substrate and increasing the temperature window for phosphorus diffusion. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0024] This invention provides a TOPCon solar cell and its fabrication method. By forming a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer on the back of a silicon wafer, and controlling the distribution of phosphorus atoms in the doped polycrystalline silicon layer after phosphorus diffusion, the phosphorus doping concentration is low near the silicon substrate in the region where the metal electrode contacts, which, combined with the tunneling oxide layer, improves the passivation performance between the metal electrode and the silicon substrate; the phosphorus doping concentration is high near the metal electrode, improving contact performance, thereby reducing phosphorus atom ingress into the silicon substrate and increasing the temperature window for phosphorus diffusion. The technical solution is as follows:

[0025] A method for fabricating a TOPCon solar cell includes the following steps:

[0026] Step 1: Select silicon wafers and perform cleaning and texturing, front-side boron diffusion, and etching and alkaline polishing treatments in sequence;

[0027] Step 2: A tunneling oxide layer, a first amorphous silicon layer, a first PSG layer, a second amorphous silicon layer, and a second PSG layer are sequentially deposited on the back side of the silicon wafer to form a stacked structure.

[0028] Step 3: Perform phosphorus diffusion annealing on the silicon wafer to form a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer;

[0029] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0030] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0031] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0032] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0033] In a preferred embodiment, in the stacked structure of step two, the thickness of the first amorphous silicon layer is less than the thickness of the second amorphous silicon layer.

[0034] In a preferred embodiment, step two, depositing the stacked structure, specifically includes: introducing O2 gas at a flow rate of 30,000-40,000 sccm and depositing the tunneling oxide layer at a temperature of 550-650°C; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the first amorphous silicon layer at a temperature of 500-600°C; then introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the first PSG layer at a temperature of 750-850°C; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the second amorphous silicon layer at a temperature of 500-600°C; and finally introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the second PSG layer at a temperature of 750-850°C.

[0035] In a preferred embodiment, the thicknesses of the stacked structure are as follows: the thickness of the tunneling oxide layer is 1~2nm, the thickness of the first amorphous silicon layer is 10~50nm, the thickness of the first PSG layer is 1~10nm, the thickness of the second amorphous silicon layer is 50~200nm, and the thickness of the second PSG layer is 30~80nm.

[0036] As a preferred embodiment, the phosphorus diffusion annealing process in step three specifically includes: placing the silicon wafer in a tube diffusion furnace and annealing it at a temperature of 850~950℃ under a nitrogen atmosphere to obtain the phosphorus-doped polycrystalline silicon layer.

[0037] In a preferred embodiment, the phosphorus-doped polysilicon layer comprises a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer, wherein the thickness of the phosphorus-doped polysilicon layer is 60~250 nm and the sheet resistance is 50~150 Ω / cm. 2 .

[0038] In a preferred embodiment, the phosphorus doping concentration of the first phosphorus-doped polysilicon layer is lower than that of the second phosphorus-doped polysilicon layer; the doping concentration of the second phosphorus-doped polysilicon layer is (0.1~1.5) E21atom / cm. 3 The doping concentration of the first phosphorus-doped polycrystalline silicon layer is (1~10) E19atom / cm. 3 .

[0039] In a preferred embodiment, the step seven, in which the metal electrode makes ohmic contact with the back side of the silicon wafer, specifically includes: the metal electrode passing through the antireflection layer on the back side of the silicon wafer and contacting the phosphorus-doped polycrystalline silicon layer.

[0040] The present invention also provides a TOPCon solar cell, which is prepared by the above-described method.

[0041] The following examples further illustrate the beneficial effects of the TOPCon solar cell and its fabrication method provided by this invention.

[0042] Example 1:

[0043] This embodiment 1 provides a method for preparing a TOPCon solar cell, including the following steps:

[0044] Step 1: Select a thickness of 150μm and a resistivity of 5Ω / cm. 2 The N-type single crystal silicon wafers were then sequentially cleaned, texturized, subjected to front-side boron diffusion, and etched and alkaline polished processes.

[0045] Step 2: O2 gas is introduced onto the back of the silicon wafer at a flow rate of 30,000 sccm, and a 1 nm tunneling oxide layer is deposited at 550°C. Then, SiH4 gas is introduced at a flow rate of 1,500 sccm, and a 10 nm first amorphous silicon layer is deposited at 500°C. Next, POCl3 gas is introduced at a flow rate of 1,000 sccm, and a 1 nm first PSG layer is deposited at 750°C. Then, SiH4 gas is introduced at a flow rate of 1,500 sccm, and a 50 nm second amorphous silicon layer is deposited at 500°C. Finally, POCl3 gas is introduced at a flow rate of 1,000 sccm, and a 30 nm second PSG layer is deposited at 750°C, resulting in a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer.

[0046] Step 3: Perform phosphorus diffusion annealing on the silicon wafer. Place the silicon wafer in a tube diffusion furnace and anneal at 850°C under a nitrogen atmosphere to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 60 nm and a sheet resistance of 50 Ω / cm. 2 The phosphorus-doped polysilicon layer includes a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer, wherein the doping concentration of the first phosphorus-doped polysilicon layer is 1×E19atom / cm. 3 The doping concentration of the second phosphorus-doped polycrystalline silicon layer is 0.1 × E21atom / cm. 3 ;

[0047] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0048] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0049] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0050] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0051] Example 2:

[0052] This embodiment 2 provides a method for preparing a TOPCon solar cell, including the following steps:

[0053] Step 1: Select a thickness of 150μm and a resistivity of 5Ω / cm. 2 The N-type single crystal silicon wafers were then sequentially cleaned, texturized, subjected to front-side boron diffusion, and etched and alkaline polished processes.

[0054] Step 2: O2 gas is introduced onto the back of the silicon wafer at a flow rate of 35000 sccm, and a 1.5 nm tunneling oxide layer is deposited at 600℃. Then, SiH4 gas is introduced at a flow rate of 2000 sccm, and a 30 nm first amorphous silicon layer is deposited at 550℃. Next, POCl3 gas is introduced at a flow rate of 1500 sccm, and a 5 nm first PSG layer is deposited at 800℃. Then, SiH4 gas is introduced at a flow rate of 2000 sccm, and a 120 nm second amorphous silicon layer is deposited at 550℃. Finally, POCl3 gas is introduced at a flow rate of 1500 sccm, and a 50 nm second PSG layer is deposited at 800℃, resulting in a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer.

[0055] Step 3: Perform phosphorus diffusion annealing on the silicon wafer. Place the silicon wafer in a tube diffusion furnace and anneal at 900℃ under a nitrogen atmosphere to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 150nm and a sheet resistance of 100Ω / cm. 2 The phosphorus-doped polysilicon layer includes a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer. The doping concentration of the first phosphorus-doped polysilicon layer is 5 × E19 atom / cm. 3 The doping concentration of the second phosphorus-doped polycrystalline silicon layer is 1×E21atom / cm. 3 ;

[0056] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0057] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0058] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0059] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0060] Example 3:

[0061] This embodiment 3 provides a method for preparing a TOPCon solar cell, including the following steps:

[0062] Step 1: Select a thickness of 150μm and a resistivity of 5Ω / cm. 2 The N-type single crystal silicon wafers were then sequentially cleaned, texturized, subjected to front-side boron diffusion, and etched and alkaline polished processes.

[0063] Step 2: O2 gas is introduced onto the back of the silicon wafer at a flow rate of 40,000 sccm, and a 2 nm tunneling oxide layer is deposited at 650°C. Then, SiH4 gas is introduced at a flow rate of 2,500 sccm, and a 50 nm first amorphous silicon layer is deposited at 600°C. Next, POCl3 gas is introduced at a flow rate of 2,000 sccm, and a 10 nm first PSG layer is deposited at 850°C. Then, SiH4 gas is introduced at a flow rate of 2,500 sccm, and a 200 nm second amorphous silicon layer is deposited at 600°C. Finally, POCl3 gas is introduced at a flow rate of 2,000 sccm, and an 80 nm second PSG layer is deposited at 850°C, resulting in a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer.

[0064] Step 3: The silicon wafer undergoes phosphorus diffusion annealing. The wafer is placed in a tube diffusion furnace and annealed at 950°C under a nitrogen atmosphere to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 250 nm and a sheet resistance of 150 Ω / cm. 2 The phosphorus-doped polysilicon layer includes a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer, wherein the doping concentration of the first phosphorus-doped polysilicon layer is 10 × E19 atom / cm. 3 The doping concentration of the second phosphorus-doped polycrystalline silicon layer is 1.5 × E21atom / cm. 3 ;

[0065] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0066] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0067] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0068] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0069] Comparative Example 1

[0070] Comparative Example 1 provides a method for preparing a TOPCon solar cell, comprising the following steps:

[0071] Step 1: Select a thickness of 150μm and a resistivity of 5Ω / cm. 2 The N-type single crystal silicon wafers were then sequentially cleaned, texturized, subjected to front-side boron diffusion, and etched and alkaline polished processes.

[0072] Step 2: Introduce O2 gas at a flow rate of 35000 sccm on the back side of the silicon wafer and deposit a 1.5 nm tunneling oxide layer at a temperature of 600 °C; then introduce SiH4 gas at a flow rate of 2000 sccm and deposit a 150 nm first amorphous silicon layer at a temperature of 550 °C; then introduce POCl3 gas at a flow rate of 1500 sccm and deposit a 150 nm PSG layer at a temperature of 800 °C.

[0073] Step 3: Perform phosphorus diffusion annealing on the silicon wafer. Place the silicon wafer in a tube diffusion furnace and anneal at 900℃ under a nitrogen atmosphere to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 150nm and a sheet resistance of 100Ω / cm. 2 ;

[0074] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0075] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0076] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0077] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0078] Comparative Example 2

[0079] Comparative Example 2 provides a method for preparing a TOPCon solar cell, comprising the following steps:

[0080] Step 1: Select a thickness of 150μm and a resistivity of 5Ω / cm. 2 The N-type single crystal silicon wafers were then sequentially cleaned, texturized, subjected to front-side boron diffusion, and etched and alkaline polished processes.

[0081] Step 2: O2 gas is introduced onto the back of the silicon wafer at a flow rate of 35000 sccm, and a 1.5 nm tunneling oxide layer is deposited at 600°C. Then, SiH4 gas is introduced at a flow rate of 2000 sccm, and a 30 nm first amorphous silicon layer is deposited at 550°C. Next, O2 gas is introduced again at a flow rate of 35000 sccm, and a 1.5 nm tunneling oxide layer is deposited at 600°C. Then, SiH4 gas is introduced again at a flow rate of 2000 sccm, and a 120 nm second amorphous silicon layer is deposited at 550°C. Finally, POCl3 gas is introduced at a flow rate of 1500 sccm, and a 50 nm PSG layer is deposited at 800°C.

[0082] Step 3: Perform phosphorus diffusion annealing on the silicon wafer. Place the silicon wafer in a tube diffusion furnace and anneal at 900℃ under a nitrogen atmosphere to obtain a phosphorus-doped polycrystalline silicon layer with a thickness of 150nm and a sheet resistance of 100Ω / cm. 2 ;

[0083] Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer.

[0084] Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer;

[0085] Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer;

[0086] Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact.

[0087] The performance of the solar cells obtained in the above embodiments and comparative examples is tested below, and the results are as follows:

[0088] Table 1. Electrical performance test results of the solar cells prepared in the examples and comparative examples.

[0089] Example 1 25.899 728.87 13.975 85.12 2477 1.015 0.034 Example 2 26.028 730.24 13.987 85.31 2486 1.013 0.047 Example 3 25.944 728.65 13.989 85.21 2481 1.028 0.039 Comparative Example 1 25.804 727.45 13.969 85.01 2667 1.028 0.037 Comparative Example 2 25.851 728.17 13.969 85.08 2869 1.028 0.045 Comparative Example 1 is a TOPCon solar cell obtained by conventional fabrication methods; Comparative Example 2 is a TOPCon solar cell obtained by depositing a stacked structure of tunneling oxide layer / first amorphous silicon layer / tunneling oxide layer / second amorphous silicon layer / PSG layer on the back of a silicon wafer and then performing phosphorus diffusion; Examples 1-3 are TOPCon solar cells prepared according to the present invention. As can be seen from the comparison in Table 1 above, compared with Comparative Example 1, the TOPCon solar cells prepared in Examples 1-3 of this application have higher Voc and FF than Comparative Example 2 because they sequentially deposit a stacked structure of tunneling oxide layer / first amorphous silicon layer / first PSG layer / second amorphous silicon layer / second PSG layer on the back of a silicon wafer, and then uniformly distribute phosphorus atoms in the polycrystalline silicon layer at a high concentration through high-temperature diffusion. Simultaneously, the presence of the first PSG layer avoids the problem of phosphorus atom diffusion. Compared with Comparative Example 2, the PSG layer in Examples 1-3 of this application provides a certain amount of phosphorus atoms. After high-temperature diffusion, there is a certain phosphorus doping concentration at the tunneling layer interface, which leads to band bending at the interface, changes the electric field distribution at the interface, and exerts a certain field passivation effect at the interface. Therefore, the Voc in the examples is higher than that in Comparative Example 2.

[0090] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A method for fabricating a TOPCon solar cell, characterized in that, Includes the following steps, Step 1: Select silicon wafers and perform cleaning and texturing, front-side boron diffusion, and etching and alkaline polishing treatments in sequence; Step 2: A tunneling oxide layer, a first amorphous silicon layer, a first PSG layer, a second amorphous silicon layer, and a second PSG layer are sequentially deposited on the back side of the silicon wafer to form a stacked structure. Step 3: Perform phosphorus diffusion annealing on the silicon wafer to form a phosphorus-doped polycrystalline silicon layer on the tunneling oxide layer; Step 4: Remove the front / side tunneling oxide layer and polysilicon layer, as well as the front BSG layer and the back PSG layer from the silicon wafer. Step 5: Deposit an aluminum oxide layer on the front side of the silicon wafer; Step 6: Deposit silicon nitride antireflection layers on the front and back sides of the silicon wafer; Step 7: Print metal electrodes on the silicon wafer to form a metal region in contact with the metal electrodes, and sinter the metal electrodes with the silicon wafer to form an ohmic contact; The first PSG layer and the second PSG layer were deposited at a temperature of 750~850℃; The thickness of the tunneling oxide layer is 1~2nm, the thickness of the first amorphous silicon layer is 10~50nm, the thickness of the first PSG layer is 1~10nm, the thickness of the second amorphous silicon layer is 50~200nm, and the thickness of the second PSG layer is 30~80nm. The phosphorus-doped polysilicon layer comprises a first phosphorus-doped polysilicon layer and a second phosphorus-doped polysilicon layer, wherein the thickness of the phosphorus-doped polysilicon layer is 60~250 nm and the sheet resistance is 50~150 Ω / cm. 2 ; The phosphorus doping concentration of the first phosphorus-doped polysilicon layer is lower than that of the second phosphorus-doped polysilicon layer; the doping concentration of the second phosphorus-doped polysilicon layer is (0.1~1.5) E21atom / cm. 3 The doping concentration of the first phosphorus-doped polycrystalline silicon layer is (1~10) E19atom / cm. 3 .

2. The preparation method according to claim 1, characterized in that, In the stacked structure of step two, the thickness of the first amorphous silicon layer is less than the thickness of the second amorphous silicon layer.

3. The preparation method according to claim 1, characterized in that, Step two, specifically, involves depositing the multilayer structure as follows: introducing O2 gas at a flow rate of 30,000-40,000 sccm and depositing the tunneling oxide layer at a temperature of 550-650°C; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the first amorphous silicon layer at a temperature of 500-600°C; then introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the first PSG layer; then introducing SiH4 gas at a flow rate of 1,500-2,500 sccm and depositing the second amorphous silicon layer at a temperature of 500-600°C; and finally introducing POCl3 gas at a flow rate of 1,000-2,000 sccm and depositing the second PSG layer.

4. The preparation method according to claim 1, characterized in that, The phosphorus diffusion annealing process in step three specifically includes: placing the silicon wafer in a tube diffusion furnace and annealing it at a temperature of 850~950℃ under a nitrogen atmosphere to obtain the phosphorus-doped polycrystalline silicon layer.

5. The preparation method according to claim 1, characterized in that, The step seven, in which the metal electrode makes ohmic contact with the back of the silicon wafer, specifically includes the metal electrode passing through the antireflection layer on the back of the silicon wafer and contacting the phosphorus-doped polycrystalline silicon layer.

6. A TOPCon solar cell, characterized in that, It is prepared by the preparation method described in any one of claims 1 to 5.