A sintering method of a solar cell

Abstract

The present application relates to the field of photovoltaic technology, and discloses a sintering method of a solar cell, which comprises the following steps: applying voltage or current to both ends of the same polarity auxiliary grid on the surface of a silicon substrate sample, and controlling the application time of the voltage or current to be less than or equal to 120s, and the absolute value of the applied voltage to be less than or equal to 30V (or the absolute value of the applied current to be less than or equal to 20A), so that a large amount of Joule heat is generated on the auxiliary grid, and the non-conductive layer such as a passivation layer in the auxiliary grid area is etched away by using the Joule heat, and then the auxiliary grid is in contact with the conductive layer, so that the sintering effect of the grid line area and the non-grid line area is realized. Moreover, the sintering method of the solar cell does not need mask alignment and does not need to be used with laser. Therefore, the sintering method of the solar cell can ensure that the metallized area realizes excellent contact, effectively avoid the damage of the non-metallized area and the passivation decay effect, improve the cell efficiency, and simplify the process and reduce the cost.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically to a sintering method for solar cells. Background Technology

[0002] Metallization in existing solar cells typically employs a sintering process to achieve contact between the metal grid lines and the carrier transport layer. However, the high-temperature sintering process can damage the internal structure of the solar cell, leading to a loss of efficiency. For example, TOPCon solar cells use an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer as passivation contact structures. These passivation contact structures (i.e., the ultrathin tunneling oxide layer and the doped polycrystalline silicon layer) exhibit significant degradation at excessively high temperatures. Furthermore, existing sintering furnaces can only perform integral sintering of both the metal and non-metal grid line regions (i.e., indiscriminate sintering of both regions). This results in significant degradation of the passivation contact structure in the non-metal grid line regions after sintering, further reducing cell efficiency.

[0003] To address this, existing technologies, such as those disclosed in CN119277840A, achieve sintering by applying a bias voltage to the sub-grid and performing laser-assisted sintering at the sub-grid. According to the description and accompanying drawings of the technology described in CN119277840A, the applied bias voltage is applied to the positive and negative grid lines of the solar cell, and this bias voltage is a reverse bias (the conductive support device carries the solar cell and is electrically connected to the back grid lines of the solar cell; the probe is electrically connected to the front sub-grid lines of the solar cell; and to achieve laser-assisted sintering, a reverse bias voltage must be applied). Furthermore, it requires the use of a laser to generate a large number of photogenerated carriers to achieve assisted sintering (the principle is to use the laser to generate a large number of photogenerated carriers at the grid lines, and with the help of a reverse bias voltage, separate the photogenerated carriers to form a large current, causing a large amount of Joule heat at the contact point between the grid lines and the cell, thus achieving a sintering effect). Therefore, the implementation process of this technology is relatively complicated and the process is complex (for example, it requires the addition of conductive support devices and other structures, and the process of applying bias voltage is also more complicated. In addition, it also requires laser operation, and the laser and bias voltage need to be adapted and adjusted in a complicated manner), the sintering cost is high (for example, its conductive device requires the addition of conductive support devices and other structures, which increases the cost, and additional laser equipment is also required, which further increases the cost), and the laser can still cause damage.

[0004] Alternatively, existing technologies, such as CN117637916A, employ a mask method for temperature-controlled sintering of the solar cells. While the metallized regions of the solar cell are sintered at high temperatures, the non-metallized regions are sintered at low temperatures. This temperature-controlled method uses a mask, which not only adds a masking process, but also makes precise mask alignment difficult and requires additional mask carriers, resulting in a complex process and high sintering costs. Furthermore, the non-metallized regions still undergo sintering (although at a lower temperature), leading to some sintering damage, which is detrimental to improving battery efficiency.

[0005] Therefore, how to ensure good contact in the metallized area while effectively avoiding damage and passivation attenuation in the non-metallized area, and at the same time simplifying the process and reducing costs, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a sintering method for solar cells.

[0007] Based on this, the present invention discloses a sintering method for solar cells, comprising the following steps:

[0008] Step 1: Prepare a silicon substrate sample with a conductive layer and a passivation layer sequentially fabricated on its surface;

[0009] Step 2: Print sub-gates on the surface of the silicon substrate sample and dry; wherein, the surface of the silicon substrate sample is the front and / or back side of the silicon substrate sample;

[0010] Step 3: Apply voltage or current to both ends of the same polarity sub-gate on the surface of the silicon substrate sample to generate Joule heating on the sub-gate, and use Joule heating to etch away the passivation layer in the sub-gate region to make the sub-gate contact with the conductive layer; wherein, the voltage or current application time is ≤120s; the absolute value of the applied voltage is ≤30V, or the absolute value of the applied current is ≤20A.

[0011] Preferably, the conductive layers on the same surface of the silicon substrate sample are of the same conductivity type, namely P-type or N-type.

[0012] In step 2, several identical polarity sub-gates are printed on the same surface of the silicon substrate sample at intervals.

[0013] More preferably, in step 3, a voltage or current is applied to both ends of each sub-gate of the same polarity on the same surface of the silicon substrate sample to generate Joule heating on the sub-gate.

[0014] More preferably, in step 3, two conductive tools are pressed onto the two ends of each sub-gate of the same polarity, and voltage or current is applied to the two conductive tools to generate Joule heating on the sub-gate; the two conductive tools are two conductive rods or two rows of probes.

[0015] Preferably, the conductive layers on the same surface of the silicon substrate sample are of the same conductivity type, namely P-type or N-type.

[0016] In step 2, several sub-gates of the same polarity are printed on the same surface of the silicon substrate sample, and the several sub-gates on the same surface of the silicon substrate sample are connected end to end in sequence to form a series sub-gate.

[0017] In this invention, preferably, the conductive layers on the same surface of the silicon substrate sample are all of the same conductivity type, such as all P-type or all N-type; therefore, the sub-gates on the same surface of the silicon substrate sample are either all positive or all negative. Thus, the voltage or current in step 3 of this invention is applied to the sub-gates of the same polarity on the surface of the silicon substrate sample (either applied to the negative sub-gate, or either applied to the positive sub-gate), and there are no requirements regarding the positive or negative polarity of the applied voltage or current.

[0018] More preferably, in step 3, a voltage or current is applied across the two ends of the series sub-gate on the same surface of the silicon substrate sample to generate Joule heating on the series sub-gate.

[0019] More preferably, in step 3, two conductive tools are pressed against the two ends of a series sub-gate, and voltage or current is applied to the two conductive tools to generate Joule heating on the series sub-gate; the two conductive tools are two conductive rods or two probes.

[0020] More preferably, the conductive tool is made of an alloy of one or more of tungsten, gold, silver, aluminum, and copper.

[0021] Preferably, in step 3, for the same polarity sub-gate on the same surface of the silicon substrate sample, the voltage or current is applied ≥1 time, and the voltage or current applied each time is one of constant, gradual, or abrupt.

[0022] Preferably, before step 2, the method further includes: printing a main gate on the surface of the silicon substrate sample and drying it;

[0023] Alternatively, after step 3, the process may include: printing the master gate on the surface of the silicon substrate sample and drying it.

[0024] More preferably, a plurality of identical polarity main gates are printed on the same surface of the silicon substrate sample at intervals, and identical polarity secondary gates on the same surface of the silicon substrate sample intersect with and are electrically connected to identical polarity main gates.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] The sintering method of the solar cell of the present invention applies a voltage or current to both ends of a sub-gate of the same polarity on the surface of a silicon substrate sample, and controls the amount and duration of the applied voltage or current to generate a potential difference on the sub-gate, thereby generating a large amount of Joule heat on the sub-gate. This Joule heat is used to etch away non-conductive layers such as passivation layers in the sub-gate region, thereby making contact between the sub-gate and the conductive layer, achieving a better sintering effect of sintering the gate line region and not sintering the non-gate line region.

[0027] Moreover, compared to the prior art such as CN119277840A (which requires the bias voltage to be applied synchronously to the positive and negative grid lines of the solar cell, and the bias voltage must be reverse biased, and also requires laser-assisted sintering), the sintering method of the present invention applies the voltage or current in step 3 to the sub-grid of the same polarity, and the applied voltage or current has no positive or negative requirements, and does not require the use of a laser; and compared to the prior art such as CN117637916A (which requires masking of the non-metallized region), the sintering method of the present invention does not require mask alignment. Therefore, the sintering method of the present invention simplifies the sintering process of existing technologies such as CN119277840A and CN117637916A, reduces sintering costs, and can also achieve better sintering results for the grid line region and the non-grid line region. In this way, while ensuring excellent contact in the metallized region, it can effectively avoid damage and passivation attenuation in the non-metallized region, thereby effectively avoiding efficiency loss of the cell in the sintering process and improving the photoelectric conversion efficiency of the solar cell. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a solar cell sintering method according to Example 1, in which current is applied to both ends of each sub-grid.

[0029] Figure 2 This is a schematic diagram of a structure in which current is applied to both ends of a series sub-grid in a sintering method for a solar cell according to Example 2.

[0030] Reference numerals: 1. Silicon substrate sample; 2. Sub-gate; 21. Current application terminal 1; 22. Current application terminal 2; 3. Main gate. Detailed Implementation

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Example 1

[0033] This embodiment describes a sintering method for solar cells, taking an N-type TOPCon solar cell as an example (of course, besides TOPCon solar cells, this method can also be used to sinter the grid lines of other existing types of solar cells). Figure 1 It includes the following steps:

[0034] Step 1: Print several main gates 3 on the back side of the silicon substrate sample 1, which has been pre-prepared with conductive and passivation layers, and then dry it.

[0035] In step 1, several main grids 3 on the back side are arranged at intervals. The fabrication process of this silicon substrate sample 1 with conductive and passivation layers refers to the existing fabrication process of N-type TOPCon solar cells before metallization, so it will not be described in detail here.

[0036] Step 2: Continue printing several sub-gates 2 on the back side of silicon substrate sample 1, and then dry.

[0037] In step 2, several sub-gates 2 on the back side are also arranged at intervals; moreover, the sub-gates 2 on the back side intersect with the main gate 3 (e.g., the sub-gates 2 on the back side intersect the main gate 3 perpendicularly) and are electrically connected (e.g., ...). Figure 1 (As shown).

[0038] In practice, grid line paste (such as main grid paste or sub-grid paste) is printed onto the surface (such as the back or front) of silicon substrate sample 1 in a specific pattern. The specific pattern formed on the surface of silicon substrate sample 1 generally includes several lines, which are grid lines.

[0039] Step 3: Apply a constant current source (i.e., a power supply that provides a constant output current) to both ends of each sub-gate 2 on the back side of the silicon substrate sample 1. After 10s, apply a current of 0.6A for 3s to generate a large amount of Joule heat on the back sub-gate 2. Use the Joule heat to etch away the back passivation layer of the back sub-gate area so that the back sub-gate 2 can come into contact with the back conductive layer (taking TOPCon solar cells as an example, its back conductive layer is the doped polycrystalline silicon layer of the passivation contact structure).

[0040] In this embodiment, the entire conductive layer on the back side is of the same conductivity type.

[0041] Step 4: Print several main gates 3 on the front side of silicon substrate sample 1 and dry them.

[0042] In step 4, several main grids 3 on the front are arranged at intervals.

[0043] Step 5: Continue printing several sub-gates 2 on the front side of silicon substrate sample 1, and then dry.

[0044] In step 5, the several sub-gates 2 on the front side are also arranged at intervals; moreover, the sub-gates 2 on the front side intersect with the main gate 3 (e.g., perpendicularly) and are electrically connected (e.g., ...). Figure 1 (As shown).

[0045] In this embodiment, both the main grid 3 and the sub-grid 2 of the solar cell are silver grids. The number of main grids 3 and sub-grids 2, their polarity, and their distribution on the silicon substrate sample 1, as well as the silicon substrate sample 1 used (including the passivation layer and conductive layer thereon), are all based on existing N-type TOPCon solar cells, and therefore will not be described in detail here.

[0046] Step 6: Apply a constant current source to both ends of each sub-gate 2 on the front side of the silicon substrate sample 1 with a current of 0.3A for 10s, and then apply a current of 0.6A for 3s to generate a large amount of Joule heat on the front sub-gate 2. Use the Joule heat to etch away the front passivation layer of the front sub-gate area so that the front sub-gate 2 can contact the front conductive layer.

[0047] In this embodiment, the entire front conductive layer is of the same conductivity type, and the conductivity types of the front conductive layer and the back conductive layer are opposite.

[0048] In steps 3 and 6, two conductive rods or two rows of probes (such as two rows of silver probes) are pressed onto the two ends of each sub-gate 2, and the two output terminals of the constant current source are applied to these two conductive rods or two rows of probes, respectively, to generate a potential difference on the sub-gate 2 and allow current to flow through it (such as...). Figure 1 The silicon substrate sample 1 shown has current applied to each sub-gate on the same surface through two rows of silver probes, with current applied to the first current terminal 21 and the second current terminal 22.

[0049] After the above steps 1-6, other existing follow-up processes such as EL screening (electroluminescence screening) and IV testing (current-voltage characteristic testing) are continued to be completed to obtain the solar cell of this embodiment.

[0050] Example 2

[0051] This embodiment describes a sintering method for a solar cell, taking an N-type TOPCon solar cell as an example, involving... Figure 2 It includes the following steps:

[0052] Step 1: Print several sub-gates 2 on the back of the silicon substrate sample 1, which has been pre-prepared with conductive and passivation layers, and then dry it.

[0053] In step 1, several sub-gates 2 on the back side are connected end to end in sequence to form a series sub-gate on the back side of the silicon substrate sample 1.

[0054] Step 2: Apply a current of 0.3A to both ends of the series sub-gate on the back side using a constant current source for 10s, and then continue to apply a current of 0.6A for 3s to generate a large amount of Joule heat in the series sub-gate on the back side. Use the Joule heat to etch away the back passivation layer in the series sub-gate area on the back side, so that the series sub-gate on the back side can contact the back conductive layer (taking TOPCon solar cells as an example, its back conductive layer is the doped polycrystalline silicon layer of the passivation contact structure).

[0055] In this embodiment, the entire conductive layer on the back side is of the same conductivity type.

[0056] Step 3: Print several main gates 3 on the back of the silicon substrate sample 1 and dry them.

[0057] In step 3, there are also multiple back main gates 3, which are distributed at intervals. Each back main gate 3 is electrically connected to the series sub-gates on the back. The back main gates 3 intersect with the sub-gates 2 (e.g., perpendicularly).

[0058] Step 4: Print several sub-gates 2 on the front side of silicon substrate sample 1 and dry them.

[0059] In step 4, several sub-gates 2 on the front side are connected end to end to form a series sub-gate on the front side of the silicon substrate sample 1.

[0060] Step 5: Apply a current of 0.3A to both ends of the series sub-gate on the front side using a constant current source for 10s, and then continue to apply a current of 0.6A for 3s to generate a large amount of Joule heat in the series sub-gate on the front side. Use the Joule heat to etch away the front passivation layer in the series sub-gate area on the front side, so that the series sub-gate on the front side can contact the front conductive layer (taking TOPCon solar cells as an example, its back conductive layer is the doped polycrystalline silicon layer of the passivation contact structure).

[0061] In this embodiment, the entire front conductive layer is of the same conductivity type, and the conductivity types of the front conductive layer and the back conductive layer are opposite.

[0062] In steps 2 and 5, two conductive rods or two probes (such as two silver probes) are pressed against the two ends of a series sub-gate, and the two output terminals of a constant current source are applied to these two conductive rods or two probes, respectively, to create a potential difference across the series sub-gate and allow current to flow through it (e.g., ...). Figure 2 The silicon substrate sample 1 shown has current applied to its tandem subgate on the same surface via two rows of silver probes at current application terminals 21 and 22.

[0063] Step 6: Print several main gates 3 on the front side of the silicon substrate sample 1 and dry them.

[0064] In step 6, there are also multiple front main gates 3, which are distributed at intervals. Each front main gate 3 is electrically connected to the front series sub-gates. The front main gates 3 intersect with the sub-gates 2 (e.g., perpendicularly).

[0065] In practice, the material, number of roots, polarity, and distribution position of the main gate 3 and the sub-gate 2 on the silicon substrate sample 1 in Example 2, as well as the silicon substrate sample 1 used (including the passivation layer and conductive layer thereon), are all consistent with those in Example 1.

[0066] After the above steps 1-6, other existing follow-up processes such as EL screening and IV testing are completed to obtain the solar cell of this embodiment.

[0067] Comparative Example 1

[0068] This comparative example describes a sintering method for a solar cell, taking an N-type TOPCon solar cell as an example, which includes the following steps:

[0069] Step 1: Print several main gates on the back of the silicon substrate sample with the pre-prepared conductive and passivation layers, and then dry it.

[0070] In step 1, several main grids on the back are arranged at intervals.

[0071] Step 2: Continue printing several sub-gates on the back side of the silicon substrate sample and then dry it.

[0072] In step 2, several sub-gates on the back side are also arranged at intervals; moreover, the sub-gates on the back side intersect the main gate perpendicularly and are electrically connected.

[0073] Step 3: Print several main gates on the front side of the silicon substrate sample and dry it.

[0074] In step 3, several main grids on the front are arranged at intervals.

[0075] Step 4: Continue printing several sub-gates on the front side of the silicon substrate sample and then dry it.

[0076] In step 4, several sub-gates on the front side are also arranged at intervals; moreover, the sub-gates on the front side intersect the main gate perpendicularly and are electrically connected.

[0077] Step 5: Use a sintering furnace to sinter the entire silicon substrate sample after step 4 at high temperature (peak sintering temperature is 720℃ and sintering time is 1min) so that the back sub-gate burns through the back passivation layer to contact the back conductive layer, and so that the front sub-gate burns through the front passivation layer to contact the front conductive layer.

[0078] In this comparative example, the entire conductive layer on the back side is of the same conductivity type; the entire conductive layer on the front side is of the same conductivity type, and the conductivity types of the conductive layer on the front side and the conductive layer on the back side are opposite.

[0079] In practice, the material, number of roots, polarity, and distribution position of the main gate and sub-gate of Comparative Example 1, as well as the silicon substrate sample used (including the passivation layer and conductive layer thereon), are consistent with those of Example 1.

[0080] After the above steps 1-5, other existing follow-up processes such as EL screening and IV testing are continued to complete, thus obtaining the solar cell of this comparative example.

[0081] Performance testing

[0082] The performance of the solar cells of Examples 1-2 and Comparative Example 1 were tested respectively, and the test results are shown in Table 1:

[0083] Table 1

[0084] Comparative Example 1 26.45 742.3 14.319 83.31 Example 1 26.49 742.5 14.322 83.39 Example 2 26.48 742.4 14.320 83.36

[0085] As can be seen from Table 1, compared with the existing method of high-temperature sintering using a sintering furnace, the solar cells prepared by the sintering methods of Examples 1 and 2 of this invention have improved fill factor (FF), short-circuit current (Isc), open-circuit voltage (Voc), and photoelectric conversion efficiency (referred to as cell efficiency, denoted by Eta).

[0086] Furthermore, compared to existing technologies such as CN119277840A (where the bias voltage needs to be applied synchronously to the positive and negative grid lines of the solar cell, and the bias voltage must be reverse biased, and laser-assisted sintering is also required), the sintering methods of Embodiments 1 and 2 of the present invention apply the voltage or current in step 3 to the sub-grid of the same polarity, and the applied voltage or current has no positive or negative requirements, and does not require the use of a laser; and compared to existing technologies such as CN117637916A (which requires masking of the non-metallized region), the sintering methods of Embodiments 1 and 2 of the present invention do not require mask alignment. Therefore, the sintering methods of Embodiments 1 and 2 of the present invention achieve better sintering effects by sintering the grid line region and not sintering the non-grid line region (the metallized region achieves excellent contact and effectively avoids damage and passivation attenuation of the non-metallized region), thereby improving the photoelectric conversion efficiency of the solar cell. At the same time, they also simplify the sintering process of existing technologies such as CN119277840A and CN117637916A and reduce the sintering cost.

[0087] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0088] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A sintering method for a solar cell, characterized in that, Includes the following steps: Step 1: Prepare a silicon substrate sample with a conductive layer and a passivation layer sequentially fabricated on its surface; Step 2: Print sub-gates on the surface of the silicon substrate sample and dry; wherein, the surface of the silicon substrate sample is the front and / or back side of the silicon substrate sample; Step 3: Apply voltage or current to both ends of the same polarity sub-gate on the surface of the silicon substrate sample to generate Joule heating on the sub-gate, and use Joule heating to etch away the passivation layer in the sub-gate region to make the sub-gate contact with the conductive layer; wherein, the voltage or current application time is ≤120s; the absolute value of the applied voltage is ≤30V, or the absolute value of the applied current is ≤20A.

2. The sintering method for a solar cell according to claim 1, characterized in that, The conductive layers on the same surface of the silicon substrate sample have the same conductivity type, which is either P-type or N-type. In step 2, several identical polarity sub-gates are printed on the same surface of the silicon substrate sample at intervals.

3. The sintering method for a solar cell according to claim 2, characterized in that, In step 3, a voltage or current is applied to both ends of each sub-gate of the same polarity on the same surface of the silicon substrate sample to generate Joule heating on the sub-gate.

4. The sintering method for a solar cell according to claim 3, characterized in that, In step 3, two conductive tools are pressed onto the two ends of each sub-gate of the same polarity, and voltage or current is applied to the two conductive tools to generate Joule heating on the sub-gate; the two conductive tools are two conductive rods or two rows of probes.

5. The sintering method for a solar cell according to claim 1, characterized in that, The conductive layers on the same surface of the silicon substrate sample have the same conductivity type, which is either P-type or N-type. In step 2, several sub-gates of the same polarity are printed on the same surface of the silicon substrate sample, and the several sub-gates on the same surface of the silicon substrate sample are connected end to end in sequence to form a series sub-gate.

6. The sintering method for a solar cell according to claim 5, characterized in that, In step 3, a voltage or current is applied across the two ends of the series sub-gate on the same surface of the silicon substrate sample to generate Joule heating on the series sub-gate.

7. The sintering method for a solar cell according to claim 6, characterized in that, In step 3, two conductive tools are pressed against the two ends of a series sub-gate, and voltage or current is applied to the two conductive tools to generate Joule heating on the series sub-gate; the two conductive tools are two conductive rods or two probes.

8. A sintering method for a solar cell according to claim 4 or 7, characterized in that, The conductive tool is made of an alloy composed of one or more of the following materials: tungsten, gold, silver, aluminum, and copper.

9. The sintering method for a solar cell according to claim 1, characterized in that, In step 3, for the same polarity sub-gate on the same surface of the silicon substrate sample, the voltage or current is applied ≥1 time, and the voltage or current applied each time is one of constant, gradual, or abrupt.

10. A sintering method for a solar cell according to claim 1, characterized in that, Before step 2, the process also includes: printing the main gate on the surface of the silicon substrate sample and drying it; Alternatively, after step 3, the process may include: printing the main gate on the surface of the silicon substrate sample and drying it; The silicon substrate sample has several main gates of the same polarity printed on the same surface, spaced apart from each other. The secondary gates of the same polarity on the same surface of the silicon substrate sample intersect with and are electrically connected to the main gates of the same polarity.

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